SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A2E8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_CASLAT_LIN_F2 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PI_TPARITY_ERROR_CMD_INHIBIT_F2 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_CA_PARITY_LAT_F2 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:23 | RESERVED | NONE | 0h | Reserved |
| 22:16 | PI_CASLAT_LIN_F2 | R/W | 0h | Sets latency from read command sent to data received from/to controller for frequency set 2. Bit [0] is half-cycle increment and the upper bits define memory CAS latency for the controller. Reset Source: ctl_amod_g_rst_n |
| 15:8 | PI_TPARITY_ERROR_CMD_INHIBIT_F2 | R/W | 0h | Defines the window after the PI receives a parity error during which DRAM commands will not execute for frequency set 2. Reset Source: ctl_amod_g_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | PI_CA_PARITY_LAT_F2 | R/W | 0h | DRAM CA parity latency value in cycles for frequency set 2. Reset Source: ctl_amod_g_rst_n |