SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
| Instance | MAIN | MCU | WKUP |
|---|---|---|---|
| MMCSD0 | ✓ |
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | Dependencies |
|---|---|---|---|---|---|---|---|
| MMCSD0 | PSC0 | GP_CORE | LPSC_main_emmc8b | 20 | OFF | YES | LPSC_main_ip |
| Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
|---|---|---|---|---|
| MMCSD0 | ICLK | MAIN_SYSCLK0/2 | interface clock | |
| MMCSD0 | FCLK | MAIN_PLL0_HSDIV5_CLKOUT | MAIN_CTRL_MMR_CFG0_EMMC0_CLKSEL[0:0]=0 | functional clock |
| MMCSD0 | FCLK | MAIN_PLL2_HSDIV2_CLKOUT | MAIN_CTRL_MMR_CFG0_EMMC0_CLKSEL[0:0]=1 | functional clock |
| Module Instance | Source | Description |
|---|---|---|
| MMCSD0 | PSC0 | MMCSD0 reset |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| MMCSD0 | MMCSD0_emmcss_intr_0 | GICSS0_spi_165 | GICSS0 | MMCSD0 interrupt request | level |
| MMCSD0 | MMCSD0_emmcss_intr_0 | WKUP_R5FSS0_CORE0_intr_161 | WKUP_R5FSS0_CORE0 | MMCSD0 interrupt request | level |
| MMCSD0 | MMCSD0_emmcss_intr_0 | MCU_R5FSS0_CORE0_cpu0_intr_161 | MCU_R5FSS0_CORE0 | MMCSD0 interrupt request | level |
| MMCSD0 | MMCSD0_emmcss_rxmem_corr_err_lvl_0 | ESM0_esm_lvl_event_54 | ESM0 | MMCSD0 interrupt request | level |
| MMCSD0 | MMCSD0_emmcss_rxmem_uncorr_err_lvl_0 | ESM0_esm_lvl_event_55 | ESM0 | MMCSD0 interrupt request | level |
| MMCSD0 | MMCSD0_emmcss_txmem_corr_err_lvl_0 | ESM0_esm_lvl_event_56 | ESM0 | MMCSD0 interrupt request | level |
| MMCSD0 | MMCSD0_emmcss_txmem_uncorr_err_lvl_0 | ESM0_esm_lvl_event_57 | ESM0 | MMCSD0 interrupt request | level |