SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A0E4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_CALVL_SEQ_EN | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_RESERVED6 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_RESERVED5 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_CALVL_CS | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED | NONE | 0h | Reserved |
| 25:24 | PI_CALVL_SEQ_EN | R/W | 0h | Specifies which CA training patterns will be used. Set to 0 for pattern 0 only, set to 1 for patterns 0 and 1, set to 2 for patterns 0, 1 and 2, or set to 3 for all patterns. Reset Source: ctl_amod_g_rst_n |
| 23:20 | RESERVED | NONE | 0h | Reserved |
| 19:16 | PI_RESERVED6 | R/W | 0h | Reserved |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | PI_RESERVED5 | R/W | 0h | Reserved |
| 7:2 | RESERVED | NONE | 0h | Reserved |
| 1:0 | PI_CALVL_CS | R/W | 0h | Specifies the target chip select for the CA training operation initiated through the CALVL_REQ parameter. Reset Source: ctl_amod_g_rst_n |