SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C0B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_FIFO_PTR_OBS_0 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_MANUAL_CLEAR_0 | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CALVL_VREF_DRIVING_SLICE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | RESERVED | NONE | 0h | Reserved |
| 23:16 | PHY_FIFO_PTR_OBS_0 | R | 0h | Observation register containing read entry FIFO pointers for slice 0. READ-ONLY Reset Source: ctl_amod_g_rst_n |
| 15:14 | RESERVED | NONE | 0h | Reserved |
| 13:8 | SC_PHY_MANUAL_CLEAR_0 | W | 0h | Manual reset/clear of internal logic for slice 0. Bit [0] initiates manual setup of the read DQS gate. Bit [1] is reset of read entry FIFO pointers. Bit [2] is reset of controller delay min/max lock values. Bit [3] is manual reset of controller delay unlock counter. Bit [4] is reset of leveling error bit in the leveling status registers. Bit [5] is clearing of the gate tracking observation register. Set each bit to 1 to initiate/reset. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PHY_CALVL_VREF_DRIVING_SLICE_0 | R/W | 0h | Indicates if slice 0 is used to drive the VREF value to the device during CA training. Reset Source: ctl_amod_g_rst_n |