SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A1B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PI_BIST_DATA_MASK_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PI_BIST_DATA_MASK_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PI_BIST_DATA_MASK_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PI_BIST_DATA_MASK_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | PI_BIST_DATA_MASK_0 | R/W | 0h | Mask applied to data for BIST error checking. Bit [0] controls memory data path bit [0], bit [1] controls memory data path bit [1], etc. The mask range is the data transfer size in each memory clock cycle [The data on a rising edge and a failing edge]. Set each bit to 1 to mask. Reset Source: ctl_amod_g_rst_n |