SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 8678h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TDFI_PHY_RDLAT_F2 | |||||||
| R/W | |||||||
| 6h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | TDFI_CTRLMSG_RESP_F1 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TDFI_PHY_WRLAT_F1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TDFI_WRCSLAT_F1 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | TDFI_PHY_RDLAT_F2 | R/W | 6h | Defines the DFI tPHY_RDLAT timing parameter [in DFI PHY clocks], the maximum cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion. FC=2 Reset Source: ctl_amod_g_rst_n |
| 23 | RESERVED | NONE | 0h | Reserved |
| 22:16 | TDFI_CTRLMSG_RESP_F1 | R/W | 0h | Defines the DFI tCTRLMSG_RESP timing parameter [in DFI clocks], the maximum number of DFI clocks allowed for dfi_ctrlmsg_ack to assert after dfi_ctrlmsg_req goes high. FC=1 Reset Source: ctl_amod_g_rst_n |
| 15:8 | TDFI_PHY_WRLAT_F1 | R/W | 0h | DFI tPHY_WRLAT timing parameter. This is the number of DFI data phases between a write command and the first assertion of dfi_wrdata_en_pN. FC=1 Reset Source: ctl_amod_g_rst_n |
| 7:0 | TDFI_WRCSLAT_F1 | R/W | 0h | Defines the DFI tPHY_WRCSLAT timing parameter [in DFI PHY clocks], the maximum cycles between a write command and a dfi_wrdata_cs_n assertion. FC=1 Reset Source: ctl_amod_g_rst_n |