SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A0E0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_CALVL_CS_SW | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_CALVL_REQ | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PI_TDFI_PHY_WRLAT | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PI_TDFI_RDDATA_EN | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED | NONE | 0h | Reserved |
| 27:24 | PI_CALVL_CS_SW | R/W | 0h | Specifies the target chip select for the CA training operation initiated through the CALVL_REQ parameter. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | PI_CALVL_REQ | W | 0h | User request to initiate CA training. Set to 1 to trigger. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |
| 15:8 | PI_TDFI_PHY_WRLAT | R | 0h | Holds the calculated DFI tPHY_WRLAT timing parameter [in DFI PHY clocks], the maximum cycles between a write command and a dfi_wrdata_en assertion. READ-ONLY Reset Source: ctl_amod_g_rst_n |
| 7:0 | PI_TDFI_RDDATA_EN | R | 0h | Holds the calculated DFI tRDDATA_EN timing parameter [in DFI PHY clocks], the maximum cycles between a read command and a dfi_rddata_en assertion. READ-ONLY Reset Source: ctl_amod_g_rst_n |