SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A328h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_RDLVL_PAT0_EN_F0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PI_TWR_MPR_F2 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PI_TWR_MPR_F1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PI_TWR_MPR_F0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED | NONE | 0h | Reserved |
| 25:24 | PI_RDLVL_PAT0_EN_F0 | R/W | 0h | Enable PATTERN-0 for read training for frequency set 0. bit1 for normal; bit0 for initialization. Reset Source: ctl_amod_g_rst_n |
| 23:16 | PI_TWR_MPR_F2 | R/W | 0h | Number of cycles after MPR write command and before any other command for frequency set 2. Reset Source: ctl_amod_g_rst_n |
| 15:8 | PI_TWR_MPR_F1 | R/W | 0h | Number of cycles after MPR write command and before any other command for frequency set 1. Reset Source: ctl_amod_g_rst_n |
| 7:0 | PI_TWR_MPR_F0 | R/W | 0h | Number of cycles after MPR write command and before any other command for frequency set 0. Reset Source: ctl_amod_g_rst_n |