SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A140h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_ROW_DIFF | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_BANK_DIFF | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_DBILVL_RESP_MASK | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_PARALLEL_WDQLVL_EN | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:27 | RESERVED | NONE | 0h | Reserved |
| 26:24 | PI_ROW_DIFF | R/W | 0h | Difference between number of address pins available and number being used. Reset Source: ctl_amod_g_rst_n |
| 23:18 | RESERVED | NONE | 0h | Reserved |
| 17:16 | PI_BANK_DIFF | R/W | 0h | Difference between number of bank pins available and number being used. Reset Source: ctl_amod_g_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:8 | PI_DBILVL_RESP_MASK | R/W | 0h | Mask for the dfi_rdlvl_resp signal during read dbi training. Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PI_PARALLEL_WDQLVL_EN | R/W | 0h | Enable per rank parallel Write DQ training for LPDDR4, 1 = enabled. Reset Source: ctl_amod_g_rst_n |