SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
An interrupt enable bit in the MCSPI_IRQENABLE register can be set to enable each event to generate interrupt requests when the corresponding event occurs. Status bits are automatically set by hardware logic conditions.
When an event occurs (the single interrupt line is asserted), the processor must:
The interrupt status bit must always be reset after channel enabling and before events are enabled as interrupt sources.