SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The Arm GIC-500 has built-in SECDED ECC on its memories to protect against errors. The syndrome generation and checking is done internally.
Additionally, the TI GIC wrapper integrates an ECC aggregator (GIC_ECC_AGGR) in order to allow errors to be injected for testing purposes. The generic ECC aggregator functionality is described in Section 12.7.4, ECC Aggregator. Note that the GIC_ECC_AGGR supports only a subset of this functionality.
Table 9-6 shows the memory ID for each ECC endpoint. The corresponding memory ID needs to be written in the GIC_ECC_AGGR_VECTOR[10-0] ECC_VECTOR bit field for proper operation.
ECC Aggregator | Memory ID | ECC Endpoint |
---|---|---|
GIC_ECC_AGGR | 0 | ICB RAM |
1 | ITE RAM | |
2 | LPI RAM | |
3 | VBUSM2AXI bridge | |
4 | AXI2VBUSM read bridge | |
5 | AXI2VBUSM write bridge |