14 Revision History
Changes from October 17, 2023 to February 28, 2024 (from Revision B (October 2023) to Revision C (February 2024))
- Updated A72SS Cache Pre-Warming
section.Go
- removed unnecessary text from diagramGo
- Added detail to main spinlock operationsGo
- Removed unnecessary text in diagramGo
- Updated WKUP_DMSC0 Interrupt MapGo
- Updated MCU_R5FSS0_CORE0 Interrupt MapGo
- Updated MCU_R5FSS0_CORE1 Interrupt MapGo
- Updated GIC500 SPI Interrupt MapGo
- Updated R5FSS0_CORE0 Interrupt MapGo
- Updated R5FSS0_CORE1 Interrupt MapGo
- Added UTC/DRU Note.Go
- Added GPIO XBAR comment for CPU interrupt routing on AM263xGo
- Added comment about AM263x GPIO requiring GPIO XBAR for DMA
events.Go
- Update UART_DLH to 6 bits. Correct Base address for
MCU_UART0/1.Go
- Update the following: UART_MVR: RTL to reset value of 8h.
UART_MDR4: MODE description. UART_EFR2: TIMEOUT_BEHAVE, RHR_OVERRUN, ENDIAN
descriptions. UART_ECR: TX_EN and RX_EN descriptions.Go
- Removed CPSW_SS_SGMII_MODE_REG registerGo
- Updated CPSW_SS_RGMII_STATUS_REG register offset from 18h to
30hGo
- Removed Note from XGIG bit in
CPSW_PN_MAC_CONTROL_REG_k Register Description
table.Go
- Changed OTFA references to OTFE.Go
- Remove misleading statement: Supports dual Quad-SPI mode for fast
boot applications.Go
- (OSPI Environment): Updated RESETn_OUT signal descriptions to show pins
operate as active lowGo
- Removed GPMC Memory Regions section.Go
- (RTI Digital Watchdog): Added note that this feature is only available for
the WWDT defined modules.Go
- (RTI Digital Windowed Watchdog): Fixed error in RTI Digital Windowed
Watchdog Operation Block Diagram.Go