Table 12-1757 lists the memory-mapped registers for the MCU_CPSW0_STAT1 (Port 1). All register offset addresses not listed in Table 12-1757 should be considered as reserved locations and the register contents should not be modified.
Table 12-1477 MCU_CPSW0_STAT1 Instances Table 12-1478 MCU_CPSW0_STAT1 Registers 1.6.9.1 CPSW_STAT1_RXGOODFRAMES Register (Offset = 0003A200h) [reset = 0h]
CPSW_STAT1_RXGOODFRAMES is shown in Figure 12-771 and described in Table 12-1480.
Return to Summary Table.
The total number of good frames received on the port. A good frame is defined to be:
- Any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Had a length of 64 to CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes inclusive
- Had no CRC error, alignment error or code error.
See the CPSW_STAT1_RXALIGNCODEERRORS and CPSW_STAT1_RXCRCERRORS statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic.
Table 12-1479 CPSW_STAT1_RXGOODFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A200h |
Figure 12-771 CPSW_STAT1_RXGOODFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1480 CPSW_STAT1_RXGOODFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of good frames received |
1.6.9.2 CPSW_STAT1_RXBROADCASTFRAMES Register (Offset = 0003A204h) [reset = 0h]
CPSW_STAT1_RXBROADCASTFRAMES is shown in Figure 12-772 and described in Table 12-1482.
Return to Summary Table.
The total number of good broadcast frames received on the port. A good broadcast frame is defined to be:
- Any data or MAC control frame which was destined for only address 0xFFFFFFFFFFFF
- Had a length of CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes inclusive
- Had no CRC error, alignment error or code error.
See the CPSW_STAT1_RXALIGNCODEERRORS and CPSW_STAT1_RXCRCERRORS statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic.
Table 12-1481 CPSW_STAT1_RXBROADCASTFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A204h |
Figure 12-772 CPSW_STAT1_RXBROADCASTFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1482 CPSW_STAT1_RXBROADCASTFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of good broadcast frames received |
1.6.9.3 CPSW_STAT1_RXMULTICASTFRAMES Register (Offset = 0003A208h) [reset = 0h]
CPSW_STAT1_RXMULTICASTFRAMES is shown in Figure 12-773 and described in Table 12-1484.
Return to Summary Table.
The total number of good multicast frames received on the port. A good multicast frame is defined to be:
- Any data or MAC control frame which was destined for any multicast address other than 0xFFFFFFFFFFFF
- Had a length of CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes inclusive
- Had no CRC error, alignment error or code error.
See the CPSW_STAT1_RXALIGNCODEERRORS and CPSW_STAT1_RXCRCERRORS statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic.
Table 12-1483 CPSW_STAT1_RXMULTICASTFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A208h |
Figure 12-773 CPSW_STAT1_RXMULTICASTFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1484 CPSW_STAT1_RXMULTICASTFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of good multicast frames received |
1.6.9.4 CPSW_STAT1_RXPAUSEFRAMES Register (Offset = 0003A20Ch) [reset = 0h]
CPSW_STAT1_RXPAUSEFRAMES is shown in Figure 12-774 and described in Table 12-1486.
Return to Summary Table.
The total number of IEEE 802.3X pause frames received by the port (whether acted upon or not). Such a frame:
- Contained any unicast, broadcast, or multicast address
- Contained the length/type field value 88.08 (hex) and the opcode 0x0001
- Was of length 64 to CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes inclusive
- Had no CRC error, alignment error or code error
- Pause-frames had been enabled on the port (CPSW_PN_MAC_CONTROL_REG[4] TX_FLOW_EN = 1h). The port could have been in either half or full-duplex mode.
See the CPSW_STAT1_RXALIGNCODEERRORS and CPSW_STAT1_RXCRCERRORS statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic.
Table 12-1485 CPSW_STAT1_RXPAUSEFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A20Ch |
Figure 12-774 CPSW_STAT1_RXPAUSEFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1486 CPSW_STAT1_RXPAUSEFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of pause frames received |
1.6.9.5 CPSW_STAT1_RXCRCERRORS Register (Offset = 0003A210h) [reset = 0h]
CPSW_STAT1_RXCRCERRORS is shown in Figure 12-775 and described in Table 12-1488.
Return to Summary Table.
The total number of frames received on the port that experienced a CRC error. Such a frame:
- Was any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Was of length 64 to CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes inclusive
- Had no code/align error,
- Had a CRC error Overruns have no effect upon this statistic.
A CRC error is defined to be:
- A frame containing an even number of nibbles
- Failing the Frame Check Sequence test
Table 12-1487 CPSW_STAT1_RXCRCERRORS InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A210h |
Figure 12-775 CPSW_STAT1_RXCRCERRORS Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1488 CPSW_STAT1_RXCRCERRORS Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of CRC errors frames received. |
1.6.9.6 CPSW_STAT1_RXALIGNCODEERRORS Register (Offset = 0003A214h) [reset = 0h]
CPSW_STAT1_RXALIGNCODEERRORS is shown in Figure 12-776 and described in Table 12-1490.
Return to Summary Table.
The total number of frames received on the port that experienced an alignment error or code error. Such a frame:
- Was any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Was of length 64 to CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes inclusive
- Had either an alignment error or a code error Overruns have no effect upon this statistic. An alignment error is defined to be:
- A frame containing an odd number of nibbles
- Failing the Frame Check Sequence test if the final nibble is ignored
A code error is defined to be a frame which has been discarded because the port's MRXER pin driven with a one for at least one bit-time's duration at any point during the frame's reception.
Note: RFC 1757 etherStatsCRCAlignErrors Ref. 1.5 can be calculated by summing CPSW_STAT1_RXALIGNCODEERRORS and CPSW_STAT1_RXCRCERRORS.
Table 12-1489 CPSW_STAT1_RXALIGNCODEERRORS InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A214h |
Figure 12-776 CPSW_STAT1_RXALIGNCODEERRORS Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1490 CPSW_STAT1_RXALIGNCODEERRORS Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of alignment/code errors received |
1.6.9.7 CPSW_STAT1_RXOVERSIZEDFRAMES Register (Offset = 0003A218h) [reset = 0h]
CPSW_STAT1_RXOVERSIZEDFRAMES is shown in Figure 12-777 and described in Table 12-1492.
Return to Summary Table.
The total number of oversized frames received on the port. An oversized frame is defined to be:
- Was any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Was greater than CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN in bytes
- Had no CRC error, alignment error or code error
See the CPSW_STAT1_RXALIGNCODEERRORS and CPSW_STAT1_RXCRCERRORS statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic.
Table 12-1491 CPSW_STAT1_RXOVERSIZEDFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A218h |
Figure 12-777 CPSW_STAT1_RXOVERSIZEDFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1492 CPSW_STAT1_RXOVERSIZEDFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of oversized frames received |
1.6.9.8 CPSW_STAT1_RXJABBERFRAMES Register (Offset = 0003A21Ch) [reset = 0h]
CPSW_STAT1_RXJABBERFRAMES is shown in Figure 12-778 and described in Table 12-1494.
Return to Summary Table.
The total number of jabber frames received on the port. A jabber frame:
- Was any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Was greater than CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN in bytes
- Had no CRC error, alignment error or code error
See the CPSW_STAT1_RXALIGNCODEERRORS and CPSW_STAT1_RXCRCERRORS statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic.
Table 12-1493 CPSW_STAT1_RXJABBERFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A21Ch |
Figure 12-778 CPSW_STAT1_RXJABBERFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1494 CPSW_STAT1_RXJABBERFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of jabber frames received. |
1.6.9.9 CPSW_STAT1_RXUNDERSIZEDFRAMES Register (Offset = 0003A220h) [reset = 0h]
CPSW_STAT1_RXUNDERSIZEDFRAMES is shown in Figure 12-779 and described in Table 12-1496.
Return to Summary Table.
The total number of undersized frames received on the port. An undersized frame is defined to be:
- Was any data frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Was less than 64 octets long
- Had no CRC error, alignment error or code error
See the CPSW_STAT1_RXALIGNCODEERRORS and CPSW_STAT1_RXCRCERRORS statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic.
Table 12-1495 CPSW_STAT1_RXUNDERSIZEDFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A220h |
Figure 12-779 CPSW_STAT1_RXUNDERSIZEDFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1496 CPSW_STAT1_RXUNDERSIZEDFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of undersized frames received |
1.6.9.10 CPSW_STAT1_RXFRAGMENTS Register (Offset = 0003A224h) [reset = 0h]
CPSW_STAT1_RXFRAGMENTS is shown in Figure 12-780 and described in Table 12-1498.
Return to Summary Table.
The total number of frame fragments received on the port. A frame fragment is defined to be:
- Any data frame (address matching does not matter)
- Less than 64 bytes long
- Having a CRC error, an alignment error, or a code error
- Not the result of a collision caused by half duplex, collision based flow control
See the CPSW_STAT1_RXALIGNCODEERRORS and CPSW_STAT1_RXCRCERRORS statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic.
Table 12-1497 CPSW_STAT1_RXFRAGMENTS InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A224h |
Figure 12-780 CPSW_STAT1_RXFRAGMENTS Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1498 CPSW_STAT1_RXFRAGMENTS Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of fragmented frames received. |
1.6.9.11 CPSW_STAT1_ALE_DROP Register (Offset = 0003A228h) [reset = 0h]
CPSW_STAT1_ALE_DROP is shown in Figure 12-781 and described in Table 12-1500.
Return to Summary Table.
Total number of frames dropped by the ALE.
Table 12-1499 CPSW_STAT1_ALE_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A228h |
Figure 12-781 CPSW_STAT1_ALE_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1500 CPSW_STAT1_ALE_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of frames dropped by the ALE. |
1.6.9.12 CPSW_STAT1_ALE_OVERRUN_DROP Register (Offset = 0003A22Ch) [reset = 0h]
CPSW_STAT1_ALE_OVERRUN_DROP is shown in Figure 12-782 and described in Table 12-1502.
Return to Summary Table.
Total number of overrun frames dropped by the ALE.
Table 12-1501 CPSW_STAT1_ALE_OVERRUN_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A22Ch |
Figure 12-782 CPSW_STAT1_ALE_OVERRUN_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1502 CPSW_STAT1_ALE_OVERRUN_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of overrun frames dropped by the ALE |
1.6.9.13 CPSW_STAT1_RXOCTETS Register (Offset = 0003A230h) [reset = 0h]
CPSW_STAT1_RXOCTETS is shown in Figure 12-783 and described in Table 12-1504.
Return to Summary Table.
The total number of bytes in all good frames received on the port. A good frame is defined to be:
- Any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Of length 64 to CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes inclusive
- Had no CRC error, alignment error or code error
See the CPSW_STAT1_RXALIGNCODEERRORS and CPSW_STAT1_RXCRCERRORS statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic.
Table 12-1503 CPSW_STAT1_RXOCTETS InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A230h |
Figure 12-783 CPSW_STAT1_RXOCTETS Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1504 CPSW_STAT1_RXOCTETS Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of received bytes in good frames |
1.6.9.14 CPSW_STAT1_TXGOODFRAMES Register (Offset = 0003A234h) [reset = 0h]
CPSW_STAT1_TXGOODFRAMES is shown in Figure 12-784 and described in Table 12-1506.
Return to Summary Table.
The total number of good frames received on the port. A good frame is defined to be:
- Any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode
- Any length
- Had no late or excessive collisions, no carrier loss and no underrun.
Table 12-1505 CPSW_STAT1_TXGOODFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A234h |
Figure 12-784 CPSW_STAT1_TXGOODFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1506 CPSW_STAT1_TXGOODFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of good frames transmitted |
1.6.9.15 CPSW_STAT1_TXBROADCASTFRAMES Register (Offset = 0003A238h) [reset = 0h]
CPSW_STAT1_TXBROADCASTFRAMES is shown in Figure 12-785 and described in Table 12-1508.
Return to Summary Table.
The total number of good broadcast frames received on the port. A good broadcast frame is defined to be:
- Any data or MAC control frame which was destined for only address 0xFFFFFFFFFFFF
- Any length
- Had no late or excessive collisions, no carrier loss and no underrun
Table 12-1507 CPSW_STAT1_TXBROADCASTFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A238h |
Figure 12-785 CPSW_STAT1_TXBROADCASTFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1508 CPSW_STAT1_TXBROADCASTFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of good broadcast frames transmitted |
1.6.9.16 CPSW_STAT1_TXMULTICASTFRAMES Register (Offset = 0003A23Ch) [reset = 0h]
CPSW_STAT1_TXMULTICASTFRAMES is shown in Figure 12-786 and described in Table 12-1510.
Return to Summary Table.
The total number of good multicast frames received on the port. A good multicast frame is defined to be:
- Any data or MAC control frame which was destined for any multicast address other than 0xFFFFFFFFFFFF
- Any length
- Had no late or excessive collisions, no carrier loss and no underrun.
Table 12-1509 CPSW_STAT1_TXMULTICASTFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A23Ch |
Figure 12-786 CPSW_STAT1_TXMULTICASTFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1510 CPSW_STAT1_TXMULTICASTFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of good multicast frames transmitted |
1.6.9.17 CPSW_STAT1_TXPAUSEFRAMES Register (Offset = 0003A240h) [reset = 0h]
CPSW_STAT1_TXPAUSEFRAMES is shown in Figure 12-787 and described in Table 12-1512.
Return to Summary Table.
This statistic indicates the number of IEEE 802.3X pause frames transmitted by the port. Pause frames cannot underrun or contain a CRC error because they are created in the transmitting MAC, so these error conditions have no effect upon the statistic. Pause frames sent by software will not be included in this count. Since pause frames are only transmitted in full duplex carrier loss and collisions have no effect upon this statistic. Transmitted pause frames are always 64 byte multicast frames so will appear in the CPSW_STAT1_TXMULTICASTFRAMES and CPSW_STAT1_OCTETFRAMES64 statistics.
Table 12-1511 CPSW_STAT1_TXPAUSEFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A240h |
Figure 12-787 CPSW_STAT1_TXPAUSEFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1512 CPSW_STAT1_TXPAUSEFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of pause frames transmitted |
1.6.9.18 CPSW_STAT1_TXDEFERREDFRAMES Register (Offset = 0003A244h) [reset = 0h]
CPSW_STAT1_TXDEFERREDFRAMES is shown in Figure 12-788 and described in Table 12-1514.
Return to Summary Table.
The total number of frames transmitted on the port that first experienced deferment. Such a frame:
- Was any data or MAC control frame destined for any unicast, broadcast or multicast address
- Was any size
- Had no carrier loss and no underrun
- Experienced no collisions before being successfully transmitted
- Found the medium busy when transmission was first attempted, so had to wait. CRC errors have no effect upon this statistic.
Table 12-1513 CPSW_STAT1_TXDEFERREDFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A244h |
Figure 12-788 CPSW_STAT1_TXDEFERREDFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1514 CPSW_STAT1_TXDEFERREDFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of deferred frames transmitted |
1.6.9.19 CPSW_STAT1_TXCOLLISIONFRAMES Register (Offset = 0003A248h) [reset = 0h]
CPSW_STAT1_TXCOLLISIONFRAMES is shown in Figure 12-789 and described in Table 12-1516.
Return to Summary Table.
This statistic records the total number of times that the port experienced a collision. Collisions occur under two circumstances.
1. When a transmit data or MAC control frame:
- Was destined for any unicast, broadcast or multicast address
- Was any size
- Had no carrier loss and no underrun
- Experienced a collision. A jam sequence is sent for every non-late collision, so this statistic will increment on each occasion if a frame experiences multiple collisions (and increments on late collisions) CRC errors have no effect upon this statistic.
2. When the port is in half-duplex mode, flow control is active, and a frame reception begins.
Table 12-1515 CPSW_STAT1_TXCOLLISIONFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A248h |
Figure 12-789 CPSW_STAT1_TXCOLLISIONFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1516 CPSW_STAT1_TXCOLLISIONFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of transmitted frames experiencing a collision |
1.6.9.20 CPSW_STAT1_TXSINGLECOLLFRAMES Register (Offset = 0003A24Ch) [reset = 0h]
CPSW_STAT1_TXSINGLECOLLFRAMES is shown in Figure 12-790 and described in Table 12-1518.
Return to Summary Table.
The total number of frames transmitted on the port that experienced exactly one collision. Such a frame:
- Was any data or MAC control frame destined for any unicast, broadcast or multicast address
- Was any size
- Had no carrier loss and no underrun
- Experienced one collision before successful transmission. The collision was not late.
CRC errors have no effect upon this statistic.
Table 12-1517 CPSW_STAT1_TXSINGLECOLLFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A24Ch |
Figure 12-790 CPSW_STAT1_TXSINGLECOLLFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1518 CPSW_STAT1_TXSINGLECOLLFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of transmitted frames experiencing a single collision |
1.6.9.21 CPSW_STAT1_TXMULTCOLLFRAMES Register (Offset = 0003A250h) [reset = 0h]
CPSW_STAT1_TXMULTCOLLFRAMES is shown in Figure 12-791 and described in Table 12-1520.
Return to Summary Table.
The total number of frames transmitted on the port that experienced multiple collisions. Such a frame:
- Was any data or MAC control frame destined for any unicast, broadcast or multicast address
- Was any size
- Had no carrier loss and no underrun
- Experienced 2 to 15 collisions before being successfully transmitted. None of the collisions were late.
CRC errors have no effect upon this statistic.
Table 12-1519 CPSW_STAT1_TXMULTCOLLFRAMES InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A250h |
Figure 12-791 CPSW_STAT1_TXMULTCOLLFRAMES Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1520 CPSW_STAT1_TXMULTCOLLFRAMES Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of transmitted frames experiencing multiple collisions |
1.6.9.22 CPSW_STAT1_TXEXCESSIVECOLLISIONS Register (Offset = 0003A254h) [reset = 0h]
CPSW_STAT1_TXEXCESSIVECOLLISIONS is shown in Figure 12-792 and described in Table 12-1522.
Return to Summary Table.
The total number of frames for which transmission was abandoned due to excessive collisions. Such a frame:
- Was any data or MAC control frame destined for any unicast, broadcast or multicast address
- Was any size
- Had no carrier loss and no underrun
- Experienced 16 collisions before abandoning all attempts at transmitting the frame. None of the collisions were late.
CRC errors have no effect upon this statistic.
Table 12-1521 CPSW_STAT1_TXEXCESSIVECOLLISIONS InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A254h |
Figure 12-792 CPSW_STAT1_TXEXCESSIVECOLLISIONS Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1522 CPSW_STAT1_TXEXCESSIVECOLLISIONS Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of transmitted frames abandoned due to excessive collisions |
1.6.9.23 CPSW_STAT1_TXLATECOLLISIONS Register (Offset = 0003A258h) [reset = 0h]
CPSW_STAT1_TXLATECOLLISIONS is shown in Figure 12-793 and described in Table 12-1524.
Return to Summary Table.
The total number of frames on the port for which transmission was abandoned because they experienced a late collision. Such a frame:
- Was any data or MAC control frame destined for any unicast, broadcast or multicast address
- Was any size
- Experienced a collision later than 512 bit-times into the transmission. There may have been up to 15 previous (non-late) collisions which had previously required the transmission to be re-attempted. The Late Collisions statistic dominates over the single, multiple and excessive Collisions statistics - if a late collision occurs the frame will not be counted in any of these other three statistics.
CRC errors have no effect upon this statistic.
Table 12-1523 CPSW_STAT1_TXLATECOLLISIONS InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A258h |
Figure 12-793 CPSW_STAT1_TXLATECOLLISIONS Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1524 CPSW_STAT1_TXLATECOLLISIONS Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of transmitted frames abandoned due to a late collision |
1.6.9.24 CPSW_STAT1_RXIPGERROR Register (Offset = 0003A25Ch) [reset = 0h]
CPSW_STAT1_RXIPGERROR is shown in Figure 12-794 and described in Table 12-1526.
Return to Summary Table.
Total number of receive inter-packet gap errors (10G only).
Table 12-1525 CPSW_STAT1_RXIPGERROR InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A25Ch |
Figure 12-794 CPSW_STAT1_RXIPGERROR Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1526 CPSW_STAT1_RXIPGERROR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of receive inter-packet gap errors (10G only) |
1.6.9.25 CPSW_STAT1_TXCARRIERSENSEERRORS Register (Offset = 0003A260h) [reset = 0h]
CPSW_STAT1_TXCARRIERSENSEERRORS is shown in Figure 12-795 and described in Table 12-1528.
Return to Summary Table.
The total number of frames received on the port that had a middle of frame (MOF) overrun. MOF overrun frame is defined to be:
- Was any data or MAC control frame destined for any unicast, broadcast or multicast address
- Was any size
- The carrier sense condition was lost or never asserted when transmitting the frame (the frame is not retransmitted). This is a transmit only statistic. Carrier Sense is a don't care for received frames. Transmit frames with carrier sense errors are sent until completion and are not aborted.
CRC errors have no effect upon this statistic.
Table 12-1527 CPSW_STAT1_TXCARRIERSENSEERRORS InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A260h |
Figure 12-795 CPSW_STAT1_TXCARRIERSENSEERRORS Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1528 CPSW_STAT1_TXCARRIERSENSEERRORS Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of transmitted frames that experienced a carrier loss |
1.6.9.26 CPSW_STAT1_TXOCTETS Register (Offset = 0003A264h) [reset = 0h]
CPSW_STAT1_TXOCTETS is shown in Figure 12-796 and described in Table 12-1530.
Return to Summary Table.
The total number of bytes in all good frames transmitted on the port. A good frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Was any size
- Had no late or excessive collisions, no carrier loss and no underrun.
Table 12-1529 CPSW_STAT1_TXOCTETS InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A264h |
Figure 12-796 CPSW_STAT1_TXOCTETS Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1530 CPSW_STAT1_TXOCTETS Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of bytes in all good frames transmitted |
1.6.9.27 CPSW_STAT1_OCTETFRAMES64 Register (Offset = 0003A268h) [reset = 0h]
CPSW_STAT1_OCTETFRAMES64 is shown in Figure 12-797 and described in Table 12-1532.
Return to Summary Table.
The total number of 64-byte frames received and transmitted on the port. Such a frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Did not experience late collisions, excessive collisions, or carrier sense error
- Was exactly 64 bytes long. (If the frame was being transmitted and experienced carrier loss that resulted in a frame of this size being transmitted, then the frame will be recorded in this statistic).
CRC errors, code/align errors and overruns do not affect the recording of frames in this statistic.
Table 12-1531 CPSW_STAT1_OCTETFRAMES64 InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A268h |
Figure 12-797 CPSW_STAT1_OCTETFRAMES64 Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1532 CPSW_STAT1_OCTETFRAMES64 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of 64-byte frames received and transmitted |
1.6.9.28 CPSW_STAT1_OCTETFRAMES65T127 Register (Offset = 0003A26Ch) [reset = 0h]
CPSW_STAT1_OCTETFRAMES65T127 is shown in Figure 12-798 and described in Table 12-1534.
Return to Summary Table.
The total number of frames of size 65 to 127 bytes received and transmitted on the port. Such a frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Did not experience late collisions, excessive collisions, or carrier sense error
- Was 65 to 127 bytes long
CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic.
Table 12-1533 CPSW_STAT1_OCTETFRAMES65T127 InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A26Ch |
Figure 12-798 CPSW_STAT1_OCTETFRAMES65T127 Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1534 CPSW_STAT1_OCTETFRAMES65T127 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of frames of size 65 to 127 bytes received and transmitted |
1.6.9.29 CPSW_STAT1_OCTETFRAMES128T255 Register (Offset = 0003A270h) [reset = 0h]
CPSW_STAT1_OCTETFRAMES128T255 is shown in Figure 12-799 and described in Table 12-1536.
Return to Summary Table.
The total number of frames of size 128 to 255 bytes received and transmitted on the port. Such a frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Did not experience late collisions, excessive collisions, or carrier sense error
- Was 128 to 255 bytes long
CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic.
Table 12-1535 CPSW_STAT1_OCTETFRAMES128T255 InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A270h |
Figure 12-799 CPSW_STAT1_OCTETFRAMES128T255 Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1536 CPSW_STAT1_OCTETFRAMES128T255 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of frames of size 128 to 255 bytes received and transmitted |
1.6.9.30 CPSW_STAT1_OCTETFRAMES256T511 Register (Offset = 0003A274h) [reset = 0h]
CPSW_STAT1_OCTETFRAMES256T511 is shown in Figure 12-800 and described in Table 12-1538.
Return to Summary Table.
The total number of frames of size 256 to 511 bytes received and transmitted on the port. Such a frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Did not experience late collisions, excessive collisions, or carrier sense error
- Was 256 to 511 bytes long
CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic.
Table 12-1537 CPSW_STAT1_OCTETFRAMES256T511 InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A274h |
Figure 12-800 CPSW_STAT1_OCTETFRAMES256T511 Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1538 CPSW_STAT1_OCTETFRAMES256T511 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of frames of size 256 to 511 bytes received and transmitted |
1.6.9.31 CPSW_STAT1_OCTETFRAMES512T1023 Register (Offset = 0003A278h) [reset = 0h]
CPSW_STAT1_OCTETFRAMES512T1023 is shown in Figure 12-801 and described in Table 12-1540.
Return to Summary Table.
The total number of frames of size 512 to 1023 bytes received and transmitted on the port. Such a frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Did not experience late collisions, excessive collisions, or carrier sense error
- Was 512 to 1023 bytes long
CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic.
Table 12-1539 CPSW_STAT1_OCTETFRAMES512T1023 InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A278h |
Figure 12-801 CPSW_STAT1_OCTETFRAMES512T1023 Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1540 CPSW_STAT1_OCTETFRAMES512T1023 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of frames of size 512 to 1023 bytes received and transmitted |
1.6.9.32 CPSW_STAT1_OCTETFRAMES1024TUP Register (Offset = 0003A27Ch) [reset = 0h]
CPSW_STAT1_OCTETFRAMES1024TUP is shown in Figure 12-802 and described in Table 12-1542.
Return to Summary Table.
The total number of frames of size 1024 to CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes for receive or 1024 up for transmit on the port. Such a frame is defined to be:
- Any data or MAC control frame which was destined for any unicast, broadcast or multicast address
- Did not experience late collisions, excessive collisions, or carrier sense error
- Was 1024 to CPSW_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes long on receive, or any size on transmit
CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic.
Table 12-1541 CPSW_STAT1_OCTETFRAMES1024TUP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A27Ch |
Figure 12-802 CPSW_STAT1_OCTETFRAMES1024TUP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1542 CPSW_STAT1_OCTETFRAMES1024TUP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted |
1.6.9.33 CPSW_STAT1_NETOCTETS Register (Offset = 0003A280h) [reset = 0h]
CPSW_STAT1_NETOCTETS is shown in Figure 12-803 and described in Table 12-1544.
Return to Summary Table.
The total number of bytes of frame data received and transmitted on the port. Each frame counted:
- was any data or MAC control frame destined for any unicast, broadcast or multicast address (address match does not matter)
- Any length (including less than 64 bytes and greater than CPSW0_P0_RX_MAXLEN_REG[13-0] RX_MAXLEN bytes)
Also counted in this statistic is:
- Every byte transmitted before a carrier- loss was experienced
- Every byte transmitted before each collision was experienced, (i.e. multiple retries are counted each time)
- Every byte received if the port is in half-duplex mode until a jam sequence was transmitted to initiate flow control. (The jam sequence was not counted to prevent double-counting)
Error conditions such as alignment errors, CRC errors, code errors, overruns and underruns do not affect the recording of bytes by this statistic. The objective of this statistic is to give a reasonable indication of ethernet utilization
Table 12-1543 CPSW_STAT1_NETOCTETS InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A280h |
Figure 12-803 CPSW_STAT1_NETOCTETS Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1544 CPSW_STAT1_NETOCTETS Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of bytes received and transmitted |
1.6.9.34 CPSW_STAT1_RX_BOTTOM_OF_FIFO_DROP Register (Offset = 0003A284h) [reset = 0h]
CPSW_STAT1_RX_BOTTOM_OF_FIFO_DROP is shown in Figure 12-804 and described in Table 12-1546.
Return to Summary Table.
Receive Bottom of FIFO Drop.
Table 12-1545 CPSW_STAT1_RX_BOTTOM_OF_FIFO_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A284h |
Figure 12-804 CPSW_STAT1_RX_BOTTOM_OF_FIFO_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1546 CPSW_STAT1_RX_BOTTOM_OF_FIFO_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Receive Bottom of FIFO Drop. |
1.6.9.35 CPSW_STAT1_PORTMASK_DROP Register (Offset = 0003A288h) [reset = 0h]
CPSW_STAT1_PORTMASK_DROP is shown in Figure 12-805 and described in Table 12-1548.
Return to Summary Table.
Total number of dropped frames received due to portmask.
Table 12-1547 CPSW_STAT1_PORTMASK_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A288h |
Figure 12-805 CPSW_STAT1_PORTMASK_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1548 CPSW_STAT1_PORTMASK_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames received due to portmask. |
1.6.9.36 CPSW_STAT1_RX_TOP_OF_FIFO_DROP Register (Offset = 0003A28Ch) [reset = 0h]
CPSW_STAT1_RX_TOP_OF_FIFO_DROP is shown in Figure 12-806 and described in Table 12-1550.
Return to Summary Table.
Receive Top of FIFO Drop.
Table 12-1549 CPSW_STAT1_RX_TOP_OF_FIFO_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A28Ch |
Figure 12-806 CPSW_STAT1_RX_TOP_OF_FIFO_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1550 CPSW_STAT1_RX_TOP_OF_FIFO_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Receive Top of FIFO Drop. |
1.6.9.37 CPSW_STAT1_ALE_RATE_LIMIT_DROP Register (Offset = 0003A290h) [reset = 0h]
CPSW_STAT1_ALE_RATE_LIMIT_DROP is shown in Figure 12-807 and described in Table 12-1552.
Return to Summary Table.
Total number of dropped frames due to ALE Rate Limiting.
Table 12-1551 CPSW_STAT1_ALE_RATE_LIMIT_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A290h |
Figure 12-807 CPSW_STAT1_ALE_RATE_LIMIT_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1552 CPSW_STAT1_ALE_RATE_LIMIT_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames due to ALE Rate Limiting. |
1.6.9.38 CPSW_STAT1_ALE_VID_INGRESS_DROP Register (Offset = 0003A294h) [reset = 0h]
CPSW_STAT1_ALE_VID_INGRESS_DROP is shown in Figure 12-808 and described in Table 12-1554.
Return to Summary Table.
Total number of dropped frames due to ALE VID Ingress.
Table 12-1553 CPSW_STAT1_ALE_VID_INGRESS_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A294h |
Figure 12-808 CPSW_STAT1_ALE_VID_INGRESS_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1554 CPSW_STAT1_ALE_VID_INGRESS_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames due to ALE VID Ingress. |
1.6.9.39 CPSW_STAT1_ALE_DA_EQ_SA_DROP Register (Offset = 0003A298h) [reset = 0h]
CPSW_STAT1_ALE_DA_EQ_SA_DROP is shown in Figure 12-809 and described in Table 12-1556.
Return to Summary Table.
Total number of dropped frames due to DA=SA.
Table 12-1555 CPSW_STAT1_ALE_DA_EQ_SA_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A298h |
Figure 12-809 CPSW_STAT1_ALE_DA_EQ_SA_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1556 CPSW_STAT1_ALE_DA_EQ_SA_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames due to DA=SA. |
1.6.9.40 CPSW_STAT1_ALE_BLOCK_DROP Register (Offset = 0003A29Ch) [reset = 0h]
CPSW_STAT1_ALE_BLOCK_DROP is shown in Figure 12-810 and described in Table 12-1558.
Return to Summary Table.
Total number of dropped frames due to ALE Block Mode.
Table 12-1557 CPSW_STAT1_ALE_BLOCK_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A29Ch |
Figure 12-810 CPSW_STAT1_ALE_BLOCK_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1558 CPSW_STAT1_ALE_BLOCK_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames due to ALE Block Mode. |
1.6.9.41 CPSW_STAT1_ALE_SECURE_DROP Register (Offset = 0003A2A0h) [reset = 0h]
CPSW_STAT1_ALE_SECURE_DROP is shown in Figure 12-811 and described in Table 12-1560.
Return to Summary Table.
Total number of dropped frames due to ALE Secure Mode.
Table 12-1559 CPSW_STAT1_ALE_SECURE_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2A0h |
Figure 12-811 CPSW_STAT1_ALE_SECURE_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1560 CPSW_STAT1_ALE_SECURE_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames due to ALE Secure Mode. |
1.6.9.42 CPSW_STAT1_ALE_AUTH_DROP Register (Offset = 0003A2A4h) [reset = 0h]
CPSW_STAT1_ALE_AUTH_DROP is shown in Figure 12-812 and described in Table 12-1562.
Return to Summary Table.
Total number of dropped frames due to ALE Authentication.
Table 12-1561 CPSW_STAT1_ALE_AUTH_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2A4h |
Figure 12-812 CPSW_STAT1_ALE_AUTH_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1562 CPSW_STAT1_ALE_AUTH_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | Total number of dropped frames due to ALE Authentication. |
1.6.9.43 CPSW_STAT1_ALE_UNKN_UNI Register (Offset = 0003A2A8h) [reset = 0h]
CPSW_STAT1_ALE_UNKN_UNI is shown in Figure 12-813 and described in Table 12-1564.
Return to Summary Table.
ALE Receive Unknown Unicast.
Table 12-1563 CPSW_STAT1_ALE_UNKN_UNI InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2A8h |
Figure 12-813 CPSW_STAT1_ALE_UNKN_UNI Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1564 CPSW_STAT1_ALE_UNKN_UNI Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE Receive Unknown Unicast. |
1.6.9.44 CPSW_STAT1_ALE_UNKN_UNI_BCNT Register (Offset = 0003A2ACh) [reset = 0h]
CPSW_STAT1_ALE_UNKN_UNI_BCNT is shown in Figure 12-814 and described in Table 12-1566.
Return to Summary Table.
ALE Receive Unknown Unicast Bytecount.
Table 12-1565 CPSW_STAT1_ALE_UNKN_UNI_BCNT InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2ACh |
Figure 12-814 CPSW_STAT1_ALE_UNKN_UNI_BCNT Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1566 CPSW_STAT1_ALE_UNKN_UNI_BCNT Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE Receive Unknown Unicast Bytecount. |
1.6.9.45 CPSW_STAT1_ALE_UNKN_MLT Register (Offset = 0003A2B0h) [reset = 0h]
CPSW_STAT1_ALE_UNKN_MLT is shown in Figure 12-815 and described in Table 12-1568.
Return to Summary Table.
ALE Receive Unknown Multicast.
Table 12-1567 CPSW_STAT1_ALE_UNKN_MLT InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2B0h |
Figure 12-815 CPSW_STAT1_ALE_UNKN_MLT Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1568 CPSW_STAT1_ALE_UNKN_MLT Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE Receive Unknown Multicast. |
1.6.9.46 CPSW_STAT1_ALE_UNKN_MLT_BCNT Register (Offset = 0003A2B4h) [reset = 0h]
CPSW_STAT1_ALE_UNKN_MLT_BCNT is shown in Figure 12-816 and described in Table 12-1570.
Return to Summary Table.
ALE Receive Unknown Multicast Bytecount.
Table 12-1569 CPSW_STAT1_ALE_UNKN_MLT_BCNT InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2B4h |
Figure 12-816 CPSW_STAT1_ALE_UNKN_MLT_BCNT Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1570 CPSW_STAT1_ALE_UNKN_MLT_BCNT Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE Receive Unknown Multicast Bytecount. |
1.6.9.47 CPSW_STAT1_ALE_UNKN_BRD Register (Offset = 0003A2B8h) [reset = 0h]
CPSW_STAT1_ALE_UNKN_BRD is shown in Figure 12-817 and described in Table 12-1572.
Return to Summary Table.
ALE Receive Unknown Broadcast.
Table 12-1571 CPSW_STAT1_ALE_UNKN_BRD InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2B8h |
Figure 12-817 CPSW_STAT1_ALE_UNKN_BRD Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1572 CPSW_STAT1_ALE_UNKN_BRD Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE Receive Unknown Broadcast. |
1.6.9.48 CPSW_STAT1_ALE_UNKN_BRD_BCNT Register (Offset = 0003A2BCh) [reset = 0h]
CPSW_STAT1_ALE_UNKN_BRD_BCNT is shown in Figure 12-818 and described in Table 12-1574.
Return to Summary Table.
ALE Receive Unknown Broadcast Bytecount.
Table 12-1573 CPSW_STAT1_ALE_UNKN_BRD_BCNT InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2BCh |
Figure 12-818 CPSW_STAT1_ALE_UNKN_BRD_BCNT Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1574 CPSW_STAT1_ALE_UNKN_BRD_BCNT Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE Receive Unknown Broadcast Bytecount. |
1.6.9.49 CPSW_STAT1_ALE_POL_MATCH Register (Offset = 0003A2C0h) [reset = 0h]
CPSW_STAT1_ALE_POL_MATCH is shown in Figure 12-819 and described in Table 12-1576.
Return to Summary Table.
ALE Policer Matched.
Table 12-1575 CPSW_STAT1_ALE_POL_MATCH InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2C0h |
Figure 12-819 CPSW_STAT1_ALE_POL_MATCH Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1576 CPSW_STAT1_ALE_POL_MATCH Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE Policer Matched. |
1.6.9.50 CPSW_STAT1_ALE_POL_MATCH_RED Register (Offset = 0003A2C4h) [reset = 0h]
CPSW_STAT1_ALE_POL_MATCH_RED is shown in Figure 12-820 and described in Table 12-1578.
Return to Summary Table.
ALE Policer Matched and Condition Red.
Table 12-1577 CPSW_STAT1_ALE_POL_MATCH_RED InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2C4h |
Figure 12-820 CPSW_STAT1_ALE_POL_MATCH_RED Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1578 CPSW_STAT1_ALE_POL_MATCH_RED Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE Policer Matched and Condition Red. |
1.6.9.51 CPSW_STAT1_ALE_POL_MATCH_YELLOW Register (Offset = 0003A2C8h) [reset = 0h]
CPSW_STAT1_ALE_POL_MATCH_YELLOW is shown in Figure 12-821 and described in Table 12-1580.
Return to Summary Table.
ALE Policer Matched and Condition Yellow.
Table 12-1579 CPSW_STAT1_ALE_POL_MATCH_YELLOW InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2C8h |
Figure 12-821 CPSW_STAT1_ALE_POL_MATCH_YELLOW Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1580 CPSW_STAT1_ALE_POL_MATCH_YELLOW Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE Policer Matched and Condition Yellow. |
1.6.9.52 CPSW_STAT1_ALE_MULT_SA_DROP Register (Offset = 0003A2CCh) [reset = 0h]
CPSW_STAT1_ALE_MULT_SA_DROP is shown in Figure 12-822 and described in Table 12-1582.
Return to Summary Table.
ALE Multicast Source Address Drop
Table 12-1581 CPSW_STAT1_ALE_MULT_SA_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2CCh |
Figure 12-822 CPSW_STAT1_ALE_MULT_SA_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1582 CPSW_STAT1_ALE_MULT_SA_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE Multicast Source Address drop |
1.6.9.53 CPSW_STAT1_ALE_DUAL_VLAN_DROP Register (Offset = 0003A2D0h) [reset = 0h]
CPSW_STAT1_ALE_DUAL_VLAN_DROP is shown in Figure 12-823 and described in Table 12-1584.
Return to Summary Table.
ALE Dual VLAN Drop
Table 12-1583 CPSW_STAT1_ALE_DUAL_VLAN_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2D0h |
Figure 12-823 CPSW_STAT1_ALE_DUAL_VLAN_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1584 CPSW_STAT1_ALE_DUAL_VLAN_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE Dual VLAN drop |
1.6.9.54 CPSW_STAT1_ALE_LEN_ERROR_DROP Register (Offset = 0003A2D4h) [reset = 0h]
CPSW_STAT1_ALE_LEN_ERROR_DROP is shown in Figure 12-824 and described in Table 12-1586.
Return to Summary Table.
ALE Length Error Drop
Table 12-1585 CPSW_STAT1_ALE_LEN_ERROR_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2D4h |
Figure 12-824 CPSW_STAT1_ALE_LEN_ERROR_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1586 CPSW_STAT1_ALE_LEN_ERROR_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE Length Error drop |
1.6.9.55 CPSW_STAT1_ALE_IP_NEXT_HDR_DROP Register (Offset = 0003A2D8h) [reset = 0h]
CPSW_STAT1_ALE_IP_NEXT_HDR_DROP is shown in Figure 12-825 and described in Table 12-1588.
Return to Summary Table.
ALE IP Next Header Drop
Table 12-1587 CPSW_STAT1_ALE_IP_NEXT_HDR_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2D8h |
Figure 12-825 CPSW_STAT1_ALE_IP_NEXT_HDR_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1588 CPSW_STAT1_ALE_IP_NEXT_HDR_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE Next Header drop |
1.6.9.56 CPSW_STAT1_ALE_IPV4_FRAG_DROP Register (Offset = 0003A2DCh) [reset = 0h]
CPSW_STAT1_ALE_IPV4_FRAG_DROP is shown in Figure 12-826 and described in Table 12-1590.
Return to Summary Table.
ALE IPV4 Frag Drop
Table 12-1589 CPSW_STAT1_ALE_IPV4_FRAG_DROP InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A2DCh |
Figure 12-826 CPSW_STAT1_ALE_IPV4_FRAG_DROP Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1590 CPSW_STAT1_ALE_IPV4_FRAG_DROP Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | COUNT | R/W | 0h | ALE IPV4 Fragment drop |
1.6.9.57 CPSW_STAT1_IET_RX_ASSEMBLY_ERROR_REG Register (Offset = 0003A340h) [reset = 0h]
CPSW_STAT1_IET_RX_ASSEMBLY_ERROR_REG is shown in Figure 12-827 and described in Table 12-1592.
Return to Summary Table.
IET Receive Assembly Error
Table 12-1591 CPSW_STAT1_IET_RX_ASSEMBLY_ERROR_REG InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A340h |
Figure 12-827 CPSW_STAT1_IET_RX_ASSEMBLY_ERROR_REG Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1592 CPSW_STAT1_IET_RX_ASSEMBLY_ERROR_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | IET_RX_ASSEMBLY_ERROR | R/W | 0h | IET Receive Assembly Error |
1.6.9.58 CPSW_STAT1_IET_RX_ASSEMBLY_OK_REG Register (Offset = 0003A344h) [reset = 0h]
CPSW_STAT1_IET_RX_ASSEMBLY_OK_REG is shown in Figure 12-828 and described in Table 12-1594.
Return to Summary Table.
IET Receive Assembly Ok
Table 12-1593 CPSW_STAT1_IET_RX_ASSEMBLY_OK_REG InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A344h |
Figure 12-828 CPSW_STAT1_IET_RX_ASSEMBLY_OK_REG Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1594 CPSW_STAT1_IET_RX_ASSEMBLY_OK_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | IET_RX_ASSEMBLY_OK | R/W | 0h | IET Receive Assembly Ok |
1.6.9.59 CPSW_STAT1_IET_RX_SMD_ERROR_REG Register (Offset = 0003A348h) [reset = 0h]
CPSW_STAT1_IET_RX_SMD_ERROR_REG is shown in Figure 12-829 and described in Table 12-1596.
Return to Summary Table.
IET Receive Smd Error
Table 12-1595 CPSW_STAT1_IET_RX_SMD_ERROR_REG InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A348h |
Figure 12-829 CPSW_STAT1_IET_RX_SMD_ERROR_REG Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1596 CPSW_STAT1_IET_RX_SMD_ERROR_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | IET_RX_SMD_ERROR | R/W | 0h | IET Receive Smd Error |
1.6.9.60 CPSW_STAT1_IET_RX_FRAG_REG Register (Offset = 0003A34Ch) [reset = 0h]
CPSW_STAT1_IET_RX_FRAG_REG is shown in Figure 12-830 and described in Table 12-1598.
Return to Summary Table.
IET Receive Frag
Table 12-1597 CPSW_STAT1_IET_RX_FRAG_REG InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A34Ch |
Figure 12-830 CPSW_STAT1_IET_RX_FRAG_REG Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1598 CPSW_STAT1_IET_RX_FRAG_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | IET_RX_FRAG | R/W | 0h | IET Receive Frag |
1.6.9.61 CPSW_STAT1_IET_TX_HOLD_REG Register (Offset = 0003A350h) [reset = 0h]
CPSW_STAT1_IET_TX_HOLD_REG is shown in Figure 12-831 and described in Table 12-1600.
Return to Summary Table.
IET Transmit Hold
Table 12-1599 CPSW_STAT1_IET_TX_HOLD_REG InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A350h |
Figure 12-831 CPSW_STAT1_IET_TX_HOLD_REG Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1600 CPSW_STAT1_IET_TX_HOLD_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | IET_TX_HOLD | R/W | 0h | IET Transmit Hold |
1.6.9.62 CPSW_STAT1_IET_TX_FRAG_REG Register (Offset = 0003A354h) [reset = 0h]
CPSW_STAT1_IET_TX_FRAG_REG is shown in Figure 12-832 and described in Table 12-1602.
Return to Summary Table.
IET Transmit Frag
Table 12-1601 CPSW_STAT1_IET_TX_FRAG_REG InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A354h |
Figure 12-832 CPSW_STAT1_IET_TX_FRAG_REG Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1602 CPSW_STAT1_IET_TX_FRAG_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | IET_TX_FRAG | R/W | 0h | IET Transmit Frag |
1.6.9.63 CPSW_STAT1_TX_MEMORY_PROTECT_ERROR Register (Offset = 0003A37Ch) [reset = X]
CPSW_STAT1_TX_MEMORY_PROTECT_ERROR is shown in Figure 12-833 and described in Table 12-1604.
Return to Summary Table.
Transmit Memory Protect CRC Error.
Table 12-1603 CPSW_STAT1_TX_MEMORY_PROTECT_ERROR InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 | 4603 A37Ch |
Figure 12-833 CPSW_STAT1_TX_MEMORY_PROTECT_ERROR Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1604 CPSW_STAT1_TX_MEMORY_PROTECT_ERROR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-8 | RESERVED | R/W | X | |
7-0 | COUNT | R/W | 0h | Transmit Memory Protect CRC Error. |
1.6.9.64 CPSW_STAT1_ENET_PN_TX_PRI_REG_y Register (Offset = 0003A380h + formula) [reset = 0h]
CPSW_STAT1_ENET_PN_TX_PRI_REG_y is shown in Figure 12-834 and described in Table 12-1606.
Return to Summary Table.
ENET Port n PRIORITY N Packet Count.
Offset = 0003A380h + (y * 4h); where y = 0h to 7h.
Table 12-1605 CPSW_STAT1_ENET_PN_TX_PRI_REG_y InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 STAT0 | 4603 A380h + formula |
Figure 12-834 CPSW_STAT1_ENET_PN_TX_PRI_REG_y Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1606 CPSW_STAT1_ENET_PN_TX_PRI_REG_y Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | PN_TX_PRIN | R/W | 0h | Enet Port n Priority N Packet Count. |
1.6.9.65 CPSW_STAT1_ENET_PN_TX_PRI_BCNT_REG_y Register (Offset = 0003A3A0h + formula) [reset = 0h]
CPSW_STAT1_ENET_PN_TX_PRI_BCNT_REG_y is shown in Figure 12-835 and described in Table 12-1608.
Return to Summary Table.
ENET Port n PRIORITY N Packet Byte Count.
Offset = 0003A3A0h + (y * 4h); where y = 0h to 7h.
Table 12-1607 CPSW_STAT1_ENET_PN_TX_PRI_BCNT_REG_y InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 STAT0 | 4603 A3A0h + formula |
Figure 12-835 CPSW_STAT1_ENET_PN_TX_PRI_BCNT_REG_y Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1608 CPSW_STAT1_ENET_PN_TX_PRI_BCNT_REG_y Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | PN_TX_PRIN_BCNT | R/W | 0h | ENET Port n PRIORITY N Packet Byte Count. |
1.6.9.66 CPSW_STAT1_ENET_PN_TX_PRI_DROP_REG_y Register (Offset = 0003A3C0h + formula) [reset = 0h]
CPSW_STAT1_ENET_PN_TX_PRI_DROP_REG_y is shown in Figure 12-836 and described in Table 12-1610.
Return to Summary Table.
ENET Port n PRIORITY N Packet Drop Count.
Offset = 0003A3C0h + (y * 4h); where y = 0h to 7h.
Table 12-1609 CPSW_STAT1_ENET_PN_TX_PRI_DROP_REG_y InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 STAT0 | 4603 A3C0h + formula |
Figure 12-836 CPSW_STAT1_ENET_PN_TX_PRI_DROP_REG_y Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1610 CPSW_STAT1_ENET_PN_TX_PRI_DROP_REG_y Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | PN_TX_PRIN_DROP | R/W | 0h | ENET Port n PRIORITY N Packet Drop Count. |
1.6.9.67 CPSW_STAT1_ENET_PN_TX_PRI_DROP_BCNT_REG_y Register (Offset = 0003A3E0h + formula) [reset = 0h]
CPSW_STAT1_ENET_PN_TX_PRI_DROP_BCNT_REG_y is shown in Figure 12-837 and described in Table 12-1612.
Return to Summary Table.
ENET Port n PRIORITY N Packet Drop Byte Count.
Offset = 0003A3E0h + (y * 4h); where y = 0h to 7h.
Table 12-1611 CPSW_STAT1_ENET_PN_TX_PRI_DROP_BCNT_REG_y InstancesInstance | Physical Address |
---|
MCU_CPSW0_NUSS_STAT1 STAT0 | 4603 A3E0h + formula |
Figure 12-837 CPSW_STAT1_ENET_PN_TX_PRI_DROP_BCNT_REG_y Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1612 CPSW_STAT1_ENET_PN_TX_PRI_DROP_BCNT_REG_y Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | PN_TX_PRIN_DROP_BCNT | R/W | 0h | ENET Port n PRIORITY N Packet Drop Byte Count. |