SPRUIU1C User guide | 德州仪器 TI.com.cn

Table 12-5248 lists the memory-mapped registers for the MCAN Core. All register offset addresses not listed in Table 12-5248 should be considered as reserved locations and the register contents should not be modified.

Table 12-5247 MCAN Core Instances

Instance	Base Address
MCU_MCAN0_CFG	4052 8000h
MCU_MCAN1_CFG	4056 8000h
MCAN0_CFG	0270 1000h
MCAN1_CFG	0271 1000h
MCAN2_CFG	0272 1000h
MCAN3_CFG	0273 1000h
MCAN4_CFG	0274 1000h
MCAN5_CFG	0275 1000h
MCAN6_CFG	0276 1000h
MCAN7_CFG	0277 1000h
MCAN8_CFG	0278 1000h
MCAN9_CFG	0279 1000h
MCAN10_CFG	027A 1000h
MCAN11_CFG	027B 1000h
MCAN12_CFG	027C 1000h
MCAN13_CFG	027D 1000h
MCAN14_CFG	0268 1000h
MCAN15_CFG	0269 1000h
MCAN16_CFG	026A 1000h
MCAN17_CFG	026B 1000h

Table 12-5248 MCAN Core Registers

Offset	Acronym	Register Name	MCU_MCAN0_CFG Physical Address	MCU_MCAN1_CFG Physical Address
0h	MCAN_CREL	Core Release Register	4052 8000h	4056 8000h
4h	MCAN_ENDN	Endian Register	4052 8004h	4056 8004h
Ch	MCAN_DBTP	Data Bit Timing & Prescaler Register	4052 800Ch	4056 800Ch
10h	MCAN_TEST	Test Register	4052 8010h	4056 8010h
14h	MCAN_RWD	RAM Watchdog	4052 8014h	4056 8014h
18h	MCAN_CCCR	CC Control Register	4052 8018h	4056 8018h
1Ch	MCAN_NBTP	Nominal Bit Timing & Prescaler Register	4052 801Ch	4056 801Ch
20h	MCAN_TSCC	Timestamp Counter Configuration	4052 8020h	4056 8020h
24h	MCAN_TSCV	Timestamp Counter Value	4052 8024h	4056 8024h
28h	MCAN_TOCC	Timeout Counter Configuration	4052 8028h	4056 8028h
2Ch	MCAN_TOCV	Timeout Counter Value	4052 802Ch	4056 802Ch
40h	MCAN_ECR	Error Counter Register	4052 8040h	4056 8040h
44h	MCAN_PSR	Protocol Status Register	4052 8044h	4056 8044h
48h	MCAN_TDCR	Transmitter Delay Compensation Register	4052 8048h	4056 8048h
50h	MCAN_IR	Interrupt Register	4052 8050h	4056 8050h
54h	MCAN_IE	Interrupt Enable	4052 8054h	4056 8054h
58h	MCAN_ILS	Interrupt Line Select	4052 8058h	4056 8058h
5Ch	MCAN_ILE	Interrupt Line Enable	4052 805Ch	4056 805Ch
80h	MCAN_GFC	Global Filter Configuration	4052 8080h	4056 8080h
84h	MCAN_SIDFC	Standard ID Filter Configuration	4052 8084h	4056 8084h
88h	MCAN_XIDFC	Extended ID Filter Configuration	4052 8088h	4056 8088h
90h	MCAN_XIDAM	Extended ID AND Mask	4052 8090h	4056 8090h
94h	MCAN_HPMS	High Priority Message Status	4052 8094h	4056 8094h
98h	MCAN_NDAT1	New Data 1	4052 8098h	4056 8098h
9Ch	MCAN_NDAT2	New Data 2	4052 809Ch	4056 809Ch
A0h	MCAN_RXF0C	Rx FIFO 0 Configuration	4052 80A0h	4056 80A0h
A4h	MCAN_RXF0S	Rx FIFO 0 Status	4052 80A4h	4056 80A4h
A8h	MCAN_RXF0A	Rx FIFO 0 Acknowledge	4052 80A8h	4056 80A8h
ACh	MCAN_RXBC	Rx Buffer Configuration	4052 80ACh	4056 80ACh
B0h	MCAN_RXF1C	Rx FIFO 1 Configuration	4052 80B0h	4056 80B0h
B4h	MCAN_RXF1S	Rx FIFO 1 Status	4052 80B4h	4056 80B4h
B8h	MCAN_RXF1A	Rx FIFO 1 Acknowledge	4052 80B8h	4056 80B8h
BCh	MCAN_RXESC	Rx Buffer / FIFO Element Size Configuration	4052 80BCh	4056 80BCh
C0h	MCAN_TXBC	Tx Buffer Configuration	4052 80C0h	4056 80C0h
C4h	MCAN_TXFQS	Tx FIFO/Queue Status	4052 80C4h	4056 80C4h
C8h	MCAN_TXESC	Tx Buffer Element Size Configuration	4052 80C8h	4056 80C8h
CCh	MCAN_TXBRP	Tx Buffer Request Pending	4052 80CCh	4056 80CCh
D0h	MCAN_TXBAR	Tx Buffer Add Request	4052 80D0h	4056 80D0h
D4h	MCAN_TXBCR	Tx Buffer Cancellation Request	4052 80D4h	4056 80D4h
D8h	MCAN_TXBTO	Tx Buffer Transmission Occurred	4052 80D8h	4056 80D8h
DCh	MCAN_TXBCF	Tx Buffer Cancellation Finished	4052 80DCh	4056 80DCh
E0h	MCAN_TXBTIE	Tx Buffer Transmission Interrupt Enable	4052 80E0h	4056 80E0h
E4h	MCAN_TXBCIE	Tx Buffer Cancellation Finished Interrupt Enable	4052 80E4h	4056 80E4h
F0h	MCAN_TXEFC	Tx Event FIFO Configuration	4052 80F0h	4056 80F0h
F4h	MCAN_TXEFS	Tx Event FIFO Status	4052 80F4h	4056 80F4h
F8h	MCAN_TXEFA	Tx Event FIFO Acknowledge	4052 80F8h	4056 80F8h

Table 12-5249 MCAN Core Registers

Offset	Acronym	Register Name	MCAN0_CFG Physical Address	MCAN1_CFG Physical Address
0h	MCAN_CREL	Core Release Register	0270 1000h	0271 1000h
4h	MCAN_ENDN	Endian Register	0270 1004h	0271 1004h
Ch	MCAN_DBTP	Data Bit Timing & Prescaler Register	0270 100Ch	0271 100Ch
10h	MCAN_TEST	Test Register	0270 1010h	0271 1010h
14h	MCAN_RWD	RAM Watchdog	0270 1014h	0271 1014h
18h	MCAN_CCCR	CC Control Register	0270 1018h	0271 1018h
1Ch	MCAN_NBTP	Nominal Bit Timing & Prescaler Register	0270 101Ch	0271 101Ch
20h	MCAN_TSCC	Timestamp Counter Configuration	0270 1020h	0271 1020h
24h	MCAN_TSCV	Timestamp Counter Value	0270 1024h	0271 1024h
28h	MCAN_TOCC	Timeout Counter Configuration	0270 1028h	0271 1028h
2Ch	MCAN_TOCV	Timeout Counter Value	0270 102Ch	0271 102Ch
40h	MCAN_ECR	Error Counter Register	0270 1040h	0271 1040h
44h	MCAN_PSR	Protocol Status Register	0270 1044h	0271 1044h
48h	MCAN_TDCR	Transmitter Delay Compensation Register	0270 1048h	0271 1048h
50h	MCAN_IR	Interrupt Register	0270 1050h	0271 1050h
54h	MCAN_IE	Interrupt Enable	0270 1054h	0271 1054h
58h	MCAN_ILS	Interrupt Line Select	0270 1058h	0271 1058h
5Ch	MCAN_ILE	Interrupt Line Enable	0270 105Ch	0271 105Ch
80h	MCAN_GFC	Global Filter Configuration	0270 1080h	0271 1080h
84h	MCAN_SIDFC	Standard ID Filter Configuration	0270 1084h	0271 1084h
88h	MCAN_XIDFC	Extended ID Filter Configuration	0270 1088h	0271 1088h
90h	MCAN_XIDAM	Extended ID AND Mask	0270 1090h	0271 1090h
94h	MCAN_HPMS	High Priority Message Status	0270 1094h	0271 1094h
98h	MCAN_NDAT1	New Data 1	0270 1098h	0271 1098h
9Ch	MCAN_NDAT2	New Data 2	0270 109Ch	0271 109Ch
A0h	MCAN_RXF0C	Rx FIFO 0 Configuration	0270 10A0h	0271 10A0h
A4h	MCAN_RXF0S	Rx FIFO 0 Status	0270 10A4h	0271 10A4h
A8h	MCAN_RXF0A	Rx FIFO 0 Acknowledge	0270 10A8h	0271 10A8h
ACh	MCAN_RXBC	Rx Buffer Configuration	0270 10ACh	0271 10ACh
B0h	MCAN_RXF1C	Rx FIFO 1 Configuration	0270 10B0h	0271 10B0h
B4h	MCAN_RXF1S	Rx FIFO 1 Status	0270 10B4h	0271 10B4h
B8h	MCAN_RXF1A	Rx FIFO 1 Acknowledge	0270 10B8h	0271 10B8h
BCh	MCAN_RXESC	Rx Buffer / FIFO Element Size Configuration	0270 10BCh	0271 10BCh
C0h	MCAN_TXBC	Tx Buffer Configuration	0270 10C0h	0271 10C0h
C4h	MCAN_TXFQS	Tx FIFO/Queue Status	0270 10C4h	0271 10C4h
C8h	MCAN_TXESC	Tx Buffer Element Size Configuration	0270 10C8h	0271 10C8h
CCh	MCAN_TXBRP	Tx Buffer Request Pending	0270 10CCh	0271 10CCh
D0h	MCAN_TXBAR	Tx Buffer Add Request	0270 10D0h	0271 10D0h
D4h	MCAN_TXBCR	Tx Buffer Cancellation Request	0270 10D4h	0271 10D4h
D8h	MCAN_TXBTO	Tx Buffer Transmission Occurred	0270 10D8h	0271 10D8h
DCh	MCAN_TXBCF	Tx Buffer Cancellation Finished	0270 10DCh	0271 10DCh
E0h	MCAN_TXBTIE	Tx Buffer Transmission Interrupt Enable	0270 10E0h	0271 10E0h
E4h	MCAN_TXBCIE	Tx Buffer Cancellation Finished Interrupt Enable	0270 10E4h	0271 10E4h
F0h	MCAN_TXEFC	Tx Event FIFO Configuration	0270 10F0h	0271 10F0h
F4h	MCAN_TXEFS	Tx Event FIFO Status	0270 10F4h	0271 10F4h
F8h	MCAN_TXEFA	Tx Event FIFO Acknowledge	0270 10F8h	0271 10F8h

Table 12-5250 MCAN Core Registers

Offset	Acronym	Register Name	MCAN2_CFG Physical Address	MCAN3_CFG Physical Address
0h	MCAN_CREL	Core Release Register	0272 1000h	0273 1000h
4h	MCAN_ENDN	Endian Register	0272 1004h	0273 1004h
Ch	MCAN_DBTP	Data Bit Timing & Prescaler Register	0272 100Ch	0273 100Ch
10h	MCAN_TEST	Test Register	0272 1010h	0273 1010h
14h	MCAN_RWD	RAM Watchdog	0272 1014h	0273 1014h
18h	MCAN_CCCR	CC Control Register	0272 1018h	0273 1018h
1Ch	MCAN_NBTP	Nominal Bit Timing & Prescaler Register	0272 101Ch	0273 101Ch
20h	MCAN_TSCC	Timestamp Counter Configuration	0272 1020h	0273 1020h
24h	MCAN_TSCV	Timestamp Counter Value	0272 1024h	0273 1024h
28h	MCAN_TOCC	Timeout Counter Configuration	0272 1028h	0273 1028h
2Ch	MCAN_TOCV	Timeout Counter Value	0272 102Ch	0273 102Ch
40h	MCAN_ECR	Error Counter Register	0272 1040h	0273 1040h
44h	MCAN_PSR	Protocol Status Register	0272 1044h	0273 1044h
48h	MCAN_TDCR	Transmitter Delay Compensation Register	0272 1048h	0273 1048h
50h	MCAN_IR	Interrupt Register	0272 1050h	0273 1050h
54h	MCAN_IE	Interrupt Enable	0272 1054h	0273 1054h
58h	MCAN_ILS	Interrupt Line Select	0272 1058h	0273 1058h
5Ch	MCAN_ILE	Interrupt Line Enable	0272 105Ch	0273 105Ch
80h	MCAN_GFC	Global Filter Configuration	0272 1080h	0273 1080h
84h	MCAN_SIDFC	Standard ID Filter Configuration	0272 1084h	0273 1084h
88h	MCAN_XIDFC	Extended ID Filter Configuration	0272 1088h	0273 1088h
90h	MCAN_XIDAM	Extended ID AND Mask	0272 1090h	0273 1090h
94h	MCAN_HPMS	High Priority Message Status	0272 1094h	0273 1094h
98h	MCAN_NDAT1	New Data 1	0272 1098h	0273 1098h
9Ch	MCAN_NDAT2	New Data 2	0272 109Ch	0273 109Ch
A0h	MCAN_RXF0C	Rx FIFO 0 Configuration	0272 10A0h	0273 10A0h
A4h	MCAN_RXF0S	Rx FIFO 0 Status	0272 10A4h	0273 10A4h
A8h	MCAN_RXF0A	Rx FIFO 0 Acknowledge	0272 10A8h	0273 10A8h
ACh	MCAN_RXBC	Rx Buffer Configuration	0272 10ACh	0273 10ACh
B0h	MCAN_RXF1C	Rx FIFO 1 Configuration	0272 10B0h	0273 10B0h
B4h	MCAN_RXF1S	Rx FIFO 1 Status	0272 10B4h	0273 10B4h
B8h	MCAN_RXF1A	Rx FIFO 1 Acknowledge	0272 10B8h	0273 10B8h
BCh	MCAN_RXESC	Rx Buffer / FIFO Element Size Configuration	0272 10BCh	0273 10BCh
C0h	MCAN_TXBC	Tx Buffer Configuration	0272 10C0h	0273 10C0h
C4h	MCAN_TXFQS	Tx FIFO/Queue Status	0272 10C4h	0273 10C4h
C8h	MCAN_TXESC	Tx Buffer Element Size Configuration	0272 10C8h	0273 10C8h
CCh	MCAN_TXBRP	Tx Buffer Request Pending	0272 10CCh	0273 10CCh
D0h	MCAN_TXBAR	Tx Buffer Add Request	0272 10D0h	0273 10D0h
D4h	MCAN_TXBCR	Tx Buffer Cancellation Request	0272 10D4h	0273 10D4h
D8h	MCAN_TXBTO	Tx Buffer Transmission Occurred	0272 10D8h	0273 10D8h
DCh	MCAN_TXBCF	Tx Buffer Cancellation Finished	0272 10DCh	0273 10DCh
E0h	MCAN_TXBTIE	Tx Buffer Transmission Interrupt Enable	0272 10E0h	0273 10E0h
E4h	MCAN_TXBCIE	Tx Buffer Cancellation Finished Interrupt Enable	0272 10E4h	0273 10E4h
F0h	MCAN_TXEFC	Tx Event FIFO Configuration	0272 10F0h	0273 10F0h
F4h	MCAN_TXEFS	Tx Event FIFO Status	0272 10F4h	0273 10F4h
F8h	MCAN_TXEFA	Tx Event FIFO Acknowledge	0272 10F8h	0273 10F8h

Table 12-5251 MCAN Core Registers

Offset	Acronym	Register Name	MCAN4_CFG Physical Address	MCAN5_CFG Physical Address
0h	MCAN_CREL	Core Release Register	0274 1000h	0275 1000h
4h	MCAN_ENDN	Endian Register	0274 1004h	0275 1004h
Ch	MCAN_DBTP	Data Bit Timing & Prescaler Register	0274 100Ch	0275 100Ch
10h	MCAN_TEST	Test Register	0274 1010h	0275 1010h
14h	MCAN_RWD	RAM Watchdog	0274 1014h	0275 1014h
18h	MCAN_CCCR	CC Control Register	0274 1018h	0275 1018h
1Ch	MCAN_NBTP	Nominal Bit Timing & Prescaler Register	0274 101Ch	0275 101Ch
20h	MCAN_TSCC	Timestamp Counter Configuration	0274 1020h	0275 1020h
24h	MCAN_TSCV	Timestamp Counter Value	0274 1024h	0275 1024h
28h	MCAN_TOCC	Timeout Counter Configuration	0274 1028h	0275 1028h
2Ch	MCAN_TOCV	Timeout Counter Value	0274 102Ch	0275 102Ch
40h	MCAN_ECR	Error Counter Register	0274 1040h	0275 1040h
44h	MCAN_PSR	Protocol Status Register	0274 1044h	0275 1044h
48h	MCAN_TDCR	Transmitter Delay Compensation Register	0274 1048h	0275 1048h
50h	MCAN_IR	Interrupt Register	0274 1050h	0275 1050h
54h	MCAN_IE	Interrupt Enable	0274 1054h	0275 1054h
58h	MCAN_ILS	Interrupt Line Select	0274 1058h	0275 1058h
5Ch	MCAN_ILE	Interrupt Line Enable	0274 105Ch	0275 105Ch
80h	MCAN_GFC	Global Filter Configuration	0274 1080h	0275 1080h
84h	MCAN_SIDFC	Standard ID Filter Configuration	0274 1084h	0275 1084h
88h	MCAN_XIDFC	Extended ID Filter Configuration	0274 1088h	0275 1088h
90h	MCAN_XIDAM	Extended ID AND Mask	0274 1090h	0275 1090h
94h	MCAN_HPMS	High Priority Message Status	0274 1094h	0275 1094h
98h	MCAN_NDAT1	New Data 1	0274 1098h	0275 1098h
9Ch	MCAN_NDAT2	New Data 2	0274 109Ch	0275 109Ch
A0h	MCAN_RXF0C	Rx FIFO 0 Configuration	0274 10A0h	0275 10A0h
A4h	MCAN_RXF0S	Rx FIFO 0 Status	0274 10A4h	0275 10A4h
A8h	MCAN_RXF0A	Rx FIFO 0 Acknowledge	0274 10A8h	0275 10A8h
ACh	MCAN_RXBC	Rx Buffer Configuration	0274 10ACh	0275 10ACh
B0h	MCAN_RXF1C	Rx FIFO 1 Configuration	0274 10B0h	0275 10B0h
B4h	MCAN_RXF1S	Rx FIFO 1 Status	0274 10B4h	0275 10B4h
B8h	MCAN_RXF1A	Rx FIFO 1 Acknowledge	0274 10B8h	0275 10B8h
BCh	MCAN_RXESC	Rx Buffer / FIFO Element Size Configuration	0274 10BCh	0275 10BCh
C0h	MCAN_TXBC	Tx Buffer Configuration	0274 10C0h	0275 10C0h
C4h	MCAN_TXFQS	Tx FIFO/Queue Status	0274 10C4h	0275 10C4h
C8h	MCAN_TXESC	Tx Buffer Element Size Configuration	0274 10C8h	0275 10C8h
CCh	MCAN_TXBRP	Tx Buffer Request Pending	0274 10CCh	0275 10CCh
D0h	MCAN_TXBAR	Tx Buffer Add Request	0274 10D0h	0275 10D0h
D4h	MCAN_TXBCR	Tx Buffer Cancellation Request	0274 10D4h	0275 10D4h
D8h	MCAN_TXBTO	Tx Buffer Transmission Occurred	0274 10D8h	0275 10D8h
DCh	MCAN_TXBCF	Tx Buffer Cancellation Finished	0274 10DCh	0275 10DCh
E0h	MCAN_TXBTIE	Tx Buffer Transmission Interrupt Enable	0274 10E0h	0275 10E0h
E4h	MCAN_TXBCIE	Tx Buffer Cancellation Finished Interrupt Enable	0274 10E4h	0275 10E4h
F0h	MCAN_TXEFC	Tx Event FIFO Configuration	0274 10F0h	0275 10F0h
F4h	MCAN_TXEFS	Tx Event FIFO Status	0274 10F4h	0275 10F4h
F8h	MCAN_TXEFA	Tx Event FIFO Acknowledge	0274 10F8h	0275 10F8h

Table 12-5252 MCAN Core Registers

Offset	Acronym	Register Name	MCAN6_CFG Physical Address	MCAN7_CFG Physical Address
0h	MCAN_CREL	Core Release Register	0276 1000h	0277 1000h
4h	MCAN_ENDN	Endian Register	0276 1004h	0277 1004h
Ch	MCAN_DBTP	Data Bit Timing & Prescaler Register	0276 100Ch	0277 100Ch
10h	MCAN_TEST	Test Register	0276 1010h	0277 1010h
14h	MCAN_RWD	RAM Watchdog	0276 1014h	0277 1014h
18h	MCAN_CCCR	CC Control Register	0276 1018h	0277 1018h
1Ch	MCAN_NBTP	Nominal Bit Timing & Prescaler Register	0276 101Ch	0277 101Ch
20h	MCAN_TSCC	Timestamp Counter Configuration	0276 1020h	0277 1020h
24h	MCAN_TSCV	Timestamp Counter Value	0276 1024h	0277 1024h
28h	MCAN_TOCC	Timeout Counter Configuration	0276 1028h	0277 1028h
2Ch	MCAN_TOCV	Timeout Counter Value	0276 102Ch	0277 102Ch
40h	MCAN_ECR	Error Counter Register	0276 1040h	0277 1040h
44h	MCAN_PSR	Protocol Status Register	0276 1044h	0277 1044h
48h	MCAN_TDCR	Transmitter Delay Compensation Register	0276 1048h	0277 1048h
50h	MCAN_IR	Interrupt Register	0276 1050h	0277 1050h
54h	MCAN_IE	Interrupt Enable	0276 1054h	0277 1054h
58h	MCAN_ILS	Interrupt Line Select	0276 1058h	0277 1058h
5Ch	MCAN_ILE	Interrupt Line Enable	0276 105Ch	0277 105Ch
80h	MCAN_GFC	Global Filter Configuration	0276 1080h	0277 1080h
84h	MCAN_SIDFC	Standard ID Filter Configuration	0276 1084h	0277 1084h
88h	MCAN_XIDFC	Extended ID Filter Configuration	0276 1088h	0277 1088h
90h	MCAN_XIDAM	Extended ID AND Mask	0276 1090h	0277 1090h
94h	MCAN_HPMS	High Priority Message Status	0276 1094h	0277 1094h
98h	MCAN_NDAT1	New Data 1	0276 1098h	0277 1098h
9Ch	MCAN_NDAT2	New Data 2	0276 109Ch	0277 109Ch
A0h	MCAN_RXF0C	Rx FIFO 0 Configuration	0276 10A0h	0277 10A0h
A4h	MCAN_RXF0S	Rx FIFO 0 Status	0276 10A4h	0277 10A4h
A8h	MCAN_RXF0A	Rx FIFO 0 Acknowledge	0276 10A8h	0277 10A8h
ACh	MCAN_RXBC	Rx Buffer Configuration	0276 10ACh	0277 10ACh
B0h	MCAN_RXF1C	Rx FIFO 1 Configuration	0276 10B0h	0277 10B0h
B4h	MCAN_RXF1S	Rx FIFO 1 Status	0276 10B4h	0277 10B4h
B8h	MCAN_RXF1A	Rx FIFO 1 Acknowledge	0276 10B8h	0277 10B8h
BCh	MCAN_RXESC	Rx Buffer / FIFO Element Size Configuration	0276 10BCh	0277 10BCh
C0h	MCAN_TXBC	Tx Buffer Configuration	0276 10C0h	0277 10C0h
C4h	MCAN_TXFQS	Tx FIFO/Queue Status	0276 10C4h	0277 10C4h
C8h	MCAN_TXESC	Tx Buffer Element Size Configuration	0276 10C8h	0277 10C8h
CCh	MCAN_TXBRP	Tx Buffer Request Pending	0276 10CCh	0277 10CCh
D0h	MCAN_TXBAR	Tx Buffer Add Request	0276 10D0h	0277 10D0h
D4h	MCAN_TXBCR	Tx Buffer Cancellation Request	0276 10D4h	0277 10D4h
D8h	MCAN_TXBTO	Tx Buffer Transmission Occurred	0276 10D8h	0277 10D8h
DCh	MCAN_TXBCF	Tx Buffer Cancellation Finished	0276 10DCh	0277 10DCh
E0h	MCAN_TXBTIE	Tx Buffer Transmission Interrupt Enable	0276 10E0h	0277 10E0h
E4h	MCAN_TXBCIE	Tx Buffer Cancellation Finished Interrupt Enable	0276 10E4h	0277 10E4h
F0h	MCAN_TXEFC	Tx Event FIFO Configuration	0276 10F0h	0277 10F0h
F4h	MCAN_TXEFS	Tx Event FIFO Status	0276 10F4h	0277 10F4h
F8h	MCAN_TXEFA	Tx Event FIFO Acknowledge	0276 10F8h	0277 10F8h

Table 12-5253 MCAN Core Registers

Offset	Acronym	Register Name	MCAN8_CFG Physical Address	MCAN9_CFG Physical Address
0h	MCAN_CREL	Core Release Register	0278 1000h	0279 1000h
4h	MCAN_ENDN	Endian Register	0278 1004h	0279 1004h
Ch	MCAN_DBTP	Data Bit Timing & Prescaler Register	0278 100Ch	0279 100Ch
10h	MCAN_TEST	Test Register	0278 1010h	0279 1010h
14h	MCAN_RWD	RAM Watchdog	0278 1014h	0279 1014h
18h	MCAN_CCCR	CC Control Register	0278 1018h	0279 1018h
1Ch	MCAN_NBTP	Nominal Bit Timing & Prescaler Register	0278 101Ch	0279 101Ch
20h	MCAN_TSCC	Timestamp Counter Configuration	0278 1020h	0279 1020h
24h	MCAN_TSCV	Timestamp Counter Value	0278 1024h	0279 1024h
28h	MCAN_TOCC	Timeout Counter Configuration	0278 1028h	0279 1028h
2Ch	MCAN_TOCV	Timeout Counter Value	0278 102Ch	0279 102Ch
40h	MCAN_ECR	Error Counter Register	0278 1040h	0279 1040h
44h	MCAN_PSR	Protocol Status Register	0278 1044h	0279 1044h
48h	MCAN_TDCR	Transmitter Delay Compensation Register	0278 1048h	0279 1048h
50h	MCAN_IR	Interrupt Register	0278 1050h	0279 1050h
54h	MCAN_IE	Interrupt Enable	0278 1054h	0279 1054h
58h	MCAN_ILS	Interrupt Line Select	0278 1058h	0279 1058h
5Ch	MCAN_ILE	Interrupt Line Enable	0278 105Ch	0279 105Ch
80h	MCAN_GFC	Global Filter Configuration	0278 1080h	0279 1080h
84h	MCAN_SIDFC	Standard ID Filter Configuration	0278 1084h	0279 1084h
88h	MCAN_XIDFC	Extended ID Filter Configuration	0278 1088h	0279 1088h
90h	MCAN_XIDAM	Extended ID AND Mask	0278 1090h	0279 1090h
94h	MCAN_HPMS	High Priority Message Status	0278 1094h	0279 1094h
98h	MCAN_NDAT1	New Data 1	0278 1098h	0279 1098h
9Ch	MCAN_NDAT2	New Data 2	0278 109Ch	0279 109Ch
A0h	MCAN_RXF0C	Rx FIFO 0 Configuration	0278 10A0h	0279 10A0h
A4h	MCAN_RXF0S	Rx FIFO 0 Status	0278 10A4h	0279 10A4h
A8h	MCAN_RXF0A	Rx FIFO 0 Acknowledge	0278 10A8h	0279 10A8h
ACh	MCAN_RXBC	Rx Buffer Configuration	0278 10ACh	0279 10ACh
B0h	MCAN_RXF1C	Rx FIFO 1 Configuration	0278 10B0h	0279 10B0h
B4h	MCAN_RXF1S	Rx FIFO 1 Status	0278 10B4h	0279 10B4h
B8h	MCAN_RXF1A	Rx FIFO 1 Acknowledge	0278 10B8h	0279 10B8h
BCh	MCAN_RXESC	Rx Buffer / FIFO Element Size Configuration	0278 10BCh	0279 10BCh
C0h	MCAN_TXBC	Tx Buffer Configuration	0278 10C0h	0279 10C0h
C4h	MCAN_TXFQS	Tx FIFO/Queue Status	0278 10C4h	0279 10C4h
C8h	MCAN_TXESC	Tx Buffer Element Size Configuration	0278 10C8h	0279 10C8h
CCh	MCAN_TXBRP	Tx Buffer Request Pending	0278 10CCh	0279 10CCh
D0h	MCAN_TXBAR	Tx Buffer Add Request	0278 10D0h	0279 10D0h
D4h	MCAN_TXBCR	Tx Buffer Cancellation Request	0278 10D4h	0279 10D4h
D8h	MCAN_TXBTO	Tx Buffer Transmission Occurred	0278 10D8h	0279 10D8h
DCh	MCAN_TXBCF	Tx Buffer Cancellation Finished	0278 10DCh	0279 10DCh
E0h	MCAN_TXBTIE	Tx Buffer Transmission Interrupt Enable	0278 10E0h	0279 10E0h
E4h	MCAN_TXBCIE	Tx Buffer Cancellation Finished Interrupt Enable	0278 10E4h	0279 10E4h
F0h	MCAN_TXEFC	Tx Event FIFO Configuration	0278 10F0h	0279 10F0h
F4h	MCAN_TXEFS	Tx Event FIFO Status	0278 10F4h	0279 10F4h
F8h	MCAN_TXEFA	Tx Event FIFO Acknowledge	0278 10F8h	0279 10F8h

Table 12-5254 MCAN Core Registers

Offset	Acronym	Register Name	MCAN10_CFG Physical Address	MCAN11_CFG Physical Address
0h	MCAN_CREL	Core Release Register	027A 1000h	027B 1000h
4h	MCAN_ENDN	Endian Register	027A 1004h	027B 1004h
Ch	MCAN_DBTP	Data Bit Timing & Prescaler Register	027A 100Ch	027B 100Ch
10h	MCAN_TEST	Test Register	027A 1010h	027B 1010h
14h	MCAN_RWD	RAM Watchdog	027A 1014h	027B 1014h
18h	MCAN_CCCR	CC Control Register	027A 1018h	027B 1018h
1Ch	MCAN_NBTP	Nominal Bit Timing & Prescaler Register	027A 101Ch	027B 101Ch
20h	MCAN_TSCC	Timestamp Counter Configuration	027A 1020h	027B 1020h
24h	MCAN_TSCV	Timestamp Counter Value	027A 1024h	027B 1024h
28h	MCAN_TOCC	Timeout Counter Configuration	027A 1028h	027B 1028h
2Ch	MCAN_TOCV	Timeout Counter Value	027A 102Ch	027B 102Ch
40h	MCAN_ECR	Error Counter Register	027A 1040h	027B 1040h
44h	MCAN_PSR	Protocol Status Register	027A 1044h	027B 1044h
48h	MCAN_TDCR	Transmitter Delay Compensation Register	027A 1048h	027B 1048h
50h	MCAN_IR	Interrupt Register	027A 1050h	027B 1050h
54h	MCAN_IE	Interrupt Enable	027A 1054h	027B 1054h
58h	MCAN_ILS	Interrupt Line Select	027A 1058h	027B 1058h
5Ch	MCAN_ILE	Interrupt Line Enable	027A 105Ch	027B 105Ch
80h	MCAN_GFC	Global Filter Configuration	027A 1080h	027B 1080h
84h	MCAN_SIDFC	Standard ID Filter Configuration	027A 1084h	027B 1084h
88h	MCAN_XIDFC	Extended ID Filter Configuration	027A 1088h	027B 1088h
90h	MCAN_XIDAM	Extended ID AND Mask	027A 1090h	027B 1090h
94h	MCAN_HPMS	High Priority Message Status	027A 1094h	027B 1094h
98h	MCAN_NDAT1	New Data 1	027A 1098h	027B 1098h
9Ch	MCAN_NDAT2	New Data 2	027A 109Ch	027B 109Ch
A0h	MCAN_RXF0C	Rx FIFO 0 Configuration	027A 10A0h	027B 10A0h
A4h	MCAN_RXF0S	Rx FIFO 0 Status	027A 10A4h	027B 10A4h
A8h	MCAN_RXF0A	Rx FIFO 0 Acknowledge	027A 10A8h	027B 10A8h
ACh	MCAN_RXBC	Rx Buffer Configuration	027A 10ACh	027B 10ACh
B0h	MCAN_RXF1C	Rx FIFO 1 Configuration	027A 10B0h	027B 10B0h
B4h	MCAN_RXF1S	Rx FIFO 1 Status	027A 10B4h	027B 10B4h
B8h	MCAN_RXF1A	Rx FIFO 1 Acknowledge	027A 10B8h	027B 10B8h
BCh	MCAN_RXESC	Rx Buffer / FIFO Element Size Configuration	027A 10BCh	027B 10BCh
C0h	MCAN_TXBC	Tx Buffer Configuration	027A 10C0h	027B 10C0h
C4h	MCAN_TXFQS	Tx FIFO/Queue Status	027A 10C4h	027B 10C4h
C8h	MCAN_TXESC	Tx Buffer Element Size Configuration	027A 10C8h	027B 10C8h
CCh	MCAN_TXBRP	Tx Buffer Request Pending	027A 10CCh	027B 10CCh
D0h	MCAN_TXBAR	Tx Buffer Add Request	027A 10D0h	027B 10D0h
D4h	MCAN_TXBCR	Tx Buffer Cancellation Request	027A 10D4h	027B 10D4h
D8h	MCAN_TXBTO	Tx Buffer Transmission Occurred	027A 10D8h	027B 10D8h
DCh	MCAN_TXBCF	Tx Buffer Cancellation Finished	027A 10DCh	027B 10DCh
E0h	MCAN_TXBTIE	Tx Buffer Transmission Interrupt Enable	027A 10E0h	027B 10E0h
E4h	MCAN_TXBCIE	Tx Buffer Cancellation Finished Interrupt Enable	027A 10E4h	027B 10E4h
F0h	MCAN_TXEFC	Tx Event FIFO Configuration	027A 10F0h	027B 10F0h
F4h	MCAN_TXEFS	Tx Event FIFO Status	027A 10F4h	027B 10F4h
F8h	MCAN_TXEFA	Tx Event FIFO Acknowledge	027A 10F8h	027B 10F8h

Table 12-5255 MCAN Core Registers

Offset	Acronym	Register Name	MCAN12_CFG Physical Address	MCAN13_CFG Physical Address
0h	MCAN_CREL	Core Release Register	027C 1000h	027D 1000h
4h	MCAN_ENDN	Endian Register	027C 1004h	027D 1004h
Ch	MCAN_DBTP	Data Bit Timing & Prescaler Register	027C 100Ch	027D 100Ch
10h	MCAN_TEST	Test Register	027C 1010h	027D 1010h
14h	MCAN_RWD	RAM Watchdog	027C 1014h	027D 1014h
18h	MCAN_CCCR	CC Control Register	027C 1018h	027D 1018h
1Ch	MCAN_NBTP	Nominal Bit Timing & Prescaler Register	027C 101Ch	027D 101Ch
20h	MCAN_TSCC	Timestamp Counter Configuration	027C 1020h	027D 1020h
24h	MCAN_TSCV	Timestamp Counter Value	027C 1024h	027D 1024h
28h	MCAN_TOCC	Timeout Counter Configuration	027C 1028h	027D 1028h
2Ch	MCAN_TOCV	Timeout Counter Value	027C 102Ch	027D 102Ch
40h	MCAN_ECR	Error Counter Register	027C 1040h	027D 1040h
44h	MCAN_PSR	Protocol Status Register	027C 1044h	027D 1044h
48h	MCAN_TDCR	Transmitter Delay Compensation Register	027C 1048h	027D 1048h
50h	MCAN_IR	Interrupt Register	027C 1050h	027D 1050h
54h	MCAN_IE	Interrupt Enable	027C 1054h	027D 1054h
58h	MCAN_ILS	Interrupt Line Select	027C 1058h	027D 1058h
5Ch	MCAN_ILE	Interrupt Line Enable	027C 105Ch	027D 105Ch
80h	MCAN_GFC	Global Filter Configuration	027C 1080h	027D 1080h
84h	MCAN_SIDFC	Standard ID Filter Configuration	027C 1084h	027D 1084h
88h	MCAN_XIDFC	Extended ID Filter Configuration	027C 1088h	027D 1088h
90h	MCAN_XIDAM	Extended ID AND Mask	027C 1090h	027D 1090h
94h	MCAN_HPMS	High Priority Message Status	027C 1094h	027D 1094h
98h	MCAN_NDAT1	New Data 1	027C 1098h	027D 1098h
9Ch	MCAN_NDAT2	New Data 2	027C 109Ch	027D 109Ch
A0h	MCAN_RXF0C	Rx FIFO 0 Configuration	027C 10A0h	027D 10A0h
A4h	MCAN_RXF0S	Rx FIFO 0 Status	027C 10A4h	027D 10A4h
A8h	MCAN_RXF0A	Rx FIFO 0 Acknowledge	027C 10A8h	027D 10A8h
ACh	MCAN_RXBC	Rx Buffer Configuration	027C 10ACh	027D 10ACh
B0h	MCAN_RXF1C	Rx FIFO 1 Configuration	027C 10B0h	027D 10B0h
B4h	MCAN_RXF1S	Rx FIFO 1 Status	027C 10B4h	027D 10B4h
B8h	MCAN_RXF1A	Rx FIFO 1 Acknowledge	027C 10B8h	027D 10B8h
BCh	MCAN_RXESC	Rx Buffer / FIFO Element Size Configuration	027C 10BCh	027D 10BCh
C0h	MCAN_TXBC	Tx Buffer Configuration	027C 10C0h	027D 10C0h
C4h	MCAN_TXFQS	Tx FIFO/Queue Status	027C 10C4h	027D 10C4h
C8h	MCAN_TXESC	Tx Buffer Element Size Configuration	027C 10C8h	027D 10C8h
CCh	MCAN_TXBRP	Tx Buffer Request Pending	027C 10CCh	027D 10CCh
D0h	MCAN_TXBAR	Tx Buffer Add Request	027C 10D0h	027D 10D0h
D4h	MCAN_TXBCR	Tx Buffer Cancellation Request	027C 10D4h	027D 10D4h
D8h	MCAN_TXBTO	Tx Buffer Transmission Occurred	027C 10D8h	027D 10D8h
DCh	MCAN_TXBCF	Tx Buffer Cancellation Finished	027C 10DCh	027D 10DCh
E0h	MCAN_TXBTIE	Tx Buffer Transmission Interrupt Enable	027C 10E0h	027D 10E0h
E4h	MCAN_TXBCIE	Tx Buffer Cancellation Finished Interrupt Enable	027C 10E4h	027D 10E4h
F0h	MCAN_TXEFC	Tx Event FIFO Configuration	027C 10F0h	027D 10F0h
F4h	MCAN_TXEFS	Tx Event FIFO Status	027C 10F4h	027D 10F4h
F8h	MCAN_TXEFA	Tx Event FIFO Acknowledge	027C 10F8h	027D 10F8h

Table 12-5256 MCAN Core Registers

Offset	Acronym	Register Name	MCAN14_CFG Physical Address	MCAN15_CFG Physical Address
0h	MCAN_CREL	Core Release Register	0268 1000h	0269 1000h
4h	MCAN_ENDN	Endian Register	0268 1004h	0269 1004h
Ch	MCAN_DBTP	Data Bit Timing & Prescaler Register	0268 100Ch	0269 100Ch
10h	MCAN_TEST	Test Register	0268 1010h	0269 1010h
14h	MCAN_RWD	RAM Watchdog	0268 1014h	0269 1014h
18h	MCAN_CCCR	CC Control Register	0268 1018h	0269 1018h
1Ch	MCAN_NBTP	Nominal Bit Timing & Prescaler Register	0268 101Ch	0269 101Ch
20h	MCAN_TSCC	Timestamp Counter Configuration	0268 1020h	0269 1020h
24h	MCAN_TSCV	Timestamp Counter Value	0268 1024h	0269 1024h
28h	MCAN_TOCC	Timeout Counter Configuration	0268 1028h	0269 1028h
2Ch	MCAN_TOCV	Timeout Counter Value	0268 102Ch	0269 102Ch
40h	MCAN_ECR	Error Counter Register	0268 1040h	0269 1040h
44h	MCAN_PSR	Protocol Status Register	0268 1044h	0269 1044h
48h	MCAN_TDCR	Transmitter Delay Compensation Register	0268 1048h	0269 1048h
50h	MCAN_IR	Interrupt Register	0268 1050h	0269 1050h
54h	MCAN_IE	Interrupt Enable	0268 1054h	0269 1054h
58h	MCAN_ILS	Interrupt Line Select	0268 1058h	0269 1058h
5Ch	MCAN_ILE	Interrupt Line Enable	0268 105Ch	0269 105Ch
80h	MCAN_GFC	Global Filter Configuration	0268 1080h	0269 1080h
84h	MCAN_SIDFC	Standard ID Filter Configuration	0268 1084h	0269 1084h
88h	MCAN_XIDFC	Extended ID Filter Configuration	0268 1088h	0269 1088h
90h	MCAN_XIDAM	Extended ID AND Mask	0268 1090h	0269 1090h
94h	MCAN_HPMS	High Priority Message Status	0268 1094h	0269 1094h
98h	MCAN_NDAT1	New Data 1	0268 1098h	0269 1098h
9Ch	MCAN_NDAT2	New Data 2	0268 109Ch	0269 109Ch
A0h	MCAN_RXF0C	Rx FIFO 0 Configuration	0268 10A0h	0269 10A0h
A4h	MCAN_RXF0S	Rx FIFO 0 Status	0268 10A4h	0269 10A4h
A8h	MCAN_RXF0A	Rx FIFO 0 Acknowledge	0268 10A8h	0269 10A8h
ACh	MCAN_RXBC	Rx Buffer Configuration	0268 10ACh	0269 10ACh
B0h	MCAN_RXF1C	Rx FIFO 1 Configuration	0268 10B0h	0269 10B0h
B4h	MCAN_RXF1S	Rx FIFO 1 Status	0268 10B4h	0269 10B4h
B8h	MCAN_RXF1A	Rx FIFO 1 Acknowledge	0268 10B8h	0269 10B8h
BCh	MCAN_RXESC	Rx Buffer / FIFO Element Size Configuration	0268 10BCh	0269 10BCh
C0h	MCAN_TXBC	Tx Buffer Configuration	0268 10C0h	0269 10C0h
C4h	MCAN_TXFQS	Tx FIFO/Queue Status	0268 10C4h	0269 10C4h
C8h	MCAN_TXESC	Tx Buffer Element Size Configuration	0268 10C8h	0269 10C8h
CCh	MCAN_TXBRP	Tx Buffer Request Pending	0268 10CCh	0269 10CCh
D0h	MCAN_TXBAR	Tx Buffer Add Request	0268 10D0h	0269 10D0h
D4h	MCAN_TXBCR	Tx Buffer Cancellation Request	0268 10D4h	0269 10D4h
D8h	MCAN_TXBTO	Tx Buffer Transmission Occurred	0268 10D8h	0269 10D8h
DCh	MCAN_TXBCF	Tx Buffer Cancellation Finished	0268 10DCh	0269 10DCh
E0h	MCAN_TXBTIE	Tx Buffer Transmission Interrupt Enable	0268 10E0h	0269 10E0h
E4h	MCAN_TXBCIE	Tx Buffer Cancellation Finished Interrupt Enable	0268 10E4h	0269 10E4h
F0h	MCAN_TXEFC	Tx Event FIFO Configuration	0268 10F0h	0269 10F0h
F4h	MCAN_TXEFS	Tx Event FIFO Status	0268 10F4h	0269 10F4h
F8h	MCAN_TXEFA	Tx Event FIFO Acknowledge	0268 10F8h	0269 10F8h

Table 12-5257 MCAN Core Registers

Offset	Acronym	Register Name	MCAN16_CFG Physical Address	MCAN17_CFG Physical Address
0h	MCAN_CREL	Core Release Register	026A 1000h	026B 1000h
4h	MCAN_ENDN	Endian Register	026A 1004h	026B 1004h
Ch	MCAN_DBTP	Data Bit Timing & Prescaler Register	026A 100Ch	026B 100Ch
10h	MCAN_TEST	Test Register	026A 1010h	026B 1010h
14h	MCAN_RWD	RAM Watchdog	026A 1014h	026B 1014h
18h	MCAN_CCCR	CC Control Register	026A 1018h	026B 1018h
1Ch	MCAN_NBTP	Nominal Bit Timing & Prescaler Register	026A 101Ch	026B 101Ch
20h	MCAN_TSCC	Timestamp Counter Configuration	026A 1020h	026B 1020h
24h	MCAN_TSCV	Timestamp Counter Value	026A 1024h	026B 1024h
28h	MCAN_TOCC	Timeout Counter Configuration	026A 1028h	026B 1028h
2Ch	MCAN_TOCV	Timeout Counter Value	026A 102Ch	026B 102Ch
40h	MCAN_ECR	Error Counter Register	026A 1040h	026B 1040h
44h	MCAN_PSR	Protocol Status Register	026A 1044h	026B 1044h
48h	MCAN_TDCR	Transmitter Delay Compensation Register	026A 1048h	026B 1048h
50h	MCAN_IR	Interrupt Register	026A 1050h	026B 1050h
54h	MCAN_IE	Interrupt Enable	026A 1054h	026B 1054h
58h	MCAN_ILS	Interrupt Line Select	026A 1058h	026B 1058h
5Ch	MCAN_ILE	Interrupt Line Enable	026A 105Ch	026B 105Ch
80h	MCAN_GFC	Global Filter Configuration	026A 1080h	026B 1080h
84h	MCAN_SIDFC	Standard ID Filter Configuration	026A 1084h	026B 1084h
88h	MCAN_XIDFC	Extended ID Filter Configuration	026A 1088h	026B 1088h
90h	MCAN_XIDAM	Extended ID AND Mask	026A 1090h	026B 1090h
94h	MCAN_HPMS	High Priority Message Status	026A 1094h	026B 1094h
98h	MCAN_NDAT1	New Data 1	026A 1098h	026B 1098h
9Ch	MCAN_NDAT2	New Data 2	026A 109Ch	026B 109Ch
A0h	MCAN_RXF0C	Rx FIFO 0 Configuration	026A 10A0h	026B 10A0h
A4h	MCAN_RXF0S	Rx FIFO 0 Status	026A 10A4h	026B 10A4h
A8h	MCAN_RXF0A	Rx FIFO 0 Acknowledge	026A 10A8h	026B 10A8h
ACh	MCAN_RXBC	Rx Buffer Configuration	026A 10ACh	026B 10ACh
B0h	MCAN_RXF1C	Rx FIFO 1 Configuration	026A 10B0h	026B 10B0h
B4h	MCAN_RXF1S	Rx FIFO 1 Status	026A 10B4h	026B 10B4h
B8h	MCAN_RXF1A	Rx FIFO 1 Acknowledge	026A 10B8h	026B 10B8h
BCh	MCAN_RXESC	Rx Buffer / FIFO Element Size Configuration	026A 10BCh	026B 10BCh
C0h	MCAN_TXBC	Tx Buffer Configuration	026A 10C0h	026B 10C0h
C4h	MCAN_TXFQS	Tx FIFO/Queue Status	026A 10C4h	026B 10C4h
C8h	MCAN_TXESC	Tx Buffer Element Size Configuration	026A 10C8h	026B 10C8h
CCh	MCAN_TXBRP	Tx Buffer Request Pending	026A 10CCh	026B 10CCh
D0h	MCAN_TXBAR	Tx Buffer Add Request	026A 10D0h	026B 10D0h
D4h	MCAN_TXBCR	Tx Buffer Cancellation Request	026A 10D4h	026B 10D4h
D8h	MCAN_TXBTO	Tx Buffer Transmission Occurred	026A 10D8h	026B 10D8h
DCh	MCAN_TXBCF	Tx Buffer Cancellation Finished	026A 10DCh	026B 10DCh
E0h	MCAN_TXBTIE	Tx Buffer Transmission Interrupt Enable	026A 10E0h	026B 10E0h
E4h	MCAN_TXBCIE	Tx Buffer Cancellation Finished Interrupt Enable	026A 10E4h	026B 10E4h
F0h	MCAN_TXEFC	Tx Event FIFO Configuration	026A 10F0h	026B 10F0h
F4h	MCAN_TXEFS	Tx Event FIFO Status	026A 10F4h	026B 10F4h
F8h	MCAN_TXEFA	Tx Event FIFO Acknowledge	026A 10F8h	026B 10F8h

4.5.2.1 MCAN_CREL Register (Offset = 0h) [reset = 32380608h]

MCAN_CREL is shown in Figure 12-2762 and described in Table 12-5259.

Return to Summary Table.

Core Release Register
Release dependent constant (version + date).

Table 12-5258 MCAN_CREL Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8000h
MCU_MCAN1_CFG	4056 8000h
MCAN0_CFG	0270 1000h
MCAN1_CFG	0271 1000h
MCAN2_CFG	0272 1000h
MCAN3_CFG	0273 1000h
MCAN4_CFG	0274 1000h
MCAN5_CFG	0275 1000h
MCAN6_CFG	0276 1000h
MCAN7_CFG	0277 1000h
MCAN8_CFG	0278 1000h
MCAN9_CFG	0279 1000h
MCAN10_CFG	027A 1000h
MCAN11_CFG	027B 1000h
MCAN12_CFG	027C 1000h
MCAN13_CFG	027D 1000h
MCAN14_CFG	0268 1000h
MCAN15_CFG	0269 1000h
MCAN16_CFG	026A 1000h
MCAN17_CFG	026B 1000h

Figure 12-2762 MCAN_CREL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REL				STEP				SUBSTEP				YEAR
R-3h				R-2h				R-3h				R-8h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MON								DAY
R-6h								R-8h

LEGEND: R = Read Only; -n = value after reset

Table 12-5259 MCAN_CREL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	REL	R	3h	Core Release One digit, BCD-coded.
27-24	STEP	R	2h	Step of Core Release One digit, BCD-coded.
23-20	SUBSTEP	R	3h	Sub-step of Core Release One digit, BCD-coded.
19-16	YEAR	R	8h	Time Stamp Year One digit, BCD-coded.
15-8	MON	R	6h	Time Stamp Month Two digits, BCD-coded.
7-0	DAY	R	8h	Time Stamp Day Two digits, BCD-coded.

4.5.2.2 MCAN_ENDN Register (Offset = 4h) [reset = 8765 4321h]

MCAN_ENDN is shown in Figure 12-2763 and described in Table 12-5261.

Return to Summary Table.

Endian Register
Constant 8765 4321h.

Table 12-5260 MCAN_ENDN Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8004h
MCU_MCAN1_CFG	4056 8004h
MCAN0_CFG	0270 1004h
MCAN1_CFG	0271 1004h
MCAN2_CFG	0272 1004h
MCAN3_CFG	0273 1004h
MCAN4_CFG	0274 1004h
MCAN5_CFG	0275 1004h
MCAN6_CFG	0276 1004h
MCAN7_CFG	0277 1004h
MCAN8_CFG	0278 1004h
MCAN9_CFG	0279 1004h
MCAN10_CFG	027A 1004h
MCAN11_CFG	027B 1004h
MCAN12_CFG	027C 1004h
MCAN13_CFG	027D 1004h
MCAN14_CFG	0268 1004h
MCAN15_CFG	0269 1004h
MCAN16_CFG	026A 1004h
MCAN17_CFG	026B 1004h

Figure 12-2763 MCAN_ENDN Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETV
R-8765 4321h

LEGEND: R = Read Only; -n = value after reset

Table 12-5261 MCAN_ENDN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ETV	R	8765 4321h	Endianness Test Value The endianness test value is 8765 4321h.

Bit

Field

Type

Reset

Description

31-0

ETV

R

8765 4321h

Endianness Test Value

The endianness test value is 8765 4321h.

4.5.2.3 MCAN_DBTP Register (Offset = Ch) [reset = A33h]

MCAN_DBTP is shown in Figure 12-2764 and described in Table 12-5263.

Return to Summary Table.

Data Bit Timing & Prescaler Register
Configuration of data phase bit timing, transmitter delay compensation enable.

This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 49 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 MCAN functional clock periods. t_q = (MCAN_DBTP[20-16] DBRP + 1) mtq (minimum time quantum = CAN clock period (MCAN functional clock)).

The MCAN_DBTP[12-8] DTSEG1 field is the sum of Prop_Seg and Phase_Seg1. The MCAN_DBTP[7-4] DTSEG2 field is Phase_Seg2.

Therefore the length of the bit time is (programmed values) [MCAN_DBTP[12-8] DTSEG1 + MCAN_DBTP[7-4] DTSEG2 + 3] t_q or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] t_q. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Note: With a CAN clock (MCAN functional clock) of 8 MHz, the reset value of 0000 0A33h configures the MCAN module for a data phase bit rate of 500 kbit/s.

Note: The bit rate configured for the CAN FD data phase via the MCAN_DBTP register must be higher or equal to the bit rate configured for the arbitration phase via the MCAN_DBTP register.

Table 12-5262 MCAN_DBTP Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 800Ch
MCU_MCAN1_CFG	4056 800Ch
MCAN0_CFG	0270 100Ch
MCAN1_CFG	0271 100Ch
MCAN2_CFG	0272 100Ch
MCAN3_CFG	0273 100Ch
MCAN4_CFG	0274 100Ch
MCAN5_CFG	0275 100Ch
MCAN6_CFG	0276 100Ch
MCAN7_CFG	0277 100Ch
MCAN8_CFG	0278 100Ch
MCAN9_CFG	0279 100Ch
MCAN10_CFG	027A 100Ch
MCAN11_CFG	027B 100Ch
MCAN12_CFG	027C 100Ch
MCAN13_CFG	027D 100Ch
MCAN14_CFG	0268 100Ch
MCAN15_CFG	0269 100Ch
MCAN16_CFG	026A 100Ch
MCAN17_CFG	026B 100Ch

Figure 12-2764 MCAN_DBTP Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
TDC	RESERVED		DBRP
R/W-0h	R-0h		R/W-0h

15	14	13	12	11	10	9	8
RESERVED			DTSEG1
R-0h			R/W-Ah

7	6	5	4	3	2	1	0
DTSEG2				DSJW
R/W-3h				R/W-3h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5263 MCAN_DBTP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23	TDC	R/W	0h	Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled
22-21	RESERVED	R	0h	Reserved
20-16	DBRP	R/W	0h	Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
15-13	RESERVED	R	0h	Reserved
12-8	DTSEG1	R/W	Ah	Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used.
7-4	DTSEG2	R/W	3h	Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used.
3-0	DSJW	R/W	3h	Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

4.5.2.4 MCAN_TEST Register (Offset = 10h) [reset = 0h]

MCAN_TEST is shown in Figure 12-2765 and described in Table 12-5265.

Return to Summary Table.

Test Register
Test mode selection.

Write access to the MCAN_TEST register has to be enabled by setting the MCAN_CCCR[7] TEST bit. All MCAN_TEST register functions are set to their reset values when the MCAN_CCCR[7] TEST bit is reset.

Loopback Mode and software control of the MCAN TX pin are hardware test modes. Programming of the MCAN_TEST[6-5] TX field ≠ 00 may disturb the message transfer on the CAN bus.

Table 12-5264 MCAN_TEST Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8010h
MCU_MCAN1_CFG	4056 8010h
MCAN0_CFG	0270 1010h
MCAN1_CFG	0271 1010h
MCAN2_CFG	0272 1010h
MCAN3_CFG	0273 1010h
MCAN4_CFG	0274 1010h
MCAN5_CFG	0275 1010h
MCAN6_CFG	0276 1010h
MCAN7_CFG	0277 1010h
MCAN8_CFG	0278 1010h
MCAN9_CFG	0279 1010h
MCAN10_CFG	027A 1010h
MCAN11_CFG	027B 1010h
MCAN12_CFG	027C 1010h
MCAN13_CFG	027D 1010h
MCAN14_CFG	0268 1010h
MCAN15_CFG	0269 1010h
MCAN16_CFG	026A 1010h
MCAN17_CFG	026B 1010h

Figure 12-2765 MCAN_TEST Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RX	TX		LBCK	RESERVED
R-0h	R/W-0h		R/W-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5265 MCAN_TEST Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	RX	R	0h	Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)
6-5	TX	R/W	0h	Control of Transmit Pin 0h = Reset value, the MCAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the MCAN TX pin
4	LBCK	R/W	0h	Loopback Mode 0h = Reset value, Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)
3-0	RESERVED	R	0h	Reserved

4.5.2.5 MCAN_RWD Register (Offset = 14h) [reset = 0h]

MCAN_RWD is shown in Figure 12-2766 and described in Table 12-5267.

RAM Watchdog
Monitors the READY output of the Message RAM.

The RAM Watchdog monitors the READY output of the Message RAM . A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the MCAN_RWD[7-0] WDC field. The counter is reloaded with the MCAN_RWD[7-0] WDC field when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag MCAN_IR[26] WDI is set. The RAM Watchdog Counter is clocked by the Host clock (MCAN interface clock).

Table 12-5266 MCAN_RWD Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8014h
MCU_MCAN1_CFG	4056 8014h
MCAN0_CFG	0270 1014h
MCAN1_CFG	0271 1014h
MCAN2_CFG	0272 1014h
MCAN3_CFG	0273 1014h
MCAN4_CFG	0274 1014h
MCAN5_CFG	0275 1014h
MCAN6_CFG	0276 1014h
MCAN7_CFG	0277 1014h
MCAN8_CFG	0278 1014h
MCAN9_CFG	0279 1014h
MCAN10_CFG	027A 1014h
MCAN11_CFG	027B 1014h
MCAN12_CFG	027C 1014h
MCAN13_CFG	027D 1014h
MCAN14_CFG	0268 1014h
MCAN15_CFG	0269 1014h
MCAN16_CFG	026A 1014h
MCAN17_CFG	026B 1014h

Figure 12-2766 MCAN_RWD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																WDV								WDC
R-0h																R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5267 MCAN_RWD Register Field Descriptions

Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-8

WDV

R

0h

Watchdog Value

Actual Message RAM Watchdog Counter Value.

7-0

WDC

R/W

0h

Watchdog Configuration

Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled.

4.5.2.6 MCAN_CCCR Register (Offset = 18h) [reset = 1h]

MCAN_CCCR is shown in Figure 12-2767 and described in Table 12-5269.

Return to Summary Table.

CC Control Register
Operation mode configuration.

For details about setting and resetting of single bits, see Section 12.4.4.4.3.1, Software Initialization.

Table 12-5268 MCAN_CCCR Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8018h
MCU_MCAN1_CFG	4056 8018h
MCAN0_CFG	0270 1018h
MCAN1_CFG	0271 1018h
MCAN2_CFG	0272 1018h
MCAN3_CFG	0273 1018h
MCAN4_CFG	0274 1018h
MCAN5_CFG	0275 1018h
MCAN6_CFG	0276 1018h
MCAN7_CFG	0277 1018h
MCAN8_CFG	0278 1018h
MCAN9_CFG	0279 1018h
MCAN10_CFG	027A 1018h
MCAN11_CFG	027B 1018h
MCAN12_CFG	027C 1018h
MCAN13_CFG	027D 1018h
MCAN14_CFG	0268 1018h
MCAN15_CFG	0269 1018h
MCAN16_CFG	026A 1018h
MCAN17_CFG	026B 1018h

Figure 12-2767 MCAN_CCCR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
NISO	TXP	EFBI	PXHD	RESERVED		BRSE	FDOE
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
TEST	DAR	MON	CSR	CSA	ASM	CCE	INIT
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h	R/W-0h	R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5269 MCAN_CCCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	NISO	R/W	0h	Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0.
14	TXP	R/W	0h	Transmit Pause If this bit is set, the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled
13	EFBI	R/W	0h	Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t_q required to detect an edge for hard synchronization
12	PXHD	R/W	0h	Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note: When protocol exception handling is disabled, the MCAN module will transmit an error frame when it detects a protocol exception condition.
11-10	RESERVED	R	0h	Reserved
9	BRSE	R/W	0h	Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h, the MCAN_CCCR[9] BRSE bit is not evaluated.
8	FDOE	R/W	0h	FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled
7	TEST	R/W	0h	Test Mode Enable 0h = Normal operation. The MCAN_TEST register holds reset values. 1h = Test Mode. Write access to the MCAN_TEST register enabled.
6	DAR	R/W	0h	Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled
5	MON	R/W	0h	Bus Monitoring Mode The MCAN_CCCR[5] MON bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled
4	CSR	R/W	0h	Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested, first the MCAN_CCCR[0] INIT bit and then the MCAN_CCCR[3] CSA bit will be set after all pending transfer requests have been completed and the CAN bus reached idle.
3	CSA	R	0h	Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock
2	ASM	R/W	0h	Restricted Operation Mode The MCAN_CCCR[2] ASM bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. For a description of the Restricted Operation Mode, see Restricted Operation Mode. 0h = Normal CAN operation 1h = Restricted Operation Mode active
1	CCE	R/W	0h	Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the MCAN_CCCR[0] INIT = 1h)
0	INIT	R/W	1h	Initialization 0h = Normal Operation 1h = Initialization is started Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the software has to assure that the previous value written to the MCAN_CCCR[0] INIT bit has been accepted by reading the MCAN_CCCR[0] INIT bit before setting the MCAN_CCCR[0] INIT bit to a new value.

4.5.2.7 MCAN_NBTP Register (Offset = 1Ch) [reset = 06000A03h]

MCAN_NBTP is shown in Figure 12-2768 and described in Table 12-5271.

Return to Summary Table.

Nominal Bit Timing & Prescaler Register
Configuration of arbitration phase bit timing.

This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN time quantum may be programmed in the range of 1 to 512 MCAN functional clock periods. t_q = (MCAN_NBTP[24-16] NBRP + 1) mtq. The MCAN_NBTP[15-8] NTSEG1 field is the sum of Prop_Seg and Phase_Seg1. The MCAN_NBTP[6-0] NTSEG2 field is Phase_Seg2.

Therefore the length of the bit time is (programmed values) [MCAN_NBTP[15-8] NTSEG1 + MCAN_NBTP[6-0] NTSEG2 + 3] t_q or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] t_q.

The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Table 12-5270 MCAN_NBTP Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 801Ch
MCU_MCAN1_CFG	4056 801Ch
MCAN0_CFG	0270 101Ch
MCAN1_CFG	0271 101Ch
MCAN2_CFG	0272 101Ch
MCAN3_CFG	0273 101Ch
MCAN4_CFG	0274 101Ch
MCAN5_CFG	0275 101Ch
MCAN6_CFG	0276 101Ch
MCAN7_CFG	0277 101Ch
MCAN8_CFG	0278 101Ch
MCAN9_CFG	0279 101Ch
MCAN10_CFG	027A 101Ch
MCAN11_CFG	027B 101Ch
MCAN12_CFG	027C 101Ch
MCAN13_CFG	027D 101Ch
MCAN14_CFG	0268 101Ch
MCAN15_CFG	0269 101Ch
MCAN16_CFG	026A 101Ch
MCAN17_CFG	026B 101Ch

Figure 12-2768 MCAN_NBTP Register

31	30	29	28	27	26	25	24
NSJW							NBRP
R/W-3h							R/W-0h

23	22	21	20	19	18	17	16
NBRP
R/W-0h

15	14	13	12	11	10	9	8
NTSEG1
R/W-Ah

7	6	5	4	3	2	1	0
RESERVED	NTSEG2
R-0h	R/W-3h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5271 MCAN_NBTP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	NSJW	R/W	3h	Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
24-16	NBRP	R/W	0h	Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
15-8	NTSEG1	R/W	Ah	Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used.
7	RESERVED	R	0h	Reserved
6-0	NTSEG2	R/W	3h	Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note: With a CAN clock (MCAN functional clock) of 8 MHz, the reset value of 0600 0A03h configures the MCAN module for a bit rate of 500 kbit/s.

4.5.2.8 MCAN_TSCC Register (Offset = 20h) [reset = 0h]

MCAN_TSCC is shown in Figure 12-2769 and described in Table 12-5273.

Return to Summary Table.

Timestamp Counter Configuration
Timestamp counter prescaler setting, selection of internal/external timestamp vector.

For a description of the Timestamp Counter, see Section 12.4.4.4.4, Timestamp Generation.

Table 12-5272 MCAN_TSCC Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8020h
MCU_MCAN1_CFG	4056 8020h
MCAN0_CFG	0270 1020h
MCAN1_CFG	0271 1020h
MCAN2_CFG	0272 1020h
MCAN3_CFG	0273 1020h
MCAN4_CFG	0274 1020h
MCAN5_CFG	0275 1020h
MCAN6_CFG	0276 1020h
MCAN7_CFG	0277 1020h
MCAN8_CFG	0278 1020h
MCAN9_CFG	0279 1020h
MCAN10_CFG	027A 1020h
MCAN11_CFG	027B 1020h
MCAN12_CFG	027C 1020h
MCAN13_CFG	027D 1020h
MCAN14_CFG	0268 1020h
MCAN15_CFG	0269 1020h
MCAN16_CFG	026A 1020h
MCAN17_CFG	026B 1020h

Figure 12-2769 MCAN_TSCC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												TCP
R-0h												R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														TSS
R-0h														R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5273 MCAN_TSCC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	TCP	R/W	0h	Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With CAN FD an external counter is required for timestamp generation (MCAN_TSCC[1-0] TSS = 2h)
15-2	RESERVED	R	0h	Reserved
1-0	TSS	R/W	0h	Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the MCAN_TSCC[19-16] TCP field 2h = External timestamp counter value used 3h = Same as 0h

4.5.2.9 MCAN_TSCV Register (Offset = 24h) [reset = 0h]

MCAN_TSCV is shown in Figure 12-2770 and described in Table 12-5275.

Return to Summary Table.

Timestamp Counter Value
Read/reset timestamp counter.

Table 12-5274 MCAN_TSCV Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8024h
MCU_MCAN1_CFG	4056 8024h
MCAN0_CFG	0270 1024h
MCAN1_CFG	0271 1024h
MCAN2_CFG	0272 1024h
MCAN3_CFG	0273 1024h
MCAN4_CFG	0274 1024h
MCAN5_CFG	0275 1024h
MCAN6_CFG	0276 1024h
MCAN7_CFG	0277 1024h
MCAN8_CFG	0278 1024h
MCAN9_CFG	0279 1024h
MCAN10_CFG	027A 1024h
MCAN11_CFG	027B 1024h
MCAN12_CFG	027C 1024h
MCAN13_CFG	027D 1024h
MCAN14_CFG	0268 1024h
MCAN15_CFG	0269 1024h
MCAN16_CFG	026A 1024h
MCAN17_CFG	026B 1024h

Figure 12-2770 MCAN_TSCV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																TSC
R-0h																RWTC-0h

LEGEND: R = Read Only; RWTC = Read/Write to Clear Field; -n = value after reset

Table 12-5275 MCAN_TSCV Register Field Descriptions

Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-0

TSC

RWTC

0h

Timestamp Counter

The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).

When the MCAN_TSCC[1-0] TSS = 1h, the Timestamp Counter is incremented in multiples of CAN bit times

[1-16] depending on the configuration of the MCAN_TSCC[19-16] TCP field. A wrap around sets interrupt flag MCAN_IR[16] TSW.

Write access resets the counter to zero. When the MCAN_TSCC[1-0] TSS = 2h, the MCAN_TSCV[15-0] TSC field reflects the external Timestamp Counter value. A write access has no impact.

Note: A 'wrap around' is a change of the Timestamp Counter value from non-zero to zero not caused by write access to the MCAN_TSCV register.

4.5.2.10 MCAN_TOCC Register (Offset = 28h) [reset = FFFF0000h]

MCAN_TOCC is shown in Figure 12-2771 and described in Table 12-5277.

Return to Summary Table.

Timeout Counter Configuration
Configuration of timeout period, selection of timeout counter operation mode.

For a description of the Timeout Counter, see Section 12.4.4.4.5, Timeout Counter.

Table 12-5276 MCAN_TOCC Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8028h
MCU_MCAN1_CFG	4056 8028h
MCAN0_CFG	0270 1028h
MCAN1_CFG	0271 1028h
MCAN2_CFG	0272 1028h
MCAN3_CFG	0273 1028h
MCAN4_CFG	0274 1028h
MCAN5_CFG	0275 1028h
MCAN6_CFG	0276 1028h
MCAN7_CFG	0277 1028h
MCAN8_CFG	0278 1028h
MCAN9_CFG	0279 1028h
MCAN10_CFG	027A 1028h
MCAN11_CFG	027B 1028h
MCAN12_CFG	027C 1028h
MCAN13_CFG	027D 1028h
MCAN14_CFG	0268 1028h
MCAN15_CFG	0269 1028h
MCAN16_CFG	026A 1028h
MCAN17_CFG	026B 1028h

Figure 12-2771 MCAN_TOCC Register

31	30	29	28	27	26	25	24
TOP
R/W-FFFFh

23	22	21	20	19	18	17	16
TOP
R/W-FFFFh

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					TOS		ETOC
R-0h					R/W-0h		R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5277 MCAN_TOCC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	TOP	R/W	FFFFh	Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period.
15-3	RESERVED	R	0h	Reserved
2-1	TOS	R/W	0h	Timeout Select When operating in Continuous mode, a write to the MCAN_TOCV[15-0] TOC field presets the counter to the value configured by the MCAN_TOCC[31-16] TOP field and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by the MCAN_TOCC[31-16] TOP field. Down-counting is started when the first FIFO element is stored. 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1
0	ETOC	R/W	0h	Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled

4.5.2.11 MCAN_TOCV Register (Offset = 2Ch) [reset = FFFFh]

MCAN_TOCV is shown in Figure 12-2772 and described in Table 12-5279.

Return to Summary Table.

Timeout Counter Value
Read/reset timeout counter.

Table 12-5278 MCAN_TOCV Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 802Ch
MCU_MCAN1_CFG	4056 802Ch
MCAN0_CFG	0270 102Ch
MCAN1_CFG	0271 102Ch
MCAN2_CFG	0272 102Ch
MCAN3_CFG	0273 102Ch
MCAN4_CFG	0274 102Ch
MCAN5_CFG	0275 102Ch
MCAN6_CFG	0276 102Ch
MCAN7_CFG	0277 102Ch
MCAN8_CFG	0278 102Ch
MCAN9_CFG	0279 102Ch
MCAN10_CFG	027A 102Ch
MCAN11_CFG	027B 102Ch
MCAN12_CFG	027C 102Ch
MCAN13_CFG	027D 102Ch
MCAN14_CFG	0268 102Ch
MCAN15_CFG	0269 102Ch
MCAN16_CFG	026A 102Ch
MCAN17_CFG	026B 102Ch

Figure 12-2772 MCAN_TOCV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																TOC
R-0h																RWTC-FFFFh

LEGEND: R = Read Only; RWTC = Read/Write to Clear Field; -n = value after reset

Table 12-5279 MCAN_TOCV Register Field Descriptions

Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-0

TOC

RWTC

FFFFh

Timeout Counter

The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the MCAN_TSCC[19-16] TCP field. When decremented to zero, interrupt flag MCAN_IR[18] TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via the MCAN_TOCC[2-1] TOS field.

4.5.2.12 MCAN_ECR Register (Offset = 40h) [reset = 0h]

MCAN_ECR is shown in Figure 12-2773 and described in Table 12-5281.

Return to Summary Table.

Error Counter Register
State of Rx/Tx Error Counter, CAN Error Logging.

Table 12-5280 MCAN_ECR Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8040h
MCU_MCAN1_CFG	4056 8040h
MCAN0_CFG	0270 1040h
MCAN1_CFG	0271 1040h
MCAN2_CFG	0272 1040h
MCAN3_CFG	0273 1040h
MCAN4_CFG	0274 1040h
MCAN5_CFG	0275 1040h
MCAN6_CFG	0276 1040h
MCAN7_CFG	0277 1040h
MCAN8_CFG	0278 1040h
MCAN9_CFG	0279 1040h
MCAN10_CFG	027A 1040h
MCAN11_CFG	027B 1040h
MCAN12_CFG	027C 1040h
MCAN13_CFG	027D 1040h
MCAN14_CFG	0268 1040h
MCAN15_CFG	0269 1040h
MCAN16_CFG	026A 1040h
MCAN17_CFG	026B 1040h

Figure 12-2773 MCAN_ECR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED								CEL
R-0h								R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RP	REC							TEC
R-0h	R-0h							R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-5281 MCAN_ECR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-16	CEL	R	0h	CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the MCAN_ECR[23-16] CEL field. The counter stops at FFh; the next increment of the MCAN_ECR[7-0] TEC or MCAN_ECR[14-8] REC fields sets interrupt flag MCAN_IR[22] ELO.
15	RP	R	0h	Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128
14-8	REC	R	0h	Receive Error Counter Actual state of the Receive Error Counter, values between 0 and 127.
7-0	TEC	R	0h	Transmit Error Counter Actual state of the Transmit Error Counter, values between 0 and 255. Note: When the MCAN_CCCR[2] ASM bit is set, the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN protocol error is detected, but the MCAN_ECR[23-16] CEL field is still incremented.

4.5.2.13 MCAN_PSR Register (Offset = 44h) [reset = 707h]

MCAN_PSR is shown in Figure 12-2774 and described in Table 12-5283.

Return to Summary Table.

Protocol Status Register
CAN protocol controller status, transmitter delay compensation value.

Table 12-5282 MCAN_PSR Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8044h
MCU_MCAN1_CFG	4056 8044h
MCAN0_CFG	0270 1044h
MCAN1_CFG	0271 1044h
MCAN2_CFG	0272 1044h
MCAN3_CFG	0273 1044h
MCAN4_CFG	0274 1044h
MCAN5_CFG	0275 1044h
MCAN6_CFG	0276 1044h
MCAN7_CFG	0277 1044h
MCAN8_CFG	0278 1044h
MCAN9_CFG	0279 1044h
MCAN10_CFG	027A 1044h
MCAN11_CFG	027B 1044h
MCAN12_CFG	027C 1044h
MCAN13_CFG	027D 1044h
MCAN14_CFG	0268 1044h
MCAN15_CFG	0269 1044h
MCAN16_CFG	026A 1044h
MCAN17_CFG	026B 1044h

Figure 12-2774 MCAN_PSR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED	TDCV
R-0h	R-0h

15	14	13	12	11	10	9	8
RESERVED	PXE	RFDF	RBRS	RESI	DLEC
R-0h	R-0h	R-0h	R-0h	R-0h	R-7h

7	6	5	4	3	2	1	0
BO	EW	EP	ACT		LEC
R-0h	R-0h	R-0h	R-0h		R-7h

LEGEND: R = Read Only; -n = value after reset

Table 12-5283 MCAN_PSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R	0h	Reserved
22-16	TDCV	R	0h	Transmitter Delay Compensation Value Position of the secondary sample point, defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the MCAN_TDCR[14-8] TDCO field. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh).
15	RESERVED	R	0h	Reserved
14	PXE	R	0h	Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred
13	RFDF	R	0h	Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU, no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received
12	RBRS	R	0h	BRS flag of last received CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit, independent of acceptance filtering. 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set
11	RESI	R	0h	ESI flag of last received CAN FD Message This bit is set together with the MCAN_PSR[13] RFDF bit, independent of acceptance filtering. 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set
10-8	DLEC	R	7h	Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the MCAN_PSR[2-0] LEC field. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.
7	BO	R	0h	Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state
6	EW	R	0h	Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96
5	EP	R	0h	Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state
4-3	ACT	R	0h	Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is operating as transmitter Note: ACT is set to 0h by a Protocol Exception Event.
2-0	LEC	R	7h	Last Error Code The MCAN_PSR[2-0] LEC field indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0h when a message has been transferred (reception or transmission) without error. 0h = No Error: No error occurred since the MCAN_PSR[2-0] LEC field has been reset by successful reception or transmission. 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame has the wrong format. 3h = AckError: The message transmitted by the MCAN module was not acknowledged by another node. 4h = Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 5h = Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the Host CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6h = CRCError: The CRC check sum of a received message was incorrect. The CRC of an incom-ing message does not match with the CRC calculated from the received data. 7h = NoChange: Any read access to the Protocol Status Register re-initializes the MCAN_PSR[2-0] LEC field to 7h. When the MCAN_PSR[2-0] LEC field shows the value 7h, no CAN bus event was detected since the last Host CPU read access to the Protocol Status Register. Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in the MCAN_PSR[10-8] DLEC field instead of the MCAN_PSR[2-0] LEC field. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error.

4.5.2.14 MCAN_TDCR Register (Offset = 48h) [reset = 0h]

MCAN_TDCR is shown in Figure 12-2775 and described in Table 12-5285.

Return to Summary Table.

Transmitter Delay Comensation Register
Configuration of transmitter delay compensation offset and filter window length.

Table 12-5284 MCAN_TDCR Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8048h
MCU_MCAN1_CFG	4056 8048h
MCAN0_CFG	0270 1048h
MCAN1_CFG	0271 1048h
MCAN2_CFG	0272 1048h
MCAN3_CFG	0273 1048h
MCAN4_CFG	0274 1048h
MCAN5_CFG	0275 1048h
MCAN6_CFG	0276 1048h
MCAN7_CFG	0277 1048h
MCAN8_CFG	0278 1048h
MCAN9_CFG	0279 1048h
MCAN10_CFG	027A 1048h
MCAN11_CFG	027B 1048h
MCAN12_CFG	027C 1048h
MCAN13_CFG	027D 1048h
MCAN14_CFG	0268 1048h
MCAN15_CFG	0269 1048h
MCAN16_CFG	026A 1048h
MCAN17_CFG	026B 1048h

Figure 12-2775 MCAN_TDCR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED	TDCO
R-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	TDCF
R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5285 MCAN_TDCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-15	RESERVED	R	0h	Reserved
14-8	TDCO	R/W	0h	Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh).
7	RESERVED	R	0h	Reserved
6-0	TDCF	R/W	0h	Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position, dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled when the MCAN_TDCR[6-0] TDCF field is configured to a value greater than the MCAN_TDCR[14-8] TDCO field. Valid values are 0 to 127 mtq (0h-7Fh).

4.5.2.15 MCAN_IR Register (Offset = 50h) [reset = 0h]

MCAN_IR is shown in Figure 12-2776 and described in Table 12-5287.

Return to Summary Table.

Interrupt Register

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no effect. A hard reset will clear the register. The configuration of the MCAN_IE register controls whether an interrupt is generated. The configuration of the MCAN_ILS register controls on which interrupt line an interrupt is signalled.

Table 12-5286 MCAN_IR Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8050h
MCU_MCAN1_CFG	4056 8050h
MCAN0_CFG	0270 1050h
MCAN1_CFG	0271 1050h
MCAN2_CFG	0272 1050h
MCAN3_CFG	0273 1050h
MCAN4_CFG	0274 1050h
MCAN5_CFG	0275 1050h
MCAN6_CFG	0276 1050h
MCAN7_CFG	0277 1050h
MCAN8_CFG	0278 1050h
MCAN9_CFG	0279 1050h
MCAN10_CFG	027A 1050h
MCAN11_CFG	027B 1050h
MCAN12_CFG	027C 1050h
MCAN13_CFG	027D 1050h
MCAN14_CFG	0268 1050h
MCAN15_CFG	0269 1050h
MCAN16_CFG	026A 1050h
MCAN17_CFG	026B 1050h

Figure 12-2776 MCAN_IR Register

31	30	29	28	27	26	25	24
RESERVED		ARA	PED	PEA	WDI	BO	EW
R-0h		RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

23	22	21	20	19	18	17	16
EP	ELO	BEU	RESERVED	DRX	TOO	MRAF	TSW
RW1TC-0h	RW1TC-0h	RW1TC-0h	R-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

15	14	13	12	11	10	9	8
TEFL	TEFF	TEFW	TEFN	TFE	TCF	TC	HPM
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

7	6	5	4	3	2	1	0
RF1L	RF1F	RF1W	RF1N	RF0L	RF0F	RF0W	RF0N
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

LEGEND: R = Read Only; RW1TC = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-5287 MCAN_IR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	0h	Reserved
29	ARA	RW1TC	0h	Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred
28	PED	RW1TC	0h	Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (MCAN_PSR[10-8] DLEC ≠ 0.7)
27	PEA	RW1TC	0h	Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (MCAN_PSR[2-0] LEC ≠ 0.7)
26	WDI	RW1TC	0h	Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY
25	BO	RW1TC	0h	Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed
24	EW	RW1TC	0h	Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed
23	EP	RW1TC	0h	Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed
22	ELO	RW1TC	0h	Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred
21	BEU	RW1TC	0h	Bit Error Uncorrected Message RAM bit error detected, uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the MCAN_CCCR[0] INIT bit to 1. This is done to avoid transmission of corrupted data. 0h = No bit error detected when reading from Message RAM 1h = Bit error detected, uncorrected (example: parity logic)
20	RESERVED	R	0h	Reserved
19	DRX	RW1TC	0h	Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer
18	TOO	RW1TC	0h	Timeout Occurred 0h = No timeout 1h = Timeout reached
17	MRAF	RW1TC	0h	Message RAM Access Failure The flag is set, when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. b) was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated respectively the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN module is switched into Restricted Operation Mode (see Restricted Operation Mode). To leave Restricted Operation Mode, the Host CPU has to reset the MCAN_CCCR[2] ASM bit. 0h = No Message RAM access failure occurred 1h = Message RAM access failure occurred
16	TSW	RW1TC	0h	Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around
15	TEFL	RW1TC	0h	Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero
14	TEFF	RW1TC	0h	Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full
13	TEFW	RW1TC	0h	Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark
12	TEFN	RW1TC	0h	Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element
11	TFE	RW1TC	0h	Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty
10	TCF	RW1TC	0h	Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished
9	TC	RW1TC	0h	Transmission Completed 0h = No transmission completed 1h = Transmission completed
8	HPM	RW1TC	0h	High Priority Message 0h = No high priority message received 1h = High priority message received
7	RF1L	RW1TC	0h	Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero
6	RF1F	RW1TC	0h	Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full
5	RF1W	RW1TC	0h	Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark
4	RF1N	RW1TC	0h	Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1
3	RF0L	RW1TC	0h	Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero
2	RF0F	RW1TC	0h	Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full
1	RF0W	RW1TC	0h	Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark
0	RF0N	RW1TC	0h	Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0

4.5.2.16 MCAN_IE Register (Offset = 54h) [reset = 0h]

MCAN_IE is shown in Figure 12-2777 and described in Table 12-5289.

Return to Summary Table.

Interrupt Enable

The settings in the Interrupt Enable register determine which status changes in the MCAN_IR register are signalled on an interrupt line.

Table 12-5288 MCAN_IE Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8054h
MCU_MCAN1_CFG	4056 8054h
MCAN0_CFG	0270 1054h
MCAN1_CFG	0271 1054h
MCAN2_CFG	0272 1054h
MCAN3_CFG	0273 1054h
MCAN4_CFG	0274 1054h
MCAN5_CFG	0275 1054h
MCAN6_CFG	0276 1054h
MCAN7_CFG	0277 1054h
MCAN8_CFG	0278 1054h
MCAN9_CFG	0279 1054h
MCAN10_CFG	027A 1054h
MCAN11_CFG	027B 1054h
MCAN12_CFG	027C 1054h
MCAN13_CFG	027D 1054h
MCAN14_CFG	0268 1054h
MCAN15_CFG	0269 1054h
MCAN16_CFG	026A 1054h
MCAN17_CFG	026B 1054h

Figure 12-2777 MCAN_IE Register

31	30	29	28	27	26	25	24
RESERVED		ARAE	PEDE	PEAE	WDIE	BOE	EWE
R-0h		R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
EPE	ELOE	BEUE	BECE	DRX	TOOE	MRAFE	TSWE
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
TEFLE	TEFFE	TEFWE	TEFNE	TFEE	TCFE	TCE	HPME
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RF1LE	RF1FE	RF1WE	RF1NE	RF0LE	RF0FE	RF0WE	RF0NE
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5289 MCAN_IE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	0h	Reserved
29	ARAE	R/W	0h	Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled
28	PEDE	R/W	0h	Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled
27	PEAE	R/W	0h	Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled
26	WDIE	R/W	0h	Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
25	BOE	R/W	0h	Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
24	EWE	R/W	0h	Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
23	EPE	R/W	0h	Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
22	ELOE	R/W	0h	Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
21	BEUE	R/W	0h	Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
20	BECE	R/W	0h	Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
19	DRX	R/W	0h	Message stored to Dedicated Rx Buffer Interrupt Enable
18	TOOE	R/W	0h	Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
17	MRAFE	R/W	0h	Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
16	TSWE	R/W	0h	Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
15	TEFLE	R/W	0h	Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
14	TEFFE	R/W	0h	Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
13	TEFWE	R/W	0h	Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
12	TEFNE	R/W	0h	Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
11	TFEE	R/W	0h	Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
10	TCFE	R/W	0h	Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
9	TCE	R/W	0h	Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
8	HPME	R/W	0h	High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
7	RF1LE	R/W	0h	Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
6	RF1FE	R/W	0h	Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
5	RF1WE	R/W	0h	Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
4	RF1NE	R/W	0h	Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
3	RF0LE	R/W	0h	Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
2	RF0FE	R/W	0h	Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
1	RF0WE	R/W	0h	Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled
0	RF0NE	R/W	0h	Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled

4.5.2.17 MCAN_ILS Register (Offset = 58h) [reset = 0h]

MCAN_ILS is shown in Figure 12-2778 and described in Table 12-5291.

Return to Summary Table.

Interrupt Line Select

The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the MCAN_IR register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via the MCAN_ILE[0] EINT0 and MCAN_ILE[1] EINT1 bits.

Table 12-5290 MCAN_ILS Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8058h
MCU_MCAN1_CFG	4056 8058h
MCAN0_CFG	0270 1058h
MCAN1_CFG	0271 1058h
MCAN2_CFG	0272 1058h
MCAN3_CFG	0273 1058h
MCAN4_CFG	0274 1058h
MCAN5_CFG	0275 1058h
MCAN6_CFG	0276 1058h
MCAN7_CFG	0277 1058h
MCAN8_CFG	0278 1058h
MCAN9_CFG	0279 1058h
MCAN10_CFG	027A 1058h
MCAN11_CFG	027B 1058h
MCAN12_CFG	027C 1058h
MCAN13_CFG	027D 1058h
MCAN14_CFG	0268 1058h
MCAN15_CFG	0269 1058h
MCAN16_CFG	026A 1058h
MCAN17_CFG	026B 1058h

Figure 12-2778 MCAN_ILS Register

31	30	29	28	27	26	25	24
RESERVED		ARAL	PEDL	PEAL	WDIL	BOL	EWL
R-0h		R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
EPL	ELOL	BEUL	BECL	DRXL	TOOL	MRAFL	TSWL
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
TEFLL	TEFFL	TEFWL	TEFNL	TFEL	TCFL	TCL	HPML
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RF1LL	RF1FL	RF1WL	RF1NL	RF0LL	RF0FL	RF0WL	RF0NL
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5291 MCAN_ILS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	0h	Reserved
29	ARAL	R/W	0h	Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
28	PEDL	R/W	0h	Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
27	PEAL	R/W	0h	Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
26	WDIL	R/W	0h	Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
25	BOL	R/W	0h	Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
24	EWL	R/W	0h	Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
23	EPL	R/W	0h	Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
22	ELOL	R/W	0h	Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
21	BEUL	R/W	0h	Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
20	BECL	R/W	0h	Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
19	DRXL	R/W	0h	Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
18	TOOL	R/W	0h	Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
17	MRAFL	R/W	0h	Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
16	TSWL	R/W	0h	Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
15	TEFLL	R/W	0h	Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
14	TEFFL	R/W	0h	Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
13	TEFWL	R/W	0h	Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
12	TEFNL	R/W	0h	Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
11	TFEL	R/W	0h	Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
10	TCFL	R/W	0h	Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
9	TCL	R/W	0h	Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
8	HPML	R/W	0h	High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
7	RF1LL	R/W	0h	Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
6	RF1FL	R/W	0h	Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
5	RF1WL	R/W	0h	Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
4	RF1NL	R/W	0h	Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
3	RF0LL	R/W	0h	Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
2	RF0FL	R/W	0h	Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
1	RF0WL	R/W	0h	Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1
0	RF0NL	R/W	0h	Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1

4.5.2.18 MCAN_ILE Register (Offset = 5Ch) [reset = 0h]

MCAN_ILE is shown in Figure 12-2779 and described in Table 12-5293.

Return to Summary Table.

Interrupt Line Enable
Enable/disable interrupt lines INT0/INT1.

Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the MCAN_ILE[0] EINT0 and MCAN_ILE[1] EINT1 bits.

Table 12-5292 MCAN_ILE Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 805Ch
MCU_MCAN1_CFG	4056 805Ch
MCAN0_CFG	0270 105Ch
MCAN1_CFG	0271 105Ch
MCAN2_CFG	0272 105Ch
MCAN3_CFG	0273 105Ch
MCAN4_CFG	0274 105Ch
MCAN5_CFG	0275 105Ch
MCAN6_CFG	0276 105Ch
MCAN7_CFG	0277 105Ch
MCAN8_CFG	0278 105Ch
MCAN9_CFG	0279 105Ch
MCAN10_CFG	027A 105Ch
MCAN11_CFG	027B 105Ch
MCAN12_CFG	027C 105Ch
MCAN13_CFG	027D 105Ch
MCAN14_CFG	0268 105Ch
MCAN15_CFG	0269 105Ch
MCAN16_CFG	026A 105Ch
MCAN17_CFG	026B 105Ch

Figure 12-2779 MCAN_ILE Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						EINT1	EINT0
R-0h						R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5293 MCAN_ILE Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

R

0h

Reserved

1

EINT1

R/W

0h

Enable Interrupt Line 1

0h = Interrupt line INT1 disabled

1h = Interrupt line INT1 enabled

0

EINT0

R/W

0h

Enable Interrupt Line 0

0h = Interrupt line INT0 disabled

1h = Interrupt line INT0 enabled

4.5.2.19 MCAN_GFC Register (Offset = 80h) [reset = 0h]

MCAN_GFC is shown in Figure 12-2780 and described in Table 12-5295.

Return to Summary Table.

Global Filter Configuration
Handling of non-matching frames and remote frames.

Global settings for Message ID filtering. The MCAN_GFC register controls the filter path for standard and extended messages (see Figure 12-2739 and Figure 12-2740).

Table 12-5294 MCAN_GFC Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8080h
MCU_MCAN1_CFG	4056 8080h
MCAN0_CFG	0270 1080h
MCAN1_CFG	0271 1080h
MCAN2_CFG	0272 1080h
MCAN3_CFG	0273 1080h
MCAN4_CFG	0274 1080h
MCAN5_CFG	0275 1080h
MCAN6_CFG	0276 1080h
MCAN7_CFG	0277 1080h
MCAN8_CFG	0278 1080h
MCAN9_CFG	0279 1080h
MCAN10_CFG	027A 1080h
MCAN11_CFG	027B 1080h
MCAN12_CFG	027C 1080h
MCAN13_CFG	027D 1080h
MCAN14_CFG	0268 1080h
MCAN15_CFG	0269 1080h
MCAN16_CFG	026A 1080h
MCAN17_CFG	026B 1080h

Figure 12-2780 MCAN_GFC Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		ANFS		ANFE		RRFS	RRFE
R-0h		R/W-0h		R/W-0h		R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5295 MCAN_GFC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5-4	ANFS	R/W	0h	Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject
3-2	ANFE	R/W	0h	Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject
1	RRFS	R/W	0h	Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs
0	RRFE	R/W	0h	Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs

4.5.2.20 MCAN_SIDFC Register (Offset = 84h) [reset = 0h]

MCAN_SIDFC is shown in Figure 12-2781 and described in Table 12-5297.

Return to Summary Table.

Standard ID Filter Configuration
Number of filter elements, pointer to start of filter list.

Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see Figure 12-2739).

Table 12-5296 MCAN_SIDFC Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8084h
MCU_MCAN1_CFG	4056 8084h
MCAN0_CFG	0270 1084h
MCAN1_CFG	0271 1084h
MCAN2_CFG	0272 1084h
MCAN3_CFG	0273 1084h
MCAN4_CFG	0274 1084h
MCAN5_CFG	0275 1084h
MCAN6_CFG	0276 1084h
MCAN7_CFG	0277 1084h
MCAN8_CFG	0278 1084h
MCAN9_CFG	0279 1084h
MCAN10_CFG	027A 1084h
MCAN11_CFG	027B 1084h
MCAN12_CFG	027C 1084h
MCAN13_CFG	027D 1084h
MCAN14_CFG	0268 1084h
MCAN15_CFG	0269 1084h
MCAN16_CFG	026A 1084h
MCAN17_CFG	026B 1084h

Figure 12-2781 MCAN_SIDFC Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
LSS
R/W-0h

15	14	13	12	11	10	9	8
FLSSA
R/W-0h

7	6	5	4	3	2	1	0
FLSSA						RESERVED
R/W-0h						R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5297 MCAN_SIDFC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-16	LSS	R/W	0h	List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements > 80h (128) = Values greater than 128 are interpreted as 128
15-2	FLSSA	R/W	0h	Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address, see Message RAM Configuration).
1-0	RESERVED	R	0h	Reserved

4.5.2.21 MCAN_XIDFC Register (Offset = 88h) [reset = 0h]

MCAN_XIDFC is shown in Figure 12-2782 and described in Table 12-5299.

Return to Summary Table.

Extended ID Filter Configuration
Number of filter elements, pointer to start of filter list.

Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see Figure 12-2740).

Table 12-5298 MCAN_XIDFC Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8088h
MCU_MCAN1_CFG	4056 8088h
MCAN0_CFG	0270 1088h
MCAN1_CFG	0271 1088h
MCAN2_CFG	0272 1088h
MCAN3_CFG	0273 1088h
MCAN4_CFG	0274 1088h
MCAN5_CFG	0275 1088h
MCAN6_CFG	0276 1088h
MCAN7_CFG	0277 1088h
MCAN8_CFG	0278 1088h
MCAN9_CFG	0279 1088h
MCAN10_CFG	027A 1088h
MCAN11_CFG	027B 1088h
MCAN12_CFG	027C 1088h
MCAN13_CFG	027D 1088h
MCAN14_CFG	0268 1088h
MCAN15_CFG	0269 1088h
MCAN16_CFG	026A 1088h
MCAN17_CFG	026B 1088h

Figure 12-2782 MCAN_XIDFC Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED	LSE
R-0h	R/W-0h

15	14	13	12	11	10	9	8
FLESA
R/W-0h

7	6	5	4	3	2	1	0
FLESA						RESERVED
R/W-0h						R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5299 MCAN_XIDFC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R	0h	Reserved
22-16	LSE	R/W	0h	List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements > 40h (64) = Values greater than 64 are interpreted as 64
15-2	FLESA	R/W	0h	Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address, see Message RAM Configuration).
1-0	RESERVED	R	0h	Reserved

4.5.2.22 MCAN_XIDAM Register (Offset = 90h) [reset = 1FFFFFFFh]

MCAN_XIDAM is shown in Figure 12-2783 and described in Table 12-5301.

Return to Summary Table.

Extended ID AND Mask
29-bit logical AND mask for J1939.

Table 12-5300 MCAN_XIDAM Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8090h
MCU_MCAN1_CFG	4056 8090h
MCAN0_CFG	0270 1090h
MCAN1_CFG	0271 1090h
MCAN2_CFG	0272 1090h
MCAN3_CFG	0273 1090h
MCAN4_CFG	0274 1090h
MCAN5_CFG	0275 1090h
MCAN6_CFG	0276 1090h
MCAN7_CFG	0277 1090h
MCAN8_CFG	0278 1090h
MCAN9_CFG	0279 1090h
MCAN10_CFG	027A 1090h
MCAN11_CFG	027B 1090h
MCAN12_CFG	027C 1090h
MCAN13_CFG	027D 1090h
MCAN14_CFG	0268 1090h
MCAN15_CFG	0269 1090h
MCAN16_CFG	026A 1090h
MCAN17_CFG	026B 1090h

Figure 12-2783 MCAN_XIDAM Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED			EIDM
R-0h			R/W-1FFFFFFFh

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EIDM
R/W-1FFFFFFFh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5301 MCAN_XIDAM Register Field Descriptions

Bit

Field

Type

Reset

Description

31-29

RESERVED

R

0h

Reserved

28-0

EIDM

R/W

1FFFFFFFh

Extended ID Mask

For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active.

4.5.2.23 MCAN_HPMS Register (Offset = 94h) [reset = 0h]

MCAN_HPMS is shown in Figure 12-2784 and described in Table 12-5303.

Return to Summary Table.

High Priority Message Status
Status monitoring of incoming high priority messages.

This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.

Table 12-5302 MCAN_HPMS Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8094h
MCU_MCAN1_CFG	4056 8094h
MCAN0_CFG	0270 1094h
MCAN1_CFG	0271 1094h
MCAN2_CFG	0272 1094h
MCAN3_CFG	0273 1094h
MCAN4_CFG	0274 1094h
MCAN5_CFG	0275 1094h
MCAN6_CFG	0276 1094h
MCAN7_CFG	0277 1094h
MCAN8_CFG	0278 1094h
MCAN9_CFG	0279 1094h
MCAN10_CFG	027A 1094h
MCAN11_CFG	027B 1094h
MCAN12_CFG	027C 1094h
MCAN13_CFG	027D 1094h
MCAN14_CFG	0268 1094h
MCAN15_CFG	0269 1094h
MCAN16_CFG	026A 1094h
MCAN17_CFG	026B 1094h

Figure 12-2784 MCAN_HPMS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
FLST	FIDX
R-0h	R-0h

7	6	5	4	3	2	1	0
MSI		BIDX
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-5303 MCAN_HPMS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	FLST	R	0h	Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List
14-8	FIDX	R	0h	Filter Index Index of matching filter element. Range is 0 to MCAN_SIDFC[23-16] LSS - 1 respectively MCAN_XIDFC[22-16] LSE - 1.
7-6	MSI	R	0h	Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1
5-0	BIDX	R	0h	Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the MCAN_HPMS[7-6] MSI = 1h.

4.5.2.24 MCAN_NDAT1 Register (Offset = 98h) [reset = 0h]

MCAN_NDAT1 is shown in Figure 12-2785 and described in Table 12-5305.

Return to Summary Table.

New Data 1
NewDat flags of dedicated Rx buffers 0-31.

The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU clears them. Aflag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no effect. A hard reset will clear the register.

Table 12-5304 MCAN_NDAT1 Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 8098h
MCU_MCAN1_CFG	4056 8098h
MCAN0_CFG	0270 1098h
MCAN1_CFG	0271 1098h
MCAN2_CFG	0272 1098h
MCAN3_CFG	0273 1098h
MCAN4_CFG	0274 1098h
MCAN5_CFG	0275 1098h
MCAN6_CFG	0276 1098h
MCAN7_CFG	0277 1098h
MCAN8_CFG	0278 1098h
MCAN9_CFG	0279 1098h
MCAN10_CFG	027A 1098h
MCAN11_CFG	027B 1098h
MCAN12_CFG	027C 1098h
MCAN13_CFG	027D 1098h
MCAN14_CFG	0268 1098h
MCAN15_CFG	0269 1098h
MCAN16_CFG	026A 1098h
MCAN17_CFG	026B 1098h

Figure 12-2785 MCAN_NDAT1 Register

31	30	29	28	27	26	25	24
ND31	ND30	ND29	ND28	ND27	ND26	ND25	ND24
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

23	22	21	20	19	18	17	16
ND23	ND22	ND21	ND20	ND19	ND18	ND17	ND16
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

15	14	13	12	11	10	9	8
ND15	ND14	ND13	ND12	ND11	ND10	ND9	ND8
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

7	6	5	4	3	2	1	0
ND7	ND6	ND5	ND4	ND3	ND2	ND1	ND0
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

LEGEND: RW1TC = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-5305 MCAN_NDAT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	ND31	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
30	ND30	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
29	ND29	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
28	ND28	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
27	ND27	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
26	ND26	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
25	ND25	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
24	ND24	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
23	ND23	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
22	ND22	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
21	ND21	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
20	ND20	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
19	ND19	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
18	ND18	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
17	ND17	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
16	ND16	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
15	ND15	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
14	ND14	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
13	ND13	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
12	ND12	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
11	ND11	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
10	ND10	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
9	ND9	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
8	ND8	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
7	ND7	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
6	ND6	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
5	ND5	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
4	ND4	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
3	ND3	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
2	ND2	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
1	ND1	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
0	ND0	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message

4.5.2.25 MCAN_NDAT2 Register (Offset = 9Ch) [reset = 0h]

MCAN_NDAT2 is shown in Figure 12-2786 and described in Table 12-5307.

Return to Summary Table.

New Data 2
NewDat flags of dedicated Rx buffers 32-63.

The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no effect. A hard reset will clear the register.

Table 12-5306 MCAN_NDAT2 Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 809Ch
MCU_MCAN1_CFG	4056 809Ch
MCAN0_CFG	0270 109Ch
MCAN1_CFG	0271 109Ch
MCAN2_CFG	0272 109Ch
MCAN3_CFG	0273 109Ch
MCAN4_CFG	0274 109Ch
MCAN5_CFG	0275 109Ch
MCAN6_CFG	0276 109Ch
MCAN7_CFG	0277 109Ch
MCAN8_CFG	0278 109Ch
MCAN9_CFG	0279 109Ch
MCAN10_CFG	027A 109Ch
MCAN11_CFG	027B 109Ch
MCAN12_CFG	027C 109Ch
MCAN13_CFG	027D 109Ch
MCAN14_CFG	0268 109Ch
MCAN15_CFG	0269 109Ch
MCAN16_CFG	026A 109Ch
MCAN17_CFG	026B 109Ch

Figure 12-2786 MCAN_NDAT2 Register

31	30	29	28	27	26	25	24
ND63	ND62	ND61	ND60	ND59	ND58	ND57	ND56
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

23	22	21	20	19	18	17	16
ND55	ND54	ND53	ND52	ND51	ND50	ND49	ND48
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

15	14	13	12	11	10	9	8
ND47	ND46	ND45	ND44	ND43	ND42	ND41	ND40
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

7	6	5	4	3	2	1	0
ND39	ND38	ND37	ND36	ND35	ND34	ND33	ND32
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

LEGEND: RW1TC = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-5307 MCAN_NDAT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	ND63	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
30	ND62	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
29	ND61	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
28	ND60	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
27	ND59	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
26	ND58	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
25	ND57	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
24	ND56	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
23	ND55	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
22	ND54	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
21	ND53	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
20	ND52	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
19	ND51	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
18	ND50	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
17	ND49	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
16	ND48	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
15	ND47	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
14	ND46	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
13	ND45	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
12	ND44	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
11	ND43	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
10	ND42	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
9	ND41	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
8	ND40	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
7	ND39	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
6	ND38	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
5	ND37	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
4	ND36	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
3	ND35	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
2	ND34	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
1	ND33	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message
0	ND32	RW1TC	0h	New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message

4.5.2.26 MCAN_RXF0C Register (Offset = A0h) [reset = 0h]

MCAN_RXF0C is shown in Figure 12-2787 and described in Table 12-5309.

Return to Summary Table.

Rx FIFO 0 Configuration
FIFO 0 operation mode, watermark, size and start address.

Table 12-5308 MCAN_RXF0C Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80A0h
MCU_MCAN1_CFG	4056 80A0h
MCAN0_CFG	0270 10A0h
MCAN1_CFG	0271 10A0h
MCAN2_CFG	0272 10A0h
MCAN3_CFG	0273 10A0h
MCAN4_CFG	0274 10A0h
MCAN5_CFG	0275 10A0h
MCAN6_CFG	0276 10A0h
MCAN7_CFG	0277 10A0h
MCAN8_CFG	0278 10A0h
MCAN9_CFG	0279 10A0h
MCAN10_CFG	027A 10A0h
MCAN11_CFG	027B 10A0h
MCAN12_CFG	027C 10A0h
MCAN13_CFG	027D 10A0h
MCAN14_CFG	0268 10A0h
MCAN15_CFG	0269 10A0h
MCAN16_CFG	026A 10A0h
MCAN17_CFG	026B 10A0h

Figure 12-2787 MCAN_RXF0C Register

31	30	29	28	27	26	25	24
F0OM	F0WM
R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
RESERVED	F0S
R-0h	R/W-0h

15	14	13	12	11	10	9	8
F0SA
R/W-0h

7	6	5	4	3	2	1	0
F0SA						RESERVED
R/W-0h						R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5309 MCAN_RXF0C Register Field Descriptions

Bit	Field	Type	Reset	Description
31	F0OM	R/W	0h	FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Section 12.4.4.4.7.2, Rx FIFOs). 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode
30-24	F0WM	R/W	0h	Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt (MCAN_IR[1] RF0W) > 40h (64) = Watermark interrupt disabled
23	RESERVED	R	0h	Reserved
22-16	F0S	R/W	0h	Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements > 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to MCAN_RXF0C[22-16] F0S - 1.
15-2	F0SA	R/W	0h	Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Section 12.4.4.4.10.1, Message RAM Configuration).
1-0	RESERVED	R	0h	Reserved

4.5.2.27 MCAN_RXF0S Register (Offset = A4h) [reset = 0h]

MCAN_RXF0S is shown in Figure 12-2788 and described in Table 12-5311.

Return to Summary Table.

Rx FIFO 0 Status
FIFO 0 message lost/full indication, put index, get index and fill level.

Table 12-5310 MCAN_RXF0S Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80A4h
MCU_MCAN1_CFG	4056 80A4h
MCAN0_CFG	0270 10A4h
MCAN1_CFG	0271 10A4h
MCAN2_CFG	0272 10A4h
MCAN3_CFG	0273 10A4h
MCAN4_CFG	0274 10A4h
MCAN5_CFG	0275 10A4h
MCAN6_CFG	0276 10A4h
MCAN7_CFG	0277 10A4h
MCAN8_CFG	0278 10A4h
MCAN9_CFG	0279 10A4h
MCAN10_CFG	027A 10A4h
MCAN11_CFG	027B 10A4h
MCAN12_CFG	027C 10A4h
MCAN13_CFG	027D 10A4h
MCAN14_CFG	0268 10A4h
MCAN15_CFG	0269 10A4h
MCAN16_CFG	026A 10A4h
MCAN17_CFG	026B 10A4h

Figure 12-2788 MCAN_RXF0S Register

31	30	29	28	27	26	25	24
RESERVED						RF0L	F0F
R-0h						R-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED		F0PI
R-0h		R-0h

15	14	13	12	11	10	9	8
RESERVED		F0GI
R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED	F0FL
R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-5311 MCAN_RXF0S Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	RF0L	R	0h	Rx FIFO 0 Message Lost This bit is a copy of interrupt flag MCAN_IR[3] RF0L. When the MCAN_IR[3] RF0L flag is reset, this bit is also reset. 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Note: Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will not set this flag.
24	F0F	R	0h	Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full
23-22	RESERVED	R	0h	Reserved
21-16	F0PI	R	0h	Rx FIFO 0 Put Index Rx FIFO 0 write index pointer, range 0 to 63.
15-14	RESERVED	R	0h	Reserved
13-8	F0GI	R	0h	Rx FIFO 0 Get Index Rx FIFO 0 read index pointer, range 0 to 63.
7	RESERVED	R	0h	Reserved
6-0	F0FL	R	0h	Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0, range 0 to 64.

4.5.2.28 MCAN_RXF0A Register (Offset = A8h) [reset = 0h]

MCAN_RXF0A is shown in Figure 12-2789 and described in Table 12-5313.

Return to Summary Table.

Rx FIFO 0 Acknowledge
FIFO 0 acknowledge last index of read buffers, updates get index and fill level.

Table 12-5312 MCAN_RXF0A Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80A8h
MCU_MCAN1_CFG	4056 80A8h
MCAN0_CFG	0270 10A8h
MCAN1_CFG	0271 10A8h
MCAN2_CFG	0272 10A8h
MCAN3_CFG	0273 10A8h
MCAN4_CFG	0274 10A8h
MCAN5_CFG	0275 10A8h
MCAN6_CFG	0276 10A8h
MCAN7_CFG	0277 10A8h
MCAN8_CFG	0278 10A8h
MCAN9_CFG	0279 10A8h
MCAN10_CFG	027A 10A8h
MCAN11_CFG	027B 10A8h
MCAN12_CFG	027C 10A8h
MCAN13_CFG	027D 10A8h
MCAN14_CFG	0268 10A8h
MCAN15_CFG	0269 10A8h
MCAN16_CFG	026A 10A8h
MCAN17_CFG	026B 10A8h

Figure 12-2789 MCAN_RXF0A Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																										F0AI
R-0h																										R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5313 MCAN_RXF0A Register Field Descriptions

Bit

Field

Type

Reset

Description

31-6

RESERVED

R

0h

Reserved

5-0

F0AI

R/W

0h

Rx FIFO 0 Acknowledge Index

After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the MCAN_RXF0A[5-0] F0AI field. This will set the Rx FIFO 0 Get Index MCAN_RXF0S[13-8] F0GI field to the MCAN_RXF0A[5-0] F0AI field + 1 and update the FIFO 0 Fill Level MCAN_RXF0S[6-0] F0FL field.

4.5.2.29 MCAN_RXBC Register (Offset = ACh) [reset = 0h]

MCAN_RXBC is shown in Figure 12-2790 and described in Table 12-5315.

Return to Summary Table.

Rx Buffer Configuration
Start address of Rx buffer section.

Table 12-5314 MCAN_RXBC Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80ACh
MCU_MCAN1_CFG	4056 80ACh
MCAN0_CFG	0270 10ACh
MCAN1_CFG	0271 10ACh
MCAN2_CFG	0272 10ACh
MCAN3_CFG	0273 10ACh
MCAN4_CFG	0274 10ACh
MCAN5_CFG	0275 10ACh
MCAN6_CFG	0276 10ACh
MCAN7_CFG	0277 10ACh
MCAN8_CFG	0278 10ACh
MCAN9_CFG	0279 10ACh
MCAN10_CFG	027A 10ACh
MCAN11_CFG	027B 10ACh
MCAN12_CFG	027C 10ACh
MCAN13_CFG	027D 10ACh
MCAN14_CFG	0268 10ACh
MCAN15_CFG	0269 10ACh
MCAN16_CFG	026A 10ACh
MCAN17_CFG	026B 10ACh

Figure 12-2790 MCAN_RXBC Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RBSA
R/W-0h

7	6	5	4	3	2	1	0
RBSA						RESERVED
R/W-0h						R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5315 MCAN_RXBC Register Field Descriptions

Bit

Field

Type

Reset

Description

31-16

RESERVED

R

0h

Reserved

15-2

RBSA

R/W

0h

Rx Buffer Start Address

Configures the start address of the Rx Buffers section in the Message RAM

(32-bit word address, see Figure 12-2745).

Also used to reference debug messages A, B, C.

Note: Debug feature is not supported.

1-0

RESERVED

R

0h

Reserved

4.5.2.30 MCAN_RXF1C Register (Offset = B0h) [reset = 0h]

MCAN_RXF1C is shown in Figure 12-2791 and described in Table 12-5317.

Return to Summary Table.

Rx FIFO 1 Configuration
FIFO 1 operation mode, watermark, size and start address.

Table 12-5316 MCAN_RXF1C Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80B0h
MCU_MCAN1_CFG	4056 80B0h
MCAN0_CFG	0270 10B0h
MCAN1_CFG	0271 10B0h
MCAN2_CFG	0272 10B0h
MCAN3_CFG	0273 10B0h
MCAN4_CFG	0274 10B0h
MCAN5_CFG	0275 10B0h
MCAN6_CFG	0276 10B0h
MCAN7_CFG	0277 10B0h
MCAN8_CFG	0278 10B0h
MCAN9_CFG	0279 10B0h
MCAN10_CFG	027A 10B0h
MCAN11_CFG	027B 10B0h
MCAN12_CFG	027C 10B0h
MCAN13_CFG	027D 10B0h
MCAN14_CFG	0268 10B0h
MCAN15_CFG	0269 10B0h
MCAN16_CFG	026A 10B0h
MCAN17_CFG	026B 10B0h

Figure 12-2791 MCAN_RXF1C Register

31	30	29	28	27	26	25	24
F1OM	F1WM
R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
RESERVED	F1S
R-0h	R/W-0h

15	14	13	12	11	10	9	8
F1SA
R/W-0h

7	6	5	4	3	2	1	0
F1SA						RESERVED
R/W-0h						R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5317 MCAN_RXF1C Register Field Descriptions

Bit	Field	Type	Reset	Description
31	F1OM	R/W	0h	FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Section 12.4.4.4.7.2, Rx FIFOs). 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode
30-24	F1WM	R/W	0h	Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt (MCAN_IR[5] RF1W) > 40h (64) = Watermark interrupt disabled
23	RESERVED	R	0h	Reserved
22-16	F1S	R/W	0h	Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements > 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to MCAN_RXF1C[22-16] F1S - 1.
15-2	F1SA	R/W	0h	Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Section 12.4.4.4.10.1, Message RAM Configuration).
1-0	RESERVED	R	0h	Reserved

4.5.2.31 MCAN_RXF1S Register (Offset = B4h) [reset = 0h]

MCAN_RXF1S is shown in Figure 12-2792 and described in Table 12-5319.

Return to Summary Table.

Rx FIFO 1 Status
FIFO 1 message lost/full indication, put index, get index and fill level.

Table 12-5318 MCAN_RXF1S Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80B4h
MCU_MCAN1_CFG	4056 80B4h
MCAN0_CFG	0270 10B4h
MCAN1_CFG	0271 10B4h
MCAN2_CFG	0272 10B4h
MCAN3_CFG	0273 10B4h
MCAN4_CFG	0274 10B4h
MCAN5_CFG	0275 10B4h
MCAN6_CFG	0276 10B4h
MCAN7_CFG	0277 10B4h
MCAN8_CFG	0278 10B4h
MCAN9_CFG	0279 10B4h
MCAN10_CFG	027A 10B4h
MCAN11_CFG	027B 10B4h
MCAN12_CFG	027C 10B4h
MCAN13_CFG	027D 10B4h
MCAN14_CFG	0268 10B4h
MCAN15_CFG	0269 10B4h
MCAN16_CFG	026A 10B4h
MCAN17_CFG	026B 10B4h

Figure 12-2792 MCAN_RXF1S Register

31	30	29	28	27	26	25	24
DMS		RESERVED				RF1L	F1F
R-0h		R-0h				R-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED		F1PI
R-0h		R-0h

15	14	13	12	11	10	9	8
RESERVED		F1GI
R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED	F1FL
R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-5319 MCAN_RXF1S Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	DMS	R	0h	Debug Message Status 0h = Idle state, wait for reception of debug messages, DMA request is cleared 1h = Debug message A received 2h = Debug messages A, B received 3h = Debug messages A, B, C received, DMA request is set Note: Debug feature is not supported.
29-26	RESERVED	R	0h	Reserved
25	RF1L	R	0h	Rx FIFO 1 Message Lost This bit is a copy of interrupt flag MCAN_IR[7] RF1L. When the MCAN_IR[7] RF1L flag is reset, this bit is also reset. 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note: Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will not set this flag.
24	F1F	R	0h	Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full
23-22	RESERVED	R	0h	Reserved
21-16	F1PI	R	0h	Rx FIFO 1 Put Index Rx FIFO 1 write index pointer, range 0 to 63.
15-14	RESERVED	R	0h	Reserved
13-8	F1GI	R	0h	Rx FIFO 1 Get Index Rx FIFO 1 read index pointer, range 0 to 63.
7	RESERVED	R	0h	Reserved
6-0	F1FL	R	0h	Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1, range 0 to 64.

4.5.2.32 MCAN_RXF1A Register (Offset = B8h) [reset = 0h]

MCAN_RXF1A is shown in Figure 12-2793 and described in Table 12-5321.

Return to Summary Table.

Rx FIFO 1 Acknowledge
FIFO 1 acknowledge last index of read buffers, updates get index and fill level.

Table 12-5320 MCAN_RXF1A Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80B8h
MCU_MCAN1_CFG	4056 80B8h
MCAN0_CFG	0270 10B8h
MCAN1_CFG	0271 10B8h
MCAN2_CFG	0272 10B8h
MCAN3_CFG	0273 10B8h
MCAN4_CFG	0274 10B8h
MCAN5_CFG	0275 10B8h
MCAN6_CFG	0276 10B8h
MCAN7_CFG	0277 10B8h
MCAN8_CFG	0278 10B8h
MCAN9_CFG	0279 10B8h
MCAN10_CFG	027A 10B8h
MCAN11_CFG	027B 10B8h
MCAN12_CFG	027C 10B8h
MCAN13_CFG	027D 10B8h
MCAN14_CFG	0268 10B8h
MCAN15_CFG	0269 10B8h
MCAN16_CFG	026A 10B8h
MCAN17_CFG	026B 10B8h

Figure 12-2793 MCAN_RXF1A Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																										F1AI
R-0h																										R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5321 MCAN_RXF1A Register Field Descriptions

Bit

Field

Type

Reset

Description

31-6

RESERVED

R

0h

Reserved

5-0

F1AI

R/W

0h

Rx FIFO 1 Acknowledge Index

After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the

buffer index of the last element read from Rx FIFO 1 to the MCAN_RXF1A[5-0] F1AI field. This will set the Rx FIFO 1 Get Index MCAN_RXF1S[13-8] F1GI field to the MCAN_RXF1A[5-0] F1AI field + 1 and update the FIFO 1 Fill Level MCAN_RXF1S[6-0] F1FL field.

4.5.2.33 MCAN_RXESC Register (Offset = BCh) [reset = 0h]

MCAN_RXESC is shown in Figure 12-2794 and described in Table 12-5323.

Return to Summary Table.

Rx Buffer/FIFO Element Size Configuration
Configure data field size for storage of accepted frames.

Table 12-5322 MCAN_RXESC Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80BCh
MCU_MCAN1_CFG	4056 80BCh
MCAN0_CFG	0270 10BCh
MCAN1_CFG	0271 10BCh
MCAN2_CFG	0272 10BCh
MCAN3_CFG	0273 10BCh
MCAN4_CFG	0274 10BCh
MCAN5_CFG	0275 10BCh
MCAN6_CFG	0276 10BCh
MCAN7_CFG	0277 10BCh
MCAN8_CFG	0278 10BCh
MCAN9_CFG	0279 10BCh
MCAN10_CFG	027A 10BCh
MCAN11_CFG	027B 10BCh
MCAN12_CFG	027C 10BCh
MCAN13_CFG	027D 10BCh
MCAN14_CFG	0268 10BCh
MCAN15_CFG	0269 10BCh
MCAN16_CFG	026A 10BCh
MCAN17_CFG	026B 10BCh

Figure 12-2794 MCAN_RXESC Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED					RBDS
R-0h					R/W-0h

7	6	5	4	3	2	1	0
RESERVED	F1DS			RESERVED	F0DS
R-0h	R/W-0h			R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5323 MCAN_RXESC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-11	RESERVED	R	0h	Reserved
10-8	RBDS	R/W	0h	Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field
7	RESERVED	R	0h	Reserved
6-4	F1DS	R/W	0h	Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field
3	RESERVED	R	0h	Reserved
2-0	F0DS	R/W	0h	Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by the MCAN_RXESC register are stored to the Rx Buffer respectively Rx FIFO element. The rest of the frame's data field is ignored.

4.5.2.34 MCAN_TXBC Register (Offset = C0h) [reset = 0h]

MCAN_TXBC is shown in Figure 12-2795 and described in Table 12-5325.

Return to Summary Table.

Tx Buffer Configuration
Configure Tx FIFO/Queue mode, Tx FIFO/Queue size, number of dedicated Tx buffers, Tx buffer start address.

Table 12-5324 MCAN_TXBC Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80C0h
MCU_MCAN1_CFG	4056 80C0h
MCAN0_CFG	0270 10C0h
MCAN1_CFG	0271 10C0h
MCAN2_CFG	0272 10C0h
MCAN3_CFG	0273 10C0h
MCAN4_CFG	0274 10C0h
MCAN5_CFG	0275 10C0h
MCAN6_CFG	0276 10C0h
MCAN7_CFG	0277 10C0h
MCAN8_CFG	0278 10C0h
MCAN9_CFG	0279 10C0h
MCAN10_CFG	027A 10C0h
MCAN11_CFG	027B 10C0h
MCAN12_CFG	027C 10C0h
MCAN13_CFG	027D 10C0h
MCAN14_CFG	0268 10C0h
MCAN15_CFG	0269 10C0h
MCAN16_CFG	026A 10C0h
MCAN17_CFG	026B 10C0h

Figure 12-2795 MCAN_TXBC Register

31	30	29	28	27	26	25	24
RESERVED	TFQM	TFQS
R-0h	R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
RESERVED		NDTB
R-0h		R/W-0h

15	14	13	12	11	10	9	8
TBSA
R/W-0h

7	6	5	4	3	2	1	0
TBSA						RESERVED
R/W-0h						R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5325 MCAN_TXBC Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	TFQM	R/W	0h	Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation
29-24	TFQS	R/W	0h	Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue > 20h (32) = Values greater than 32 are interpreted as 32
23-22	RESERVED	R	0h	Reserved
21-16	NDTB	R/W	0h	Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers > 20h (32) = Values greater than 32 are interpreted as 32
15-2	TBSA	R/W	0h	Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address, see Section 12.4.4.4.10.1, Message RAM Configuration). Note: Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers.
1-0	RESERVED	R	0h	Reserved

4.5.2.35 MCAN_TXFQS Register (Offset = C4h) [reset = 0h]

MCAN_TXFQS is shown in Figure 12-2796 and described in Table 12-5327.

Return to Summary Table.

Tx FIFO/Queue Status
Tx FIFO/Queue full indication and put index, Tx FIFO get index and fill level.

The Tx FIFO/Queue status is related to the pending Tx requests listed in the MCAN_TXBRP register. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (the MCAN_TXBRP register not yet updated).

Table 12-5326 MCAN_TXFQS Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80C4h
MCU_MCAN1_CFG	4056 80C4h
MCAN0_CFG	0270 10C4h
MCAN1_CFG	0271 10C4h
MCAN2_CFG	0272 10C4h
MCAN3_CFG	0273 10C4h
MCAN4_CFG	0274 10C4h
MCAN5_CFG	0275 10C4h
MCAN6_CFG	0276 10C4h
MCAN7_CFG	0277 10C4h
MCAN8_CFG	0278 10C4h
MCAN9_CFG	0279 10C4h
MCAN10_CFG	027A 10C4h
MCAN11_CFG	027B 10C4h
MCAN12_CFG	027C 10C4h
MCAN13_CFG	027D 10C4h
MCAN14_CFG	0268 10C4h
MCAN15_CFG	0269 10C4h
MCAN16_CFG	026A 10C4h
MCAN17_CFG	026B 10C4h

Figure 12-2796 MCAN_TXFQS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED		TFQF	TFQPI
R-0h		R-0h	R-0h

15	14	13	12	11	10	9	8
RESERVED			TFGI
R-0h			R-0h

7	6	5	4	3	2	1	0
RESERVED		TFFL
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-5327 MCAN_TXFQS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-22	RESERVED	R	0h	Reserved
21	TFQF	R	0h	Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full
20-16	TFQPI	R	0h	Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer, range 0 to 31.
15-13	RESERVED	R	0h	Reserved
12-8	TFGI	R	0h	Tx FIFO Get Index Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (MCAN_TXBC[30] TFQM = 1h).
7-6	RESERVED	R	0h	Reserved
5-0	TFFL	R	0h	Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the MCAN_TXFQS[12-8] TFGI field, range 0 to 32. Read as zero when Tx Queue operation is configured (MCAN_TXBC[30] TFQM = 1h). Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.

4.5.2.36 MCAN_TXESC Register (Offset = C8h) [reset = 0h]

MCAN_TXESC is shown in Figure 12-2797 and described in Table 12-5329.

Return to Summary Table.

Tx Buffer Element Size Configuration
Configure data field size for frame transmission.

Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only.

Table 12-5328 MCAN_TXESC Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80C8h
MCU_MCAN1_CFG	4056 80C8h
MCAN0_CFG	0270 10C8h
MCAN1_CFG	0271 10C8h
MCAN2_CFG	0272 10C8h
MCAN3_CFG	0273 10C8h
MCAN4_CFG	0274 10C8h
MCAN5_CFG	0275 10C8h
MCAN6_CFG	0276 10C8h
MCAN7_CFG	0277 10C8h
MCAN8_CFG	0278 10C8h
MCAN9_CFG	0279 10C8h
MCAN10_CFG	027A 10C8h
MCAN11_CFG	027B 10C8h
MCAN12_CFG	027C 10C8h
MCAN13_CFG	027D 10C8h
MCAN14_CFG	0268 10C8h
MCAN15_CFG	0269 10C8h
MCAN16_CFG	026A 10C8h
MCAN17_CFG	026B 10C8h

Figure 12-2797 MCAN_TXESC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													TBDS
R-0h													R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5329 MCAN_TXESC Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

TBDS

R/W

0h

Tx Buffer Data Field Size

0h = 8 byte data field

1h = 12 byte data field

2h = 16 byte data field

3h = 20 byte data field

4h = 24 byte data field

5h = 32 byte data field

6h = 48 byte data field

7h = 64 byte data field

Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size MCAN_TXESC[2-0] TBDS, the bytes not defined by the Tx Buffer are transmitted as CCh (padding bytes).

4.5.2.37 MCAN_TXBRP Register (Offset = CCh) [reset = 0h]

MCAN_TXBRP is shown in Figure 12-2798 and described in Table 12-5331.

Return to Summary Table.

Tx Buffer Request Pending
Tx buffers with pending transmission request.

Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the MCAN_TXBAR register. The bits are reset after a requested transmission has completed or has been cancelled via the MCAN_TXBCR register.

The MCAN_TXBRP bits are set only for those Tx Buffers configured via the MCAN_TXBC register. After a MCAN_TXBRP bit has been set, a Tx scan (see Section 12.4.4.4.8, Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID).

A cancellation request resets the corresponding transmission request pending bit of register the MCAN_TXBRP register. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding MCAN_TXBRP bit has been reset.

After a cancellation has been requested, a finished cancellation is signalled via the MCAN_TXBCF flag

• after successful transmission together with the corresponding MCAN_TXBTO bit

• when the transmission has not yet been started at the point of cancellation

• when the transmission has been aborted due to lost arbitration

• when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding MCAN_TXBCF bit is set for all unsuccessful transmissions.

Note: The MCAN_TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding MCAN_TXBRP bit is reset.

Table 12-5330 MCAN_TXBRP Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80CCh
MCU_MCAN1_CFG	4056 80CCh
MCAN0_CFG	0270 10CCh
MCAN1_CFG	0271 10CCh
MCAN2_CFG	0272 10CCh
MCAN3_CFG	0273 10CCh
MCAN4_CFG	0274 10CCh
MCAN5_CFG	0275 10CCh
MCAN6_CFG	0276 10CCh
MCAN7_CFG	0277 10CCh
MCAN8_CFG	0278 10CCh
MCAN9_CFG	0279 10CCh
MCAN10_CFG	027A 10CCh
MCAN11_CFG	027B 10CCh
MCAN12_CFG	027C 10CCh
MCAN13_CFG	027D 10CCh
MCAN14_CFG	0268 10CCh
MCAN15_CFG	0269 10CCh
MCAN16_CFG	026A 10CCh
MCAN17_CFG	026B 10CCh

Figure 12-2798 MCAN_TXBRP Register

31	30	29	28	27	26	25	24
TRP31	TRP30	TRP29	TRP28	TRP27	TRP26	TRP25	TRP24
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

23	22	21	20	19	18	17	16
TRP23	TRP22	TRP21	TRP20	TRP19	TRP18	TRP17	TRP16
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

15	14	13	12	11	10	9	8
TRP15	TRP14	TRP13	TRP12	TRP11	TRP10	TRP9	TRP8
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
TRP7	TRP6	TRP5	TRP4	TRP3	TRP2	TRP1	TRP0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-5331 MCAN_TXBRP Register Field Descriptions

Bit	Field	Type	Reset	Description
31	TRP31	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
30	TRP30	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
29	TRP29	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
28	TRP28	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
27	TRP27	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
26	TRP26	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
25	TRP25	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
24	TRP24	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
23	TRP23	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
22	TRP22	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
21	TRP21	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
20	TRP20	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
19	TRP19	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
18	TRP18	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
17	TRP17	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
16	TRP16	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
15	TRP15	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
14	TRP14	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
13	TRP13	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
12	TRP12	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
11	TRP11	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
10	TRP10	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
9	TRP9	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
8	TRP8	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
7	TRP7	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
6	TRP6	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
5	TRP5	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
4	TRP4	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
3	TRP3	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
2	TRP2	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
1	TRP1	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending
0	TRP0	R	0h	Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending

4.5.2.38 MCAN_TXBAR Register (Offset = D0h) [reset = 0h]

MCAN_TXBAR is shown in Figure 12-2799 and described in Table 12-5333.

Return to Summary Table.

Tx Buffer Add Request
Add transmission requests.

Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple Tx Buffers with one write to the MCAN_TXBAR register. The MCAN_TXBAR bits are set only for those Tx Buffers configured via the MCAN_TXBC register. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed.

Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding MCAN_TXBRP bit already set), this add request is ignored.

Table 12-5332 MCAN_TXBAR Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80D0h
MCU_MCAN1_CFG	4056 80D0h
MCAN0_CFG	0270 10D0h
MCAN1_CFG	0271 10D0h
MCAN2_CFG	0272 10D0h
MCAN3_CFG	0273 10D0h
MCAN4_CFG	0274 10D0h
MCAN5_CFG	0275 10D0h
MCAN6_CFG	0276 10D0h
MCAN7_CFG	0277 10D0h
MCAN8_CFG	0278 10D0h
MCAN9_CFG	0279 10D0h
MCAN10_CFG	027A 10D0h
MCAN11_CFG	027B 10D0h
MCAN12_CFG	027C 10D0h
MCAN13_CFG	027D 10D0h
MCAN14_CFG	0268 10D0h
MCAN15_CFG	0269 10D0h
MCAN16_CFG	026A 10D0h
MCAN17_CFG	026B 10D0h

Figure 12-2799 MCAN_TXBAR Register

31	30	29	28	27	26	25	24
AR31	AR30	AR29	AR28	AR27	AR26	AR25	AR24
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

23	22	21	20	19	18	17	16
AR23	AR22	AR21	AR20	AR19	AR18	AR17	AR16
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

15	14	13	12	11	10	9	8
AR15	AR14	AR13	AR12	AR11	AR10	AR9	AR8
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

7	6	5	4	3	2	1	0
AR7	AR6	AR5	AR4	AR3	AR2	AR1	AR0
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

LEGEND: RW1TC = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-5333 MCAN_TXBAR Register Field Descriptions

Bit	Field	Type	Reset	Description
31	AR31	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
30	AR30	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
29	AR29	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
28	AR28	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
27	AR27	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
26	AR26	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
25	AR25	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
24	AR24	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
23	AR23	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
22	AR22	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
21	AR21	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
20	AR20	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
19	AR19	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
18	AR18	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
17	AR17	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
16	AR16	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
15	AR15	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
14	AR14	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
13	AR13	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
12	AR12	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
11	AR11	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
10	AR10	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
9	AR9	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
8	AR8	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
7	AR7	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
6	AR6	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
5	AR5	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
4	AR4	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
3	AR3	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
2	AR2	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
1	AR1	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added
0	AR0	RW1TC	0h	Add Request 0h = No transmission request added 1h = Transmission requested added

4.5.2.39 MCAN_TXBCR Register (Offset = D4h) [reset = 0h]

MCAN_TXBCR is shown in Figure 12-2800 and described in Table 12-5335.

Return to Summary Table.

Tx Buffer Cancellation Request
Request cancellation of pending transmissions.

Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the Host CPU to set cancellation requests for multiple Tx Buffers with one write to the MCAN_TXBCR register. The MCAN_TXBCR bits are set only for those Tx Buffers configured via the MCAN_TXBC register. The bits remain set until the corresponding bit of the MCAN_TXBRP register is reset.

Table 12-5334 MCAN_TXBCR Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80D4h
MCU_MCAN1_CFG	4056 80D4h
MCAN0_CFG	0270 10D4h
MCAN1_CFG	0271 10D4h
MCAN2_CFG	0272 10D4h
MCAN3_CFG	0273 10D4h
MCAN4_CFG	0274 10D4h
MCAN5_CFG	0275 10D4h
MCAN6_CFG	0276 10D4h
MCAN7_CFG	0277 10D4h
MCAN8_CFG	0278 10D4h
MCAN9_CFG	0279 10D4h
MCAN10_CFG	027A 10D4h
MCAN11_CFG	027B 10D4h
MCAN12_CFG	027C 10D4h
MCAN13_CFG	027D 10D4h
MCAN14_CFG	0268 10D4h
MCAN15_CFG	0269 10D4h
MCAN16_CFG	026A 10D4h
MCAN17_CFG	026B 10D4h

Figure 12-2800 MCAN_TXBCR Register

31	30	29	28	27	26	25	24
CR31	CR30	CR29	CR28	CR27	CR26	CR25	CR24
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

23	22	21	20	19	18	17	16
CR23	CR22	CR21	CR20	CR19	CR18	CR17	CR16
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

15	14	13	12	11	10	9	8
CR15	CR14	CR13	CR12	CR11	CR10	CR9	CR8
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

7	6	5	4	3	2	1	0
CR7	CR6	CR5	CR4	CR3	CR2	CR1	CR0
RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h	RW1TC-0h

LEGEND: RW1TC = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-5335 MCAN_TXBCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CR31	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
30	CR30	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
29	CR29	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
28	CR28	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
27	CR27	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
26	CR26	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
25	CR25	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
24	CR24	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
23	CR23	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
22	CR22	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
21	CR21	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
20	CR20	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
19	CR19	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
18	CR18	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
17	CR17	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
16	CR16	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
15	CR15	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
14	CR14	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
13	CR13	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
12	CR12	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
11	CR11	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
10	CR10	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
9	CR9	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
8	CR8	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
7	CR7	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
6	CR6	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
5	CR5	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
4	CR4	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
3	CR3	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
2	CR2	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
1	CR1	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending
0	CR0	RW1TC	0h	Cancellation Request 0h = No cancellation pending 1h = Cancellation pending

4.5.2.40 MCAN_TXBTO Register (Offset = D8h) [reset = 0h]

MCAN_TXBTO is shown in Figure 12-2801 and described in Table 12-5337.

Return to Summary Table.

Tx Buffer Transmission Occurred
Signals successful transmissions, set when corresponding MCAN_TXBRP flag is cleared.

Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding MCAN_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1h to the corresponding bit of register the MCAN_TXBAR register.

Table 12-5336 MCAN_TXBTO Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80D8h
MCU_MCAN1_CFG	4056 80D8h
MCAN0_CFG	0270 10D8h
MCAN1_CFG	0271 10D8h
MCAN2_CFG	0272 10D8h
MCAN3_CFG	0273 10D8h
MCAN4_CFG	0274 10D8h
MCAN5_CFG	0275 10D8h
MCAN6_CFG	0276 10D8h
MCAN7_CFG	0277 10D8h
MCAN8_CFG	0278 10D8h
MCAN9_CFG	0279 10D8h
MCAN10_CFG	027A 10D8h
MCAN11_CFG	027B 10D8h
MCAN12_CFG	027C 10D8h
MCAN13_CFG	027D 10D8h
MCAN14_CFG	0268 10D8h
MCAN15_CFG	0269 10D8h
MCAN16_CFG	026A 10D8h
MCAN17_CFG	026B 10D8h

Figure 12-2801 MCAN_TXBTO Register

31	30	29	28	27	26	25	24
TO31	TO30	TO29	TO28	TO27	TO26	TO25	TO24
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

23	22	21	20	19	18	17	16
TO23	TO22	TO21	TO20	TO19	TO18	TO17	TO16
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

15	14	13	12	11	10	9	8
TO15	TO14	TO13	TO12	TO11	TO10	TO9	TO8
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
TO7	TO6	TO5	TO4	TO3	TO2	TO1	TO0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-5337 MCAN_TXBTO Register Field Descriptions

Bit	Field	Type	Reset	Description
31	TO31	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
30	TO30	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
29	TO29	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
28	TO28	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
27	TO27	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
26	TO26	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
25	TO25	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
24	TO24	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
23	TO23	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
22	TO22	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
21	TO21	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
20	TO20	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
19	TO19	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
18	TO18	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
17	TO17	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
16	TO16	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
15	TO15	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
14	TO14	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
13	TO13	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
12	TO12	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
11	TO11	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
10	TO10	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
9	TO9	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
8	TO8	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
7	TO7	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
6	TO6	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
5	TO5	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
4	TO4	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
3	TO3	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
2	TO2	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
1	TO1	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred
0	TO0	R	0h	Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred

4.5.2.41 MCAN_TXBCF Register (Offset = DCh) [reset = 0h]

MCAN_TXBCF is shown in Figure 12-2802 and described in Table 12-5339.

Return to Summary Table.

Tx Buffer Cancellation Finished
Signals successful transmit cancellation, set when corresponding MCAN_TXBRP flag is cleared after cancellation request.

Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding MCAN_TXBRP bit is cleared after a cancellation was requested via the MCAN_TXBCR register. In case the corresponding MCAN_TXBRP bit was not set at the point of cancellation, MCAN_TXBCF[n] CF bit is set immediately. The bits are reset when a new transmission is requested by writing a 1h to the corresponding bit of the MCAN_TXBAR register.

Table 12-5338 MCAN_TXBCF Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80DCh
MCU_MCAN1_CFG	4056 80DCh
MCAN0_CFG	0270 10DCh
MCAN1_CFG	0271 10DCh
MCAN2_CFG	0272 10DCh
MCAN3_CFG	0273 10DCh
MCAN4_CFG	0274 10DCh
MCAN5_CFG	0275 10DCh
MCAN6_CFG	0276 10DCh
MCAN7_CFG	0277 10DCh
MCAN8_CFG	0278 10DCh
MCAN9_CFG	0279 10DCh
MCAN10_CFG	027A 10DCh
MCAN11_CFG	027B 10DCh
MCAN12_CFG	027C 10DCh
MCAN13_CFG	027D 10DCh
MCAN14_CFG	0268 10DCh
MCAN15_CFG	0269 10DCh
MCAN16_CFG	026A 10DCh
MCAN17_CFG	026B 10DCh

Figure 12-2802 MCAN_TXBCF Register

31	30	29	28	27	26	25	24
CF31	CF30	CF29	CF28	CF27	CF26	CF25	CF24
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

23	22	21	20	19	18	17	16
CF23	CF22	CF21	CF20	CF19	CF18	CF17	CF16
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

15	14	13	12	11	10	9	8
CF15	CF14	CF13	CF12	CF11	CF10	CF9	CF8
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
CF7	CF6	CF5	CF4	CF3	CF2	CF1	CF0
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-5339 MCAN_TXBCF Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CF31	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
30	CF30	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
29	CF29	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
28	CF28	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
27	CF27	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
26	CF26	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
25	CF25	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
24	CF24	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
23	CF23	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
22	CF22	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
21	CF21	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
20	CF20	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
19	CF19	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
18	CF18	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
17	CF17	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
16	CF16	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
15	CF15	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
14	CF14	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
13	CF13	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
12	CF12	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
11	CF11	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
10	CF10	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
9	CF9	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
8	CF8	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
7	CF7	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
6	CF6	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
5	CF5	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
4	CF4	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
3	CF3	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
2	CF2	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
1	CF1	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished
0	CF0	R	0h	Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished

4.5.2.42 MCAN_TXBTIE Register (Offset = E0h) [reset = 0h]

MCAN_TXBTIE is shown in Figure 12-2803 and described in Table 12-5341.

Return to Summary Table.

Tx Buffer Transmission Interrupt Enable
Enable transmit interrupts for selected Tx buffers.

Table 12-5340 MCAN_TXBTIE Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80E0h
MCU_MCAN1_CFG	4056 80E0h
MCAN0_CFG	0270 10E0h
MCAN1_CFG	0271 10E0h
MCAN2_CFG	0272 10E0h
MCAN3_CFG	0273 10E0h
MCAN4_CFG	0274 10E0h
MCAN5_CFG	0275 10E0h
MCAN6_CFG	0276 10E0h
MCAN7_CFG	0277 10E0h
MCAN8_CFG	0278 10E0h
MCAN9_CFG	0279 10E0h
MCAN10_CFG	027A 10E0h
MCAN11_CFG	027B 10E0h
MCAN12_CFG	027C 10E0h
MCAN13_CFG	027D 10E0h
MCAN14_CFG	0268 10E0h
MCAN15_CFG	0269 10E0h
MCAN16_CFG	026A 10E0h
MCAN17_CFG	026B 10E0h

Figure 12-2803 MCAN_TXBTIE Register

31	30	29	28	27	26	25	24
TIE31	TIE30	TIE29	TIE28	TIE27	TIE26	TIE25	TIE24
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
TIE23	TIE22	TIE21	TIE20	TIE19	TIE18	TIE17	TIE16
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
TIE15	TIE14	TIE13	TIE12	TIE11	TIE10	TIE9	TIE8
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
TIE7	TIE6	TIE5	TIE4	TIE3	TIE2	TIE1	TIE0
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-5341 MCAN_TXBTIE Register Field Descriptions

Bit	Field	Type	Reset	Description
31	TIE31	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
30	TIE30	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
29	TIE29	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
28	TIE28	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
27	TIE27	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
26	TIE26	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
25	TIE25	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
24	TIE24	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
23	TIE23	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
22	TIE22	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
21	TIE21	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
20	TIE20	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
19	TIE19	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
18	TIE18	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
17	TIE17	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
16	TIE16	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
15	TIE15	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
14	TIE14	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
13	TIE13	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
12	TIE12	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
11	TIE11	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
10	TIE10	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
9	TIE9	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
8	TIE8	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
7	TIE7	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
6	TIE6	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
5	TIE5	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
4	TIE4	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
3	TIE3	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
2	TIE2	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
1	TIE1	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable
0	TIE0	R/W	0h	Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable

4.5.2.43 MCAN_TXBCIE Register (Offset = E4h) [reset = 0h]

MCAN_TXBCIE is shown in Figure 12-2804 and described in Table 12-5343.

Return to Summary Table.

Tx Buffer Cancellation Finished Interrupt Enable
Enable cancellation finished interrupts for selected Tx buffers.

Table 12-5342 MCAN_TXBCIE Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80E4h
MCU_MCAN1_CFG	4056 80E4h
MCAN0_CFG	0270 10E4h
MCAN1_CFG	0271 10E4h
MCAN2_CFG	0272 10E4h
MCAN3_CFG	0273 10E4h
MCAN4_CFG	0274 10E4h
MCAN5_CFG	0275 10E4h
MCAN6_CFG	0276 10E4h
MCAN7_CFG	0277 10E4h
MCAN8_CFG	0278 10E4h
MCAN9_CFG	0279 10E4h
MCAN10_CFG	027A 10E4h
MCAN11_CFG	027B 10E4h
MCAN12_CFG	027C 10E4h
MCAN13_CFG	027D 10E4h
MCAN14_CFG	0268 10E4h
MCAN15_CFG	0269 10E4h
MCAN16_CFG	026A 10E4h
MCAN17_CFG	026B 10E4h

Figure 12-2804 MCAN_TXBCIE Register

31	30	29	28	27	26	25	24
CFIE31	CFIE30	CFIE29	CFIE28	CFIE27	CFIE26	CFIE25	CFIE24
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
CFIE23	CFIE22	CFIE21	CFIE20	CFIE19	CFIE18	CFIE17	CFIE16
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
CFIE15	CFIE14	CFIE13	CFIE12	CFIE11	CFIE10	CFIE9	CFIE8
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
CFIE7	CFIE6	CFIE5	CFIE4	CFIE3	CFIE2	CFIE1	CFIE0
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-5343 MCAN_TXBCIE Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CFIE31	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
30	CFIE30	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
29	CFIE29	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
28	CFIE28	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
27	CFIE27	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
26	CFIE26	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
25	CFIE25	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
24	CFIE24	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
23	CFIE23	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
22	CFIE22	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
21	CFIE21	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
20	CFIE20	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
19	CFIE19	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
18	CFIE18	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
17	CFIE17	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
16	CFIE16	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
15	CFIE15	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
14	CFIE14	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
13	CFIE13	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
12	CFIE12	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
11	CFIE11	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
10	CFIE10	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
9	CFIE9	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
8	CFIE8	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
7	CFIE7	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
6	CFIE6	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
5	CFIE5	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
4	CFIE4	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
3	CFIE3	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
2	CFIE2	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
1	CFIE1	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled
0	CFIE0	R/W	0h	Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled

4.5.2.44 MCAN_TXEFC Register (Offset = F0h) [reset = 0h]

MCAN_TXEFC is shown in Figure 12-2805 and described in Table 12-5345.

Return to Summary Table.

Tx Event FIFO Configuration
Tx event FIFO watermark, size and start address.

Table 12-5344 MCAN_TXEFC Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80F0h
MCU_MCAN1_CFG	4056 80F0h
MCAN0_CFG	0270 10F0h
MCAN1_CFG	0271 10F0h
MCAN2_CFG	0272 10F0h
MCAN3_CFG	0273 10F0h
MCAN4_CFG	0274 10F0h
MCAN5_CFG	0275 10F0h
MCAN6_CFG	0276 10F0h
MCAN7_CFG	0277 10F0h
MCAN8_CFG	0278 10F0h
MCAN9_CFG	0279 10F0h
MCAN10_CFG	027A 10F0h
MCAN11_CFG	027B 10F0h
MCAN12_CFG	027C 10F0h
MCAN13_CFG	027D 10F0h
MCAN14_CFG	0268 10F0h
MCAN15_CFG	0269 10F0h
MCAN16_CFG	026A 10F0h
MCAN17_CFG	026B 10F0h

Figure 12-2805 MCAN_TXEFC Register

31	30	29	28	27	26	25	24
RESERVED		EFWM
R-0h		R/W-0h

23	22	21	20	19	18	17	16
RESERVED		EFS
R-0h		R/W-0h

15	14	13	12	11	10	9	8
EFSA
R/W-0h

7	6	5	4	3	2	1	0
EFSA						RESERVED
R/W-0h						R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5345 MCAN_TXEFC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	0h	Reserved
29-24	EFWM	R/W	0h	Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt (MCAN_IR[13] TEFW) > 20h (32) = Watermark interrupt disabled
23-22	RESERVED	R	0h	Reserved
21-16	EFS	R/W	0h	Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements > 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to MCAN_TXEFC[21-16] EFS field - 1.
15-2	EFSA	R/W	0h	Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address, see Section 12.4.4.4.10.1, Message RAM Configuration).
1-0	RESERVED	R	0h	Reserved

4.5.2.45 MCAN_TXEFS Register (Offset = F4h) [reset = 0h]

MCAN_TXEFS is shown in Figure 12-2806 and described in Table 12-5347.

Return to Summary Table.

Tx Event FIFO Status
Tx event FIFO element lost/full indication, put index, get index, and fill level.

Table 12-5346 MCAN_TXEFS Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80F4h
MCU_MCAN1_CFG	4056 80F4h
MCAN0_CFG	0270 10F4h
MCAN1_CFG	0271 10F4h
MCAN2_CFG	0272 10F4h
MCAN3_CFG	0273 10F4h
MCAN4_CFG	0274 10F4h
MCAN5_CFG	0275 10F4h
MCAN6_CFG	0276 10F4h
MCAN7_CFG	0277 10F4h
MCAN8_CFG	0278 10F4h
MCAN9_CFG	0279 10F4h
MCAN10_CFG	027A 10F4h
MCAN11_CFG	027B 10F4h
MCAN12_CFG	027C 10F4h
MCAN13_CFG	027D 10F4h
MCAN14_CFG	0268 10F4h
MCAN15_CFG	0269 10F4h
MCAN16_CFG	026A 10F4h
MCAN17_CFG	026B 10F4h

Figure 12-2806 MCAN_TXEFS Register

31	30	29	28	27	26	25	24
RESERVED						TEFL	EFF
R-0h						R-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED			EFPI
R-0h			R-0h

15	14	13	12	11	10	9	8
RESERVED			EFGI
R-0h			R-0h

7	6	5	4	3	2	1	0
RESERVED		EFFL
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-5347 MCAN_TXEFS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	TEFL	R	0h	This bit is a copy of interrupt flag MCAN_IR[15] TEFL. When the MCAN_IR[15] TEFL flag is reset, this bit is also reset. 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.
24	EFF	R	0h	Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full
23-21	RESERVED	R	0h	Reserved
20-16	EFPI	R	0h	Event FIFO Put Index Tx Event FIFO write index pointer, range 0 to 31.
15-13	RESERVED	R	0h	Reserved
12-8	EFGI	R	0h	Event FIFO Get Index Tx Event FIFO read index pointer, range 0 to 31.
7-6	RESERVED	R	0h	Reserved
5-0	EFFL	R	0h	Event FIFO Fill Level Number of elements stored in Tx Event FIFO, range 0 to 32.

4.5.2.46 MCAN_TXEFA Register (Offset = F8h) [reset = 0h]

MCAN_TXEFA is shown in Figure 12-2807 and described in Table 12-5349.

Return to Summary Table.

Tx Event FIFO Acknowledge
Tx event FIFO acknowledge last index of read elements, updates get index and fill level.

Table 12-5348 MCAN_TXEFA Instances

Instance	Physical Address
MCU_MCAN0_CFG	4052 80F8h
MCU_MCAN1_CFG	4056 80F8h
MCAN0_CFG	0270 10F8h
MCAN1_CFG	0271 10F8h
MCAN2_CFG	0272 10F8h
MCAN3_CFG	0273 10F8h
MCAN4_CFG	0274 10F8h
MCAN5_CFG	0275 10F8h
MCAN6_CFG	0276 10F8h
MCAN7_CFG	0277 10F8h
MCAN8_CFG	0278 10F8h
MCAN9_CFG	0279 10F8h
MCAN10_CFG	027A 10F8h
MCAN11_CFG	027B 10F8h
MCAN12_CFG	027C 10F8h
MCAN13_CFG	027D 10F8h
MCAN14_CFG	0268 10F8h
MCAN15_CFG	0269 10F8h
MCAN16_CFG	026A 10F8h
MCAN17_CFG	026B 10F8h

Figure 12-2807 MCAN_TXEFA Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																											EFAI
R-0h																											R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-5349 MCAN_TXEFA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4-0	EFAI	R/W	0h	After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the MCAN_TXEFA[4-0] EFAI field. This will set the Tx Event FIFO Get Index MCAN_TXEFS[12-8] EFGI field to the MCAN_TXEFA[4-0] EFAI field + 1 and update the Event FIFO Fill Level MCAN_TXEFS[5-0] EFFL field.

12.4.4.5.2 MCAN Core Registers

4.5.2.1 MCAN_CREL Register (Offset = 0h) [reset = 32380608h]

4.5.2.2 MCAN_ENDN Register (Offset = 4h) [reset = 8765 4321h]

4.5.2.3 MCAN_DBTP Register (Offset = Ch) [reset = A33h]

4.5.2.4 MCAN_TEST Register (Offset = 10h) [reset = 0h]

4.5.2.5 MCAN_RWD Register (Offset = 14h) [reset = 0h]

4.5.2.6 MCAN_CCCR Register (Offset = 18h) [reset = 1h]

4.5.2.7 MCAN_NBTP Register (Offset = 1Ch) [reset = 06000A03h]

4.5.2.8 MCAN_TSCC Register (Offset = 20h) [reset = 0h]

4.5.2.9 MCAN_TSCV Register (Offset = 24h) [reset = 0h]

4.5.2.10 MCAN_TOCC Register (Offset = 28h) [reset = FFFF0000h]

4.5.2.11 MCAN_TOCV Register (Offset = 2Ch) [reset = FFFFh]

4.5.2.12 MCAN_ECR Register (Offset = 40h) [reset = 0h]

4.5.2.13 MCAN_PSR Register (Offset = 44h) [reset = 707h]

4.5.2.14 MCAN_TDCR Register (Offset = 48h) [reset = 0h]

4.5.2.15 MCAN_IR Register (Offset = 50h) [reset = 0h]

4.5.2.16 MCAN_IE Register (Offset = 54h) [reset = 0h]

4.5.2.17 MCAN_ILS Register (Offset = 58h) [reset = 0h]

4.5.2.18 MCAN_ILE Register (Offset = 5Ch) [reset = 0h]

4.5.2.19 MCAN_GFC Register (Offset = 80h) [reset = 0h]

4.5.2.20 MCAN_SIDFC Register (Offset = 84h) [reset = 0h]

4.5.2.21 MCAN_XIDFC Register (Offset = 88h) [reset = 0h]

4.5.2.22 MCAN_XIDAM Register (Offset = 90h) [reset = 1FFFFFFFh]

4.5.2.23 MCAN_HPMS Register (Offset = 94h) [reset = 0h]

4.5.2.24 MCAN_NDAT1 Register (Offset = 98h) [reset = 0h]

4.5.2.25 MCAN_NDAT2 Register (Offset = 9Ch) [reset = 0h]

4.5.2.26 MCAN_RXF0C Register (Offset = A0h) [reset = 0h]

4.5.2.27 MCAN_RXF0S Register (Offset = A4h) [reset = 0h]

4.5.2.28 MCAN_RXF0A Register (Offset = A8h) [reset = 0h]

4.5.2.29 MCAN_RXBC Register (Offset = ACh) [reset = 0h]

4.5.2.30 MCAN_RXF1C Register (Offset = B0h) [reset = 0h]

4.5.2.31 MCAN_RXF1S Register (Offset = B4h) [reset = 0h]

4.5.2.32 MCAN_RXF1A Register (Offset = B8h) [reset = 0h]

4.5.2.33 MCAN_RXESC Register (Offset = BCh) [reset = 0h]

4.5.2.34 MCAN_TXBC Register (Offset = C0h) [reset = 0h]

4.5.2.35 MCAN_TXFQS Register (Offset = C4h) [reset = 0h]

4.5.2.36 MCAN_TXESC Register (Offset = C8h) [reset = 0h]

4.5.2.37 MCAN_TXBRP Register (Offset = CCh) [reset = 0h]

4.5.2.38 MCAN_TXBAR Register (Offset = D0h) [reset = 0h]

4.5.2.39 MCAN_TXBCR Register (Offset = D4h) [reset = 0h]

4.5.2.40 MCAN_TXBTO Register (Offset = D8h) [reset = 0h]

4.5.2.41 MCAN_TXBCF Register (Offset = DCh) [reset = 0h]

4.5.2.42 MCAN_TXBTIE Register (Offset = E0h) [reset = 0h]

4.5.2.43 MCAN_TXBCIE Register (Offset = E4h) [reset = 0h]

4.5.2.44 MCAN_TXEFC Register (Offset = F0h) [reset = 0h]

4.5.2.45 MCAN_TXEFS Register (Offset = F4h) [reset = 0h]

4.5.2.46 MCAN_TXEFA Register (Offset = F8h) [reset = 0h]