SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Endpoints in MCU_NAVSS0 can be paired with NAVSS0 and vice versa as shown in Table 10-101 (source/destination pairs). The configuration proxy in each subsystem can configure any endpoint in the map on either subsystem without restriction.
Thread Number | NAVSS Instance | Endpoint |
---|---|---|
0x0000 | NAVSS0 | Configuration Proxy |
0x0001 | MCU_NAVSS0 | Configuration Proxy |
0x0002-0x0007 | - | Reserved |
0x0008 | NAVSS0 | UDMAP0 TRSTRM |
0x0009-0x001F | NAVSS0 | Reserved for future UDMA TRSTRM instances |
0x0020 | NAVSS0 | UDMAP0 CFGSTRM |
0x0021-0x003F | - | Reserved for future UDMA CFGSTRM instances |
0x0040-0x0FFF | - | Reserved |
0x1000-0x3FFF | NAVSS0 | UDMAP0 Threads |
0x4000-0x40FF | NAVSS0 | Reserved |
0x4100-0x41FF | NAVSS0 | Reserved |
0x4200-0x42FF | NAVSS0 | Reserved |
0x4300-0x43FF | NAVSS0 | MAIN_PDMA_DEBUG (to PDMA_DEBUG_PSILSS0) |
0x4400-0x44FF | NAVSS0 | MAIN_PDMA_MCASP_G1 (to PDMA_MAIN_MCASP_G1 directly, not through a PSILSS) |
0x4500-0x45FF | NAVSS0 | Reserved |
0x4500-0x45FF | NAVSS0 | Reserved |
0x4600-0x46FF | NAVSS0 | MAIN_PDMA_MISC (to PDMA_MISC_PSILSS0) |
0x4700-0x47FF | NAVSS0 | MAIN_PDMA_USART (to PDMA_USART_PSILSS0) |
0x4800-0x48FF | NAVSS0 | Reserved |
0x4820-0x483F | NAVSS0 | Reserved |
0x4840-0x487F | NAVSS0 | Reserved |
0x4880-0x48FF | NAVSS0 | Reserved |
0x4900-0x49FF | NAVSS0 | Reserved |
0x4A00-0x4AFF | NAVSS0 | CPSW5 (5-port CPSW0) |
0x4B00-0x5FFF | - | Reserved |
0x6000-0x6FFF | MCU_NAVSS0 | UDMAP0 Threads |
0x7000-0x70FF | MCU_NAVSS0 | CPSW0 (2-port MCU_CPSW0) |
0x7100-0x71FF | MCU_NAVSS0 | MCU_PDMA0 |
0x7200-0x72FF | MCU_NAVSS0 | MCU_PDMA1 |
0x7300-0x73FF | MCU_NAVSS0 | MCU_PDMA2 |
0x7400-0x74FF | MCU_NAVSS0 | MCU_PDMA_ADC |
0x7500-0x75FF | MCU_NAVSS0 | SAUL0 (SA0) |
0x7600-0x7FFF | - | Reserved |