The PCIe subsystem does not support the following features:
- Gen4 (16GT/s) operation
- Breaking the x4 link into multiple x1 or x2 links
- PCIe beacon for in-band wake
- Vendor Messaging
- I/O access in inbound direction in RP or EP mode
- Addressing modes other than incremental for burst transactions. As a result, the PCIe addresses cannot be in cacheable memory space.
- Single-root I/O virtualization (SR-IOV)
- Address Translation Services (ATS)
- Quality of Service (QoS)
- L2 power state
- Hot-plug
- PHY loopback
- Reduced Swing Signaling
- Separate Reference Clock with Independent Spread (SRIS)