SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-613 lists the PSI-L configuration registers (PSIL_CFG). They are not memory mapped and are accessed indirectly via CFG_PROXY modules in NAVSS0 and MCU_NAVSS0.
Instance | Base Address |
---|---|
PSIL_CFG | N/A |
Offset | Acronym | Register Name | PSIL_CFG Physical Address |
---|---|---|---|
0h | PSIL_PEER_THREAD_ID_REG | Peer Thread ID Register | N/A |
1h | PSIL_PEER_CREDIT_REG | Peer Credit Register | N/A |
2h | PSIL_ENABLE_REG | Enable Register | N/A |
40h | PSIL_LOCAL_CAPABILITIES_REG | Local Capabilities Register | N/A |
400h to 407h | Real Time Registers | Real Time Registers (varies by module) | N/A |
408h | PSIL_REAL_TIME_ENABLE_REG | Real Time Enable Register | N/A |
409h to 40Fh | Real Time Registers | Real Time Registers (varies by module) | N/A |
PSIL_PEER_THREAD_ID_REG is shown in Figure 10-226 and described in Table 10-615.
Return to Summary Table.
The Peer Thread ID register contains the thread ID of the thread destination which is used for routing the messages. This register is only implemented for source threads.
Instance | Physical Address |
---|---|
PSIL_CFG | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
THREAD_PRIORITY | PEER_THREAD_WIDTH | ||||||
R/W-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PEER_THREAD_ID | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEER_THREAD_ID | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | THREAD_PRIORITY | R/W | 0h | Priority level to use for this source thread in arbitration |
28-24 | PEER_THREAD_WIDTH | R | 0h | Datapath width of paired peer destination thread. 0h - 32-bit 1h - 64-bit 2h - 128-bit 3h - 256-bit 4h - 512-bit |
23-16 | RESERVED | R/W | 0h | Reserved |
15-0 | PEER_THREAD_ID | R/W | 0h | Thread ID to which all nontransfer response, nonconfiguration messages from this thread are sent |
PSIL_PEER_CREDIT_REG is shown in Figure 10-227 and described in Table 10-617.
Return to Summary Table.
This register contains a free credit count in completed destination data phases for the thread destination. This register is only implemented for source threads.
Instance | Physical Address |
---|---|
PSIL_CFG | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CREDIT_CNT | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | CREDIT_CNT | R/W | 0h | Free entries in destination thread. This field is encoded as follows: 0h to 80h - Actual count in data phases 81h to FFh - Reserved |
PSIL_ENABLE_REG is shown in Figure 10-228 and described in Table 10-619.
Return to Summary Table.
This register contains enable control for the thread.
Instance | Physical Address |
---|---|
PSIL_CFG | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ENABLE | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ENABLE | R/W | 0h | Thread enable 0 = thread is disabled and should not perform data transfers. Any input data is discarded. 1 = thread is enabled and may perform data transfers Note: A 1 to 0 transition on this bit may completely reset the channel. Regardless, a channel that is manually disabled via this bit should be assumed to require a full reconfiguration. |
30-0 | RESERVED | R | 0h | Reserved |
PSIL_LOCAL_CAPABILITIES_REG is shown in Figure 10-229 and described in Table 10-621.
Return to Summary Table.
The Local Capabilities Register provides the width and count of the credits for which buffering is available in the local thread. This register can be read by the system configuration software to determine what values to place in the PSIL_PEER_CREDIT_REG and PSIL_PEER_THREAD_ID_REG registers of the paired thread.
Instance | Physical Address |
---|---|
PSIL_CFG | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | LOCAL_THREAD_WIDTH | ||||||
R-0h | R-Xh | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCAL_CREDIT_CNT | |||||||
R-Xh | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R | 0h | Reserved |
28-24 | LOCAL_THREAD_WIDTH | R | -h | Width for the local thread used for pairing purposes. 0h = 4 bytes 1h = 8 bytes 2h = 16 bytes 3h = 32 bytes 4h = 64 bytes 5h = 128 bytes 6h to 1Fh = Reserved |
23-8 | RESERVED | R | 0h | Reserved |
7-0 | LOCAL_CREDIT_CNT | R | -h | Read only local thread free entry count used for pairing purposes. This field is encoded as follows: 0h to 80h - Available count in elements 81h to FFh - Reserved |
PSIL_REAL_TIME_ENABLE_REG is shown in Figure 10-230 and described in Table 10-623.
Return to Summary Table.
Real Time Enable Register
Instance | Physical Address |
---|---|
PSIL_CFG | N/A |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ENABLE | TDOWN | PAUSE | FLUSH | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IDLE | RESERVED | |||||
R-0h | R-0h | R-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ENABLE | R/W | 0h | Destination threads: When set, the thread is enabled and normal data transfers can occur. When cleared, the thread is disabled. When disabled, a thread is expected to discard all held data and new incoming data, clear any internal state (FIFO pointers/occupancies, DMA event counts) back to a reset condition. When disabled, a thread is required to respond to PSI-L transactions so that credit handshake is not disrupted even though data is discarded. A 'hard teardown' can be performed by directly clearing this bit. Source threads: When set, the thread is enabled and the source thread can initiate transfers. When cleared, the thread is disabled. When disabled, the thread is required to continue to track outstanding transactions so that that the credit handshake is not disrupted. If the teardown bit is set, this bit is cleared automatically after the current packet is closed. Directly clearing this bit does not close out the current open packet. Thus the teardown bit should always be used to disable a source thread instead of manually clearing this bit. This bit should be manually cleared only if the source thread is to be reset before being re-enabled. |
30 | TDOWN | R/W | 0h | Destination threads: When set, the thread commences a teardown procedure. To perform a destination teardown, the teardown condition should be set in the source thread and it automatically propagates to this register bit with the normal flow of peripheral data via the TDOWN bit (this bit should not be set directly). Once the thread is fully stopped and ready to be reused (including returning all credits), the ENABLE bit is cleared. Source threads: When set, the thread commences a teardown procedure. It stops transferring data on a boundary which is appropriate for the type of attached peripheral and clear and mask any peripheral specific functionality (for example, DMA event counters). Note that a protocol conversion gasket may have limited visibility into the state of the peripheral and thus may complete teardown at seemingly arbitrary point in the data stream. After stopping data transfer, the source thread sends a 'NULL data' teardown message to the destination thread that also closes the current packet with an EOP. If no packet is open at the time of the teardown, the message also includes SOP (constitutes a new packet). Once the thread teardown is complete and ready to be reused, the ENABLE bit is cleared. Note: NOTE: Before attempting to stop the
clock of PSI-L associated module, software is required to
teardown all active channels either via the UDMA_TRT_CTL_j[30]
TDOWN bit or via the PSIL_REAL_TIME_ENABLE_REG[30] TDOWN bit.
After completion software is also required to clear the
PSIL_ENABLE_REG[31] ENABLE bit in both the PSI-L based
peripherals and UDMA-P. Attempting to stop the clock without first performing the channel teardown or clearing the PSIL_ENABLE_REG[31] ENABLE bit may lead to undefined module behavior. |
29 | PAUSE | R/W | 0h | Destination threads: When set, the thread is in a paused state. It stops transferring data on a boundary which is appropriate for the type of attached peripheral. While paused, data transfers no longer occur but other application specific actions may still occur (for example, DMA event increments). The pause bit can be cleared and data transfers will resume. Source threads: When set, the thread is in a paused state. It stops transferring data on a boundary which is appropriate for the type of attached peripheral. While paused, data transfers no longer occur but other application specific actions may still occur (for example, DMA event increments). The pause bit can be cleared and data transfers will resume. PAUSE does not stop teardown from completing. |
28 | FLUSH | R/W | 0h | Destination threads: When set, causes all destination thread data to be discarded instead of being written to the peripheral. This bit should be set only when a thread fails to complete its teardown procedure normally, because a peripheral is no longer functioning or because some other factor is causing a deadlock beyond the PSI-L interface. Source threads: Not used |
27-2 | RESERVED | R | 0h | Reserved |
1 | IDLE | R | 0h | Destination threads: This is a read-only bit that signifies that the disabled thread is also idle. This bit is read only and can only become set if the ENABLE bit is cleared. Source threads: This is a read-only bit that signifies that the Paused or Disabled channel is also idle. This bit is read only and can only become set if PAUSE is set or ENABLE is cleared. |
0 | RESERVED | R | 0h | Reserved |