SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 6-6 lists the memory-mapped registers for compute cluster configuration and boot vectors control (COMPUTE_CLUSTER0_DMSC_BOOT). All register offset addresses not listed in Table 6-6 should be considered as reserved locations and the register contents should not be modified.
This section describes the registers for compute cluster configuration and boot vectors control. For information about all other registers associated with the memory regions in Table 6-1, see the corresponding Registers sections of:
The emulation and debug registers are not covered in the device TRM.
Instance | Base Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 0000h |
Offset | Acronym | Register Name | COMPUTE_CLUSTER0_DMSC_BOOT Physical Address |
---|---|---|---|
0h | CC_REVISION | Compute Cluster Revision Register | 45A0 0000h |
4h | CC_MSMC_DEF | MSMC Definition Register | 45A0 0004h |
8h | CC_GIC_CONFIG | GIC Configuration Register | 45A0 0008h |
Ch | CC_MISC_CONFIG | MISC Configuration Register | 45A0 000Ch |
1000h + formula | CC_DEF_j | Compute Cluster Definition Register for MSMC port j | 45A0 1000h |
1004h + formula | CC_CP_CONFIG_j | Compute Cluster Configuration Register for MSMC port j | 45A0 1004h |
1008h + formula | CC_RST_VEC_LO_CP0_j | Core 0 Boot Vector Register (Low) for MSMC port j | 45A0 1008h |
100Ch + formula | CC_RST_VEC_HI_CP0_j | Core 0 Boot Vector Register (High) for MSMC port j | 45A0 100Ch |
1010h + formula | CC_RST_VEC_LO_CP1_j | Core 1 Boot Vector Register (Low) for MSMC port j. | 45A0 1010h |
1014h + formula | CC_RST_VEC_HI_CP1_j | Core 1 Boot Vector Register (High) for MSMC port j. | 45A0 1014h |
1028h + formula | CC_PM_CONFIG_j | Power Management Configuration Register for MSMC port j. | 45A0 1028h |
102Ch + formula | CC_PM_STATUS_j | Power Management Status Register for MSMC port j. | 45A0 102Ch |
1030h + formula | CC_PM_FFI_CONFIG_j | Power Management FFI Configuration Register for MSMC port j. | 45A0 1030h |
1034h + formula | CC_MISC_CORE_CONFIG_j | MISC Core Configuration Register for MSMC port j. | 45A0 1034h |
CC_REVISION is shown in Figure 6-2 and described in Table 6-8.
Return to Summary Table.
Compute Cluster Revision Register
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-60000000h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 60000000h | TI internal data. |
CC_MSMC_DEF is shown in Figure 6-3 and described in Table 6-10.
Return to Summary Table.
MSMC Definition Register
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_COREPAC | ||||||||||||||
R-0h | R-0h | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | NUM_COREPAC | R | 0h | Denotes the number of corepacs connected to compute cluster. 0h - Two corepacs |
CC_GIC_CONFIG is shown in Figure 6-4 and described in Table 6-12.
Return to Summary Table.
GIC Configuration Register.
GIC0 has input signals cpu_active_X_N (where X = A72SS number; N = Core number) which indicate when a core is active and available for routing SPIs unlike being in a software-transparent low-power mode in which case SPIs are not routed to, and a core wake-up would result in increased power consumption.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CP0_CPU_ACTIVE | ||||||
R/W-Fh | R/W-Fh | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GIC_FFI_MODE_DIS | GIC_SECURE | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | RESERVED | R/W | Fh | Reserved |
11-8 | CP0_CPU_ACTIVE | R/W | Fh | A72SS0 Cores active Bits [11-10]: Reserved Bit [9]: 0h - A72SS0 Core 1 is in software-transparent low-power mode such as retention 1h - A72SS0 Core 1 is active and available for shared SPIs Bit [8]: 0h - A72SS0 Core 0 is in software-transparent low-power mode such as retention 1h - A72SS0 Core 0 is active and available for shared SPIs |
7-2 | RESERVED | R | 0h | Reserved |
1 | GIC_FFI_MODE_DIS | R/W | 0h | Disables AXI auto responses to ARM in FFI mode. |
0 | GIC_SECURE | R/W | 0h | Not used on this SoC |
CC_MISC_CONFIG is shown in Figure 6-5 and described in Table 6-14.
Return to Summary Table.
MISC Configuration Register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DISABLE_EN_RDATA_FORWARDING | DISABLE_NRT_ESCALATION | NOGATE_MSMC_CFG | NOGATE_MSMC_DMSC | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | DISABLE_EN_RDATA_FORWARDING | R/W | 0h | Disable control for AXI2VBUSMC return data forwarding feature |
2 | DISABLE_NRT_ESCALATION | R/W | 0h | Disable control for MSMC NRT escalation feature |
1 | NOGATE_MSMC_CFG | R/W | 0h | No gate control for the Configuration Interconnect (see Compute Cluster Overview) and related bridges |
0 | NOGATE_MSMC_DMSC | R/W | 0h | No gate control for the DMSC Interconnect (see Compute Cluster Overview) and related bridges |
CC_DEF_j is shown in Figure 6-6 and described in Table 6-16.
Return to Summary Table.
Compute Cluster Definition Register for MSMC port j
Offset = 1000h*(j + 1); where j = 0h
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 1000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | SRAM_SIZE | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | NUM_CORES | ||||||
R-0h | R-1h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
COREPAC_TYPE_DSP | |||||||
R-FFh | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COREPAC_TYPE_ARM | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27-24 | SRAM_SIZE | R | 0h | SRAM size (if present in the corepac) 0h - 0 bytes |
23-18 | RESERVED | R | 0h | Reserved |
17-16 | NUM_CORES | R | 1h | Number of cores in the corepac 0h - One core 1h - Two cores 2h - Four cores 3h - Reserved |
15-8 | COREPAC_TYPE_DSP | R | FFh | Not used on this SoC |
7-0 | COREPAC_TYPE_ARM | R | 1h | MSMC port "j" configuration 0h - A53 corepac connected to MSMC port "j" 1h - A72 corepac connected to MSMC port "j" 2h to FEh - Reserved FFh - Port not used for ARM |
CC_CP_CONFIG_j is shown in Figure 6-7 and described in Table 6-18.
Return to Summary Table.
Compute Cluster Configuration Register for MSMC port j
Offset = 1004h*(j + 1); where j = 0h
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 1004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ENDIAN | RESERVED | L2ACCESS_LAT | L2PIPELINE_LAT | ||||
R/W-0h | R-0h | R/W-2h | R/W-1h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
L2PIPELINE_LAT | RESERVED | ||||||
R/W-1h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CP15DISABLE | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CONFIGTE | AARCH | ||||||
R/W-0h | R/W-Fh | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ENDIAN | R/W | 0h | Not used on this SoC |
30-29 | RESERVED | R | 0h | Reserved |
28-25 | L2ACCESS_LAT | R/W | 2h | Not used on this SoC |
24-21 | L2PIPELINE_LAT | R/W | 1h | Not used on this SoC |
20-12 | RESERVED | R | 0h | Reserved |
11-8 | CP15DISABLE | R/W | 0h | Disable write access to some secure CP15 registers. Valid only for Arm corepacs. |
7-4 | CONFIGTE | R/W | 0h | Enable T32 exceptions. It sets the initial value of the TE bit in the CP15 SCTLR register. This pin is sampled only during reset of the processor. Valid only for Arm corepacs. Bits [7-6]: Reserved Bit [5]: 0h - TE bit is LOW for core 1 of A72SS0 1h - TE bit is HIGH for core 1 of A72SS0 Bit [4]: 0h - TE bit is LOW for core 0 of A72SS0 1h - TE bit is HIGH for core 0 of A72SS0 |
3-0 | AARCH | R/W | Fh | Arm Architecture. Valid only for Arm corepacs. Bits [3-2]: Reserved Bit [1]: 0h - AArch32 for core 1 of A72SS0 1h - AArch64 for core 1 of A72SS0 Bit [0]: 0h - AArch32 for core 0 of A72SS0 1h - AArch64 for core 0 of A72SS0 |
CC_RST_VEC_LO_CP0_j is shown in Figure 6-8 and described in Table 6-20.
Return to Summary Table.
Core 0 Boot Vector Register (Low) for MSMC port j
Offset = 1008h*(j + 1); where j = 0h
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 1008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET_BASE_VECTOR_LO | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESET_BASE_VECTOR_LO | R/W | 0h | Low reset base vector (bits [33-2]) for Core 0 of a corepac connected to MSMC port j. |
CC_RST_VEC_HI_CP0_j is shown in Figure 6-9 and described in Table 6-22.
Return to Summary Table.
Core 0 Boot Vector Register (High) for MSMC port j
Offset = 100Ch*(j + 1); where j = 0h
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 100Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESET_BASE_VECTOR_HI | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET_BASE_VECTOR_HI | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | Reserved |
16-0 | RESET_BASE_VECTOR_HI | R/W | 0h | High reset base vector (bits [39-34]) for Core 0 of a corepac connected to MSMC port j. |
CC_RST_VEC_LO_CP1_j is shown in Figure 6-10 and described in Table 6-24.
Return to Summary Table.
Core 1 Boot Vector Register (Low) for MSMC port j.
Offset = 1010h*(j + 1); where j = 0h
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 1010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET_BASE_VECTOR_LO | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESET_BASE_VECTOR_LO | R/W | 0h | Low reset base vector (bits [33-2]) for Core 1 of a corepac connected to MSMC port j. |
CC_RST_VEC_HI_CP1_j is shown in Figure 6-11 and described in Table 6-26.
Return to Summary Table.
Core 1 Boot Vector Register (High) for MSMC port j.
Offset = 1014h*(j + 1); where j = 0h
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 1014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESET_BASE_VECTOR_HI | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET_BASE_VECTOR_HI | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | Reserved |
16-0 | RESET_BASE_VECTOR_HI | R/W | 0h | High reset base vector (bits [39-34]) for Core 1 of a corepac connected to MSMC port j. |
CC_PM_CONFIG_j is shown in Figure 6-12 and described in Table 6-28.
Return to Summary Table.
Power Management Configuration Register for MSMC port j.
Offset = 1028h*(j + 1); where j = 0h
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 1028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DBGPWRUP0 | ||||||
R-0h | R/W-Fh | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBGL1RSTDISABLE0 | CLEAR_MON0 | L2_FLUSHREQ0 | BROADCAST_INNER0 | CACHE_BROADCAST0 | SYS_BARR0 | ACP_MASTER0 | SNOOP_IF0 |
R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-1h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-8 | DBGPWRUP0 | R/W | Fh | Core power up Bits [11-10]: Reserved Bit [9]: 0h - A72SSj Core 1 is powered down 1h - A72SSj Core 1 is powered up Bit [8]: 0h - A72SSj Core 0 is powered down 1h - A72SSj Core 0 is powered up |
7 | DBGL1RSTDISABLE0 | R/W | 0h | Disable L1 data cache automatic invalidate on reset. This pin is sampled only during reset of the processor. 0h - Enable automatic invalidation of L1 data cache on reset 1h - Disable automatic invalidation of L1 data cache on reset |
6 | CLEAR_MON0 | R/W | 0h | Request to clear the external global exclusive monitor. This sends a WFE wake-up event to all cores in the cluster. When set HIGH the global exclusive monitor in the system is requesting the processor EVENT registers to be set HIGH. |
5 | L2_FLUSHREQ0 | R/W | 0h | ARM L2 hardware flush request |
4 | BROADCAST_INNER0 | R/W | 1h | Enable broadcasting of inner shareable and outer sharable transactions 0h - Broadcasting disabled 1h - Broadcasting enabled |
3 | CACHE_BROADCAST0 | R/W | 1h | Enable Broadcasting of cache maintenance transactions 0h - Broadcasting disabled 1h - Broadcasting enabled |
2 | SYS_BARR0 | R/W | 0h | Disable broadcasting of barriers 0h - Broadcasting enabled 1h - Broadcasting disabled |
1 | ACP_MASTER0 | R/W | 0h | ACP master is inactive and is not participating in coherency 0h - ACP Master is active 1h - ACP Master is inactive Note: NOTE: There must be no outstanding transactions when the master asserts this signal, and while it is asserted the master must not send any new transactions |
0 | SNOOP_IF0 | R/W | 0h | Snoop interface is inactive and not participating in coherency 0h - Snoop interface is active 1h - Snoop interface is inactive |
CC_PM_STATUS_j is shown in Figure 6-13 and described in Table 6-30.
Return to Summary Table.
Power Management Status Register for MSMC port j.
Offset = 102Ch*(j + 1); where j = 0h
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 102Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CLEAR_MONITOR_ACK0 | STANDBY_WFI_L20 | L2_HW_FLUSH0 | SMPEN0 | |||
R-0h | R-0h | R-1h | R-0h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU3_WFE0 | CPU2_WFE0 | CPU1_WFE0 | CPU0_WFE0 | CPU3_WFI0 | CPU2_WFI0 | CPU1_WFI0 | CPU0_WFI0 |
R-0h | R-0h | R-0h | R-0h | R-1h | R-1h | R-1h | R-1h |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | Reserved |
14 | CLEAR_MONITOR_ACK0 | R | 0h | Clearing of the external global exclusive monitor acknowledge. When set HIGH the processor EVENT registers have been set HIGH. |
13 | STANDBY_WFI_L20 | R | 1h | L2 in WFI low power state indication |
12 | L2_HW_FLUSH0 | R | 0h | L2 hardware flush complete |
11-8 | SMPEN0 | R | 0h | Corepac taking part in coherency indication |
7 | CPU3_WFE0 | R | 0h | Reserved |
6 | CPU2_WFE0 | R | 0h | Reserved |
5 | CPU1_WFE0 | R | 0h | CPU in WFE state |
4 | CPU0_WFE0 | R | 0h | CPU in WFE state |
3 | CPU3_WFI0 | R | 1h | Reserved |
2 | CPU2_WFI0 | R | 1h | Reserved |
1 | CPU1_WFI0 | R | 1h | CPU in WFI state |
0 | CPU0_WFI0 | R | 1h | CPU in WFI state |
CC_PM_FFI_CONFIG_j is shown in Figure 6-14 and described in Table 6-32.
Return to Summary Table.
Power Management FFI Configuration Register for MSMC port j.
Offset = 1030h*(j + 1); where j = 0h
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 1030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT_VAL | FORCE_TIMEOUT | EN_TIMEOUT_DETECT | DIS_EGLN_EXTERNAL_FLUSH_CNTRL | FFI_MODE_EN | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | 0h | Reserved |
6-4 | TIMEOUT_VAL | R/W | 0h | Selects one of the 8 timeout values in number of cycles. 0h - 1024 1h - 4096 2h - 16384 3h - 65536 4h - 262144 5h - 1048576 6h - 2097152 7h - 4194303 |
3 | FORCE_TIMEOUT | R/W | 0h | Forces timeout interrupt. |
2 | EN_TIMEOUT_DETECT | R/W | 0h | Enables timeout detect for snoop commands in AXI2VBUSMC. |
1 | DIS_EGLN_EXTERNAL_FLUSH_CNTRL | R/W | 0h | Disables AXI2VBUSMC external port control to trigger FFI mode. |
0 | FFI_MODE_EN | R/W | 0h | Enables FFI mode. |
CC_MISC_CORE_CONFIG_j is shown in Figure 6-15 and described in Table 6-34.
Return to Summary Table.
MISC Core Configuration Register for MSMC port j.
Offset = 1034h*(j + 1); where j = 0h
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_DMSC_BOOT | 45A0 1034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ARM_ALLOCATE_VALUE | ARM_ALLOCATE_OVERRIDE | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-1 | ARM_ALLOCATE_VALUE | R/W | 0h | Override value for allocation hint. |
0 | ARM_ALLOCATE_OVERRIDE | R/W | 0h | Control to override arm outer allocation hint. |