SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The Error Interrupt Raw Status Register contains the raw status of the gasket interrupts
Bits | Field | Type | Reset | Description |
---|---|---|---|---|
31:3 | Reserved | r | 0x0 | Reserved. Read as 0. |
2 | cmd | r/w1ts | 0x0 |
This field represents the raw status of the Command Timeout Error. Read 0 – No pending command timeout interrupt 1 – Pending command timeout interrupt Write 0 – No effect 1 – Set command timeout interrupt |
1 | unexp | r/w1ts | 0x0 |
This field represents the raw status of the Unexpected Response Error. Read 0 – No pending unexpected response interrupt 1 – Pending unexpected response interrupt Write 0 – No effect 1 – Set unexpected response interrupt |
0 | timeout | r/w1ts | 0x0 |
This field represents the raw status of the Timeout Error Interrupt. Read 0 – No pending timeout interrupt 1 – Pending timeout interrupt Write 0 – No effect 1 – Set timeout interrupt |