SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-438 lists the memory-mapped registers for the NAVSS0_UDMASS_RINGACC0_CFG_MON. All register offset addresses not listed in Table 10-438 should be considered as reserved locations and the register contents should not be modified.
The Ring Accelerator Monitor Control / Status Registers region is accessed by setting the cfg_rsel signal to 3 during the access. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG_MON | 3200 0000h |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON | 2A28 0000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_RINGACC0_CFG_MON Physical Address | MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON Physical Address |
---|---|---|---|---|
0h + formula | RINGACC_CONTROL_j | Monitor Control Register | 3200 0000h + formula | 2A280 000h + formula |
4h + formula | RINGACC_QUEUE_j | Monitor Queue Register | 3200 0004h + formula | 2A280 004h + formula |
8h + formula | RINGACC_DATA0_j | Monitor Data Register | 3200 0008h + formula | 2A280 008h + formula |
Ch + formula | RINGACC_DATA1_j | Monitor Data Register | 3200 000Ch + formula | 2A280 00Ch + formula |
RINGACC_CONTROL_j is shown in Figure 10-162 and described in Table 10-440.
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Monitor Control Register
Offset = 0h + (j * 1000h); where j = 0h to 1Fh
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG_MON | 3200 0000h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON | 2A28 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EVT | |||||||||||||||
R/W-FFFFh | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOURCE | RESERVED | MODE | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | EVT | R/W | FFFFh | Event to produce. |
15-12 | RESERVED | R/W | X | |
11-8 | SOURCE | R/W | 0h | Monitor source selection. 0 = element count 1 = reserved 2 = reseved |
7-3 | RESERVED | R/W | X | |
2-0 | MODE | R/W | 0h | Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting. |
RINGACC_QUEUE_j is shown in Figure 10-163 and described in Table 10-442.
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Monitor Queue Register
Offset = 4h + (j * 1000h); where j = 0h to 1Fh
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG_MON | 3200 0004h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON | 2A28 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | VAL | R/W | 0h | Queue to monitor. |
RINGACC_DATA0_j is shown in Figure 10-164 and described in Table 10-444.
Return to Summary Table.
Monitor Data Register
Offset = 8h + (j * 1000h); where j = 0h to 1Fh
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG_MON | 3200 0008h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON | 2A28 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count. |
RINGACC_DATA1_j is shown in Figure 10-165 and described in Table 10-446.
Return to Summary Table.
Monitor Data Register
Offset = Ch + (j * 1000h); where j = 0h to 1Fh
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG_MON | 3200 000Ch + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON | 2A28 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used. |