SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There are registers within the CTRL_MMR0 module address space that are used to dynamically change the DDR clock frequency to support LPDDR4 Frequency Set Point (FSP). These registers are shown in Table 5-693. For more information, see Section 8.2.4.5 DDRSS Dynamic Frequency Change Interface in Chapter 8 Memory Controllers.