SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-3500 lists the memory-mapped registers for the PCIE_INTD. All register offset addresses not listed in Table 12-3500 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0000h |
Offset | Acronym | Register Name | PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG Physical Address |
---|---|---|---|
0h | PCIE_INTD_REVISION | 0291 0000h | |
10h | PCIE_INTD_EOI_REG | 0291 0010h | |
14h | PCIE_INTD_INTR_VECTOR_REG | 0291 0014h | |
100h | PCIE_INTD_ENABLE_REG_SYS_0 | 0291 0100h | |
104h | PCIE_INTD_ENABLE_REG_SYS_1 | 0291 0104h | |
108h | PCIE_INTD_ENABLE_REG_SYS_2 | 0291 0108h | |
300h | PCIE_INTD_ENABLE_CLR_REG_SYS_0 | 0291 0300h | |
304h | PCIE_INTD_ENABLE_CLR_REG_SYS_1 | 0291 0304h | |
308h | PCIE_INTD_ENABLE_CLR_REG_SYS_2 | 0291 0308h | |
500h | PCIE_INTD_STATUS_REG_SYS_0 | 0291 0500h | |
504h | PCIE_INTD_STATUS_REG_SYS_1 | 0291 0504h | |
508h | PCIE_INTD_STATUS_REG_SYS_2 | 0291 0508h | |
708h | PCIE_INTD_STATUS_CLR_REG_SYS_2 | 0291 0708h | |
A80h | PCIE_INTD_INTR_VECTOR_REG_SYS | 0291 0A80h |
PCIE_INTD_REVISION is shown in Figure 12-1777 and described in Table 12-3502.
Return to Summary Table.
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | FUNCTION | |||||||||||||
R-1h | R-2h | R-690h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTLVER | MAJREV | CUSTOM | MINREV | ||||||||||||
R-14h | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | BU |
27-16 | FUNCTION | R | 690h | Module ID |
15-11 | RTLVER | R | 14h | RTL revisions |
10-8 | MAJREV | R | 2h | Major PCIE_INTD_REVISION |
7-6 | CUSTOM | R | 0h | Custom PCIE_INTD_REVISION |
5-0 | MINREV | R | 0h | Minor PCIE_INTD_REVISION |
PCIE_INTD_EOI_REG is shown in Figure 12-1778 and described in Table 12-3504.
Return to Summary Table.
End of Interrupt Register
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_VECTOR | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | EOI_VECTOR | R/W | 0h | End of Interrupt Vector |
PCIE_INTD_INTR_VECTOR_REG is shown in Figure 12-1779 and described in Table 12-3506.
Return to Summary Table.
Interrupt Vector Register
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTR_VECTOR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | INTR_VECTOR | R | 0h | Interrupt Vector Register |
PCIE_INTD_ENABLE_REG_SYS_0 is shown in Figure 12-1780 and described in Table 12-3508.
Return to Summary Table.
Enable Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_SYS_EN_PCIE_DOWNSTREAM_5 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_4 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_3 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_2 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_1 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_0 | |
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | X | Reserved |
5 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_5 | R/W1S | 0h | Enable Set for sys_en_pcie_downstream_5 |
4 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_4 | R/W1S | 0h | Enable Set for sys_en_pcie_downstream_4 |
3 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_3 | R/W1S | 0h | Enable Set for sys_en_pcie_downstream_3 |
2 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_2 | R/W1S | 0h | Enable Set for sys_en_pcie_downstream_2 |
1 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_1 | R/W1S | 0h | Enable Set for sys_en_pcie_downstream_1 |
0 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_0 | R/W1S | 0h | Enable Set for sys_en_pcie_downstream_0 |
PCIE_INTD_ENABLE_REG_SYS_1 is shown in Figure 12-1781 and described in Table 12-3510.
Return to Summary Table.
Enable Register 1
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0104h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | ENABLE_SYS_EN_PCIE_PWR_STATE | ENABLE_SYS_EN_PCIE_LEGACY_3 | ENABLE_SYS_EN_PCIE_LEGACY_2 | ||||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ENABLE_SYS_EN_PCIE_LEGACY_1 | ENABLE_SYS_EN_PCIE_LEGACY_0 | ENABLE_SYS_EN_PCIE_FLR_21 | ENABLE_SYS_EN_PCIE_FLR_20 | ENABLE_SYS_EN_PCIE_FLR_19 | ENABLE_SYS_EN_PCIE_FLR_18 | ENABLE_SYS_EN_PCIE_FLR_17 | ENABLE_SYS_EN_PCIE_FLR_16 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ENABLE_SYS_EN_PCIE_FLR_15 | ENABLE_SYS_EN_PCIE_FLR_14 | ENABLE_SYS_EN_PCIE_FLR_13 | ENABLE_SYS_EN_PCIE_FLR_12 | ENABLE_SYS_EN_PCIE_FLR_11 | ENABLE_SYS_EN_PCIE_FLR_10 | ENABLE_SYS_EN_PCIE_FLR_9 | ENABLE_SYS_EN_PCIE_FLR_8 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE_SYS_EN_PCIE_FLR_7 | ENABLE_SYS_EN_PCIE_FLR_6 | ENABLE_SYS_EN_PCIE_FLR_5 | ENABLE_SYS_EN_PCIE_FLR_4 | ENABLE_SYS_EN_PCIE_FLR_3 | ENABLE_SYS_EN_PCIE_FLR_2 | ENABLE_SYS_EN_PCIE_FLR_1 | ENABLE_SYS_EN_PCIE_FLR_0 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | X | Reserved |
26 | ENABLE_SYS_EN_PCIE_PWR_STATE | R/W1S | 0h | Enable Set for sys_en_pcie_pwr_state |
25 | ENABLE_SYS_EN_PCIE_LEGACY_3 | R/W1S | 0h | Enable Set for sys_en_pcie_legacy_3 |
24 | ENABLE_SYS_EN_PCIE_LEGACY_2 | R/W1S | 0h | Enable Set for sys_en_pcie_legacy_2 |
23 | ENABLE_SYS_EN_PCIE_LEGACY_1 | R/W1S | 0h | Enable Set for sys_en_pcie_legacy_1 |
22 | ENABLE_SYS_EN_PCIE_LEGACY_0 | R/W1S | 0h | Enable Set for sys_en_pcie_legacy_0 |
21 | ENABLE_SYS_EN_PCIE_FLR_21 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_21 |
20 | ENABLE_SYS_EN_PCIE_FLR_20 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_20 |
19 | ENABLE_SYS_EN_PCIE_FLR_19 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_19 |
18 | ENABLE_SYS_EN_PCIE_FLR_18 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_18 |
17 | ENABLE_SYS_EN_PCIE_FLR_17 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_17 |
16 | ENABLE_SYS_EN_PCIE_FLR_16 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_16 |
15 | ENABLE_SYS_EN_PCIE_FLR_15 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_15 |
14 | ENABLE_SYS_EN_PCIE_FLR_14 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_14 |
13 | ENABLE_SYS_EN_PCIE_FLR_13 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_13 |
12 | ENABLE_SYS_EN_PCIE_FLR_12 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_12 |
11 | ENABLE_SYS_EN_PCIE_FLR_11 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_11 |
10 | ENABLE_SYS_EN_PCIE_FLR_10 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_10 |
9 | ENABLE_SYS_EN_PCIE_FLR_9 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_9 |
8 | ENABLE_SYS_EN_PCIE_FLR_8 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_8 |
7 | ENABLE_SYS_EN_PCIE_FLR_7 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_7 |
6 | ENABLE_SYS_EN_PCIE_FLR_6 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_6 |
5 | ENABLE_SYS_EN_PCIE_FLR_5 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_5 |
4 | ENABLE_SYS_EN_PCIE_FLR_4 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_4 |
3 | ENABLE_SYS_EN_PCIE_FLR_3 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_3 |
2 | ENABLE_SYS_EN_PCIE_FLR_2 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_2 |
1 | ENABLE_SYS_EN_PCIE_FLR_1 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_1 |
0 | ENABLE_SYS_EN_PCIE_FLR_0 | R/W1S | 0h | Enable Set for sys_en_pcie_flr_0 |
PCIE_INTD_ENABLE_REG_SYS_2 is shown in Figure 12-1782 and described in Table 12-3512.
Return to Summary Table.
Enable Register 2
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0108h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ENABLE_SYS_EN_PCIE_PTM | ENABLE_SYS_EN_PCIE_LINK_STATE | ENABLE_SYS_EN_PCIE_HOT_RESET | ENABLE_SYS_EN_PCIE_ERROR_2 | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE_SYS_EN_PCIE_ERROR_1 | ENABLE_SYS_EN_PCIE_ERROR_0 | ENABLE_SYS_EN_PCIE_DPA_5 | ENABLE_SYS_EN_PCIE_DPA_4 | ENABLE_SYS_EN_PCIE_DPA_3 | ENABLE_SYS_EN_PCIE_DPA_2 | ENABLE_SYS_EN_PCIE_DPA_1 | ENABLE_SYS_EN_PCIE_DPA_0 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | X | Reserved |
11 | ENABLE_SYS_EN_PCIE_PTM | R/W1S | 0h | Enable Set for sys_en_pcie_ptm |
10 | ENABLE_SYS_EN_PCIE_LINK_STATE | R/W1S | 0h | Enable Set for sys_en_pcie_link_state |
9 | ENABLE_SYS_EN_PCIE_HOT_RESET | R/W1S | 0h | Enable Set for sys_en_pcie_hot_reset |
8 | ENABLE_SYS_EN_PCIE_ERROR_2 | R/W1S | 0h | Enable Set for sys_en_pcie_error_2 |
7 | ENABLE_SYS_EN_PCIE_ERROR_1 | R/W1S | 0h | Enable Set for sys_en_pcie_error_1 |
6 | ENABLE_SYS_EN_PCIE_ERROR_0 | R/W1S | 0h | Enable Set for sys_en_pcie_error_0 |
5 | ENABLE_SYS_EN_PCIE_DPA_5 | R/W1S | 0h | Enable Set for sys_en_pcie_dpa_5 |
4 | ENABLE_SYS_EN_PCIE_DPA_4 | R/W1S | 0h | Enable Set for sys_en_pcie_dpa_4 |
3 | ENABLE_SYS_EN_PCIE_DPA_3 | R/W1S | 0h | Enable Set for sys_en_pcie_dpa_3 |
2 | ENABLE_SYS_EN_PCIE_DPA_2 | R/W1S | 0h | Enable Set for sys_en_pcie_dpa_2 |
1 | ENABLE_SYS_EN_PCIE_DPA_1 | R/W1S | 0h | Enable Set for sys_en_pcie_dpa_1 |
0 | ENABLE_SYS_EN_PCIE_DPA_0 | R/W1S | 0h | Enable Set for sys_en_pcie_dpa_0 |
PCIE_INTD_ENABLE_CLR_REG_SYS_0 is shown in Figure 12-1783 and described in Table 12-3514.
Return to Summary Table.
Enable Clear Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0300h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_SYS_EN_PCIE_DOWNSTREAM_5_CLR | ENABLE_SYS_EN_PCIE_DOWNSTREAM_4_CLR | ENABLE_SYS_EN_PCIE_DOWNSTREAM_3_CLR | ENABLE_SYS_EN_PCIE_DOWNSTREAM_2_CLR | ENABLE_SYS_EN_PCIE_DOWNSTREAM_1_CLR | ENABLE_SYS_EN_PCIE_DOWNSTREAM_0_CLR | |
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | X | Reserved |
5 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_5_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_downstream_5 |
4 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_4_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_downstream_4 |
3 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_3_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_downstream_3 |
2 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_2_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_downstream_2 |
1 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_1_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_downstream_1 |
0 | ENABLE_SYS_EN_PCIE_DOWNSTREAM_0_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_downstream_0 |
PCIE_INTD_ENABLE_CLR_REG_SYS_1 is shown in Figure 12-1784 and described in Table 12-3516.
Return to Summary Table.
Enable Clear Register 1
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0304h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | ENABLE_SYS_EN_PCIE_PWR_STATE_CLR | ENABLE_SYS_EN_PCIE_LEGACY_3_CLR | ENABLE_SYS_EN_PCIE_LEGACY_2_CLR | ||||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ENABLE_SYS_EN_PCIE_LEGACY_1_CLR | ENABLE_SYS_EN_PCIE_LEGACY_0_CLR | ENABLE_SYS_EN_PCIE_FLR_21_CLR | ENABLE_SYS_EN_PCIE_FLR_20_CLR | ENABLE_SYS_EN_PCIE_FLR_19_CLR | ENABLE_SYS_EN_PCIE_FLR_18_CLR | ENABLE_SYS_EN_PCIE_FLR_17_CLR | ENABLE_SYS_EN_PCIE_FLR_16_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ENABLE_SYS_EN_PCIE_FLR_15_CLR | ENABLE_SYS_EN_PCIE_FLR_14_CLR | ENABLE_SYS_EN_PCIE_FLR_13_CLR | ENABLE_SYS_EN_PCIE_FLR_12_CLR | ENABLE_SYS_EN_PCIE_FLR_11_CLR | ENABLE_SYS_EN_PCIE_FLR_10_CLR | ENABLE_SYS_EN_PCIE_FLR_9_CLR | ENABLE_SYS_EN_PCIE_FLR_8_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE_SYS_EN_PCIE_FLR_7_CLR | ENABLE_SYS_EN_PCIE_FLR_6_CLR | ENABLE_SYS_EN_PCIE_FLR_5_CLR | ENABLE_SYS_EN_PCIE_FLR_4_CLR | ENABLE_SYS_EN_PCIE_FLR_3_CLR | ENABLE_SYS_EN_PCIE_FLR_2_CLR | ENABLE_SYS_EN_PCIE_FLR_1_CLR | ENABLE_SYS_EN_PCIE_FLR_0_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | X | Reserved |
26 | ENABLE_SYS_EN_PCIE_PWR_STATE_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_pwr_state |
25 | ENABLE_SYS_EN_PCIE_LEGACY_3_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_legacy_3 |
24 | ENABLE_SYS_EN_PCIE_LEGACY_2_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_legacy_2 |
23 | ENABLE_SYS_EN_PCIE_LEGACY_1_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_legacy_1 |
22 | ENABLE_SYS_EN_PCIE_LEGACY_0_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_legacy_0 |
21 | ENABLE_SYS_EN_PCIE_FLR_21_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_21 |
20 | ENABLE_SYS_EN_PCIE_FLR_20_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_20 |
19 | ENABLE_SYS_EN_PCIE_FLR_19_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_19 |
18 | ENABLE_SYS_EN_PCIE_FLR_18_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_18 |
17 | ENABLE_SYS_EN_PCIE_FLR_17_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_17 |
16 | ENABLE_SYS_EN_PCIE_FLR_16_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_16 |
15 | ENABLE_SYS_EN_PCIE_FLR_15_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_15 |
14 | ENABLE_SYS_EN_PCIE_FLR_14_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_14 |
13 | ENABLE_SYS_EN_PCIE_FLR_13_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_13 |
12 | ENABLE_SYS_EN_PCIE_FLR_12_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_12 |
11 | ENABLE_SYS_EN_PCIE_FLR_11_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_11 |
10 | ENABLE_SYS_EN_PCIE_FLR_10_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_10 |
9 | ENABLE_SYS_EN_PCIE_FLR_9_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_9 |
8 | ENABLE_SYS_EN_PCIE_FLR_8_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_8 |
7 | ENABLE_SYS_EN_PCIE_FLR_7_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_7 |
6 | ENABLE_SYS_EN_PCIE_FLR_6_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_6 |
5 | ENABLE_SYS_EN_PCIE_FLR_5_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_5 |
4 | ENABLE_SYS_EN_PCIE_FLR_4_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_4 |
3 | ENABLE_SYS_EN_PCIE_FLR_3_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_3 |
2 | ENABLE_SYS_EN_PCIE_FLR_2_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_2 |
1 | ENABLE_SYS_EN_PCIE_FLR_1_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_1 |
0 | ENABLE_SYS_EN_PCIE_FLR_0_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_flr_0 |
PCIE_INTD_ENABLE_CLR_REG_SYS_2 is shown in Figure 12-1785 and described in Table 12-3518.
Return to Summary Table.
Enable Clear Register 2
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0308h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ENABLE_SYS_EN_PCIE_PTM_CLR | ENABLE_SYS_EN_PCIE_LINK_STATE_CLR | ENABLE_SYS_EN_PCIE_HOT_RESET_CLR | ENABLE_SYS_EN_PCIE_ERROR_2_CLR | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE_SYS_EN_PCIE_ERROR_1_CLR | ENABLE_SYS_EN_PCIE_ERROR_0_CLR | ENABLE_SYS_EN_PCIE_DPA_5_CLR | ENABLE_SYS_EN_PCIE_DPA_4_CLR | ENABLE_SYS_EN_PCIE_DPA_3_CLR | ENABLE_SYS_EN_PCIE_DPA_2_CLR | ENABLE_SYS_EN_PCIE_DPA_1_CLR | ENABLE_SYS_EN_PCIE_DPA_0_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | X | Reserved |
11 | ENABLE_SYS_EN_PCIE_PTM_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_ptm |
10 | ENABLE_SYS_EN_PCIE_LINK_STATE_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_link_state |
9 | ENABLE_SYS_EN_PCIE_HOT_RESET_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_hot_reset |
8 | ENABLE_SYS_EN_PCIE_ERROR_2_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_error_2 |
7 | ENABLE_SYS_EN_PCIE_ERROR_1_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_error_1 |
6 | ENABLE_SYS_EN_PCIE_ERROR_0_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_error_0 |
5 | ENABLE_SYS_EN_PCIE_DPA_5_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_dpa_5 |
4 | ENABLE_SYS_EN_PCIE_DPA_4_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_dpa_4 |
3 | ENABLE_SYS_EN_PCIE_DPA_3_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_dpa_3 |
2 | ENABLE_SYS_EN_PCIE_DPA_2_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_dpa_2 |
1 | ENABLE_SYS_EN_PCIE_DPA_1_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_dpa_1 |
0 | ENABLE_SYS_EN_PCIE_DPA_0_CLR | R/W1C | 0h | Enable Clear for sys_en_pcie_dpa_0 |
PCIE_INTD_STATUS_REG_SYS_0 is shown in Figure 12-1786 and described in Table 12-3520.
Return to Summary Table.
Status Register 0
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STATUS_SYS_PCIE_DOWNSTREAM_5 | STATUS_SYS_PCIE_DOWNSTREAM_4 | STATUS_SYS_PCIE_DOWNSTREAM_3 | STATUS_SYS_PCIE_DOWNSTREAM_2 | STATUS_SYS_PCIE_DOWNSTREAM_1 | STATUS_SYS_PCIE_DOWNSTREAM_0 | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | X | Reserved |
5 | STATUS_SYS_PCIE_DOWNSTREAM_5 | R | 0h | Status for sys_en_pcie_downstream_5 |
4 | STATUS_SYS_PCIE_DOWNSTREAM_4 | R | 0h | Status for sys_en_pcie_downstream_4 |
3 | STATUS_SYS_PCIE_DOWNSTREAM_3 | R | 0h | Status for sys_en_pcie_downstream_3 |
2 | STATUS_SYS_PCIE_DOWNSTREAM_2 | R | 0h | Status for sys_en_pcie_downstream_2 |
1 | STATUS_SYS_PCIE_DOWNSTREAM_1 | R | 0h | Status for sys_en_pcie_downstream_1 |
0 | STATUS_SYS_PCIE_DOWNSTREAM_0 | R | 0h | Status for sys_en_pcie_downstream_0 |
PCIE_INTD_STATUS_REG_SYS_1 is shown in Figure 12-1787 and described in Table 12-3522.
Return to Summary Table.
Status Register 1
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0504h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | STATUS_SYS_PCIE_PWR_STATE | STATUS_SYS_PCIE_LEGACY_3 | STATUS_SYS_PCIE_LEGACY_2 | ||||
R-0h | R-0h | R-0h | R-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
STATUS_SYS_PCIE_LEGACY_1 | STATUS_SYS_PCIE_LEGACY_0 | STATUS_SYS_PCIE_FLR_21 | STATUS_SYS_PCIE_FLR_20 | STATUS_SYS_PCIE_FLR_19 | STATUS_SYS_PCIE_FLR_18 | STATUS_SYS_PCIE_FLR_17 | STATUS_SYS_PCIE_FLR_16 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
STATUS_SYS_PCIE_FLR_15 | STATUS_SYS_PCIE_FLR_14 | STATUS_SYS_PCIE_FLR_13 | STATUS_SYS_PCIE_FLR_12 | STATUS_SYS_PCIE_FLR_11 | STATUS_SYS_PCIE_FLR_10 | STATUS_SYS_PCIE_FLR_9 | STATUS_SYS_PCIE_FLR_8 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATUS_SYS_PCIE_FLR_7 | STATUS_SYS_PCIE_FLR_6 | STATUS_SYS_PCIE_FLR_5 | STATUS_SYS_PCIE_FLR_4 | STATUS_SYS_PCIE_FLR_3 | STATUS_SYS_PCIE_FLR_2 | STATUS_SYS_PCIE_FLR_1 | STATUS_SYS_PCIE_FLR_0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | X | Reserved |
26 | STATUS_SYS_PCIE_PWR_STATE | R | 0h | Status for sys_en_pcie_pwr_state |
25 | STATUS_SYS_PCIE_LEGACY_3 | R | 0h | Status for sys_en_pcie_legacy_3 |
24 | STATUS_SYS_PCIE_LEGACY_2 | R | 0h | Status for sys_en_pcie_legacy_2 |
23 | STATUS_SYS_PCIE_LEGACY_1 | R | 0h | Status for sys_en_pcie_legacy_1 |
22 | STATUS_SYS_PCIE_LEGACY_0 | R | 0h | Status for sys_en_pcie_legacy_0 |
21 | STATUS_SYS_PCIE_FLR_21 | R | 0h | Status for sys_en_pcie_flr_21 |
20 | STATUS_SYS_PCIE_FLR_20 | R | 0h | Status for sys_en_pcie_flr_20 |
19 | STATUS_SYS_PCIE_FLR_19 | R | 0h | Status for sys_en_pcie_flr_19 |
18 | STATUS_SYS_PCIE_FLR_18 | R | 0h | Status for sys_en_pcie_flr_18 |
17 | STATUS_SYS_PCIE_FLR_17 | R | 0h | Status for sys_en_pcie_flr_17 |
16 | STATUS_SYS_PCIE_FLR_16 | R | 0h | Status for sys_en_pcie_flr_16 |
15 | STATUS_SYS_PCIE_FLR_15 | R | 0h | Status for sys_en_pcie_flr_15 |
14 | STATUS_SYS_PCIE_FLR_14 | R | 0h | Status for sys_en_pcie_flr_14 |
13 | STATUS_SYS_PCIE_FLR_13 | R | 0h | Status for sys_en_pcie_flr_13 |
12 | STATUS_SYS_PCIE_FLR_12 | R | 0h | Status for sys_en_pcie_flr_12 |
11 | STATUS_SYS_PCIE_FLR_11 | R | 0h | Status for sys_en_pcie_flr_11 |
10 | STATUS_SYS_PCIE_FLR_10 | R | 0h | Status for sys_en_pcie_flr_10 |
9 | STATUS_SYS_PCIE_FLR_9 | R | 0h | Status for sys_en_pcie_flr_9 |
8 | STATUS_SYS_PCIE_FLR_8 | R | 0h | Status for sys_en_pcie_flr_8 |
7 | STATUS_SYS_PCIE_FLR_7 | R | 0h | Status for sys_en_pcie_flr_7 |
6 | STATUS_SYS_PCIE_FLR_6 | R | 0h | Status for sys_en_pcie_flr_6 |
5 | STATUS_SYS_PCIE_FLR_5 | R | 0h | Status for sys_en_pcie_flr_5 |
4 | STATUS_SYS_PCIE_FLR_4 | R | 0h | Status for sys_en_pcie_flr_4 |
3 | STATUS_SYS_PCIE_FLR_3 | R | 0h | Status for sys_en_pcie_flr_3 |
2 | STATUS_SYS_PCIE_FLR_2 | R | 0h | Status for sys_en_pcie_flr_2 |
1 | STATUS_SYS_PCIE_FLR_1 | R | 0h | Status for sys_en_pcie_flr_1 |
0 | STATUS_SYS_PCIE_FLR_0 | R | 0h | Status for sys_en_pcie_flr_0 |
PCIE_INTD_STATUS_REG_SYS_2 is shown in Figure 12-1788 and described in Table 12-3524.
Return to Summary Table.
Status Register 2
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0508h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | STATUS_SYS_PCIE_PTM | STATUS_SYS_PCIE_LINK_STATE | STATUS_SYS_PCIE_HOT_RESET | STATUS_SYS_PCIE_ERROR_2 | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATUS_SYS_PCIE_ERROR_1 | STATUS_SYS_PCIE_ERROR_0 | STATUS_SYS_PCIE_DPA_5 | STATUS_SYS_PCIE_DPA_4 | STATUS_SYS_PCIE_DPA_3 | STATUS_SYS_PCIE_DPA_2 | STATUS_SYS_PCIE_DPA_1 | STATUS_SYS_PCIE_DPA_0 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | X | Reserved |
11 | STATUS_SYS_PCIE_PTM | R/W1S | 0h | Status ,write 1 to set, for sys_en_pcie_ptm |
10 | STATUS_SYS_PCIE_LINK_STATE | R/W1S | 0h | Status ,write 1 to set, for sys_en_pcie_link_state |
9 | STATUS_SYS_PCIE_HOT_RESET | R/W1S | 0h | Status ,write 1 to set, for sys_en_pcie_hot_reset |
8 | STATUS_SYS_PCIE_ERROR_2 | R/W1S | 0h | Status ,write 1 to set, for sys_en_pcie_error_2 |
7 | STATUS_SYS_PCIE_ERROR_1 | R/W1S | 0h | Status ,write 1 to set, for sys_en_pcie_error_1 |
6 | STATUS_SYS_PCIE_ERROR_0 | R/W1S | 0h | Status ,write 1 to set, for sys_en_pcie_error_0 |
5 | STATUS_SYS_PCIE_DPA_5 | R/W1S | 0h | Status ,write 1 to set, for sys_en_pcie_dpa_5 |
4 | STATUS_SYS_PCIE_DPA_4 | R/W1S | 0h | Status ,write 1 to set, for sys_en_pcie_dpa_4 |
3 | STATUS_SYS_PCIE_DPA_3 | R/W1S | 0h | Status ,write 1 to set, for sys_en_pcie_dpa_3 |
2 | STATUS_SYS_PCIE_DPA_2 | R/W1S | 0h | Status ,write 1 to set, for sys_en_pcie_dpa_2 |
1 | STATUS_SYS_PCIE_DPA_1 | R/W1S | 0h | Status ,write 1 to set, for sys_en_pcie_dpa_1 |
0 | STATUS_SYS_PCIE_DPA_0 | R/W1S | 0h | Status ,write 1 to set, for sys_en_pcie_dpa_0 |
PCIE_INTD_STATUS_CLR_REG_SYS_2 is shown in Figure 12-1789 and described in Table 12-3526.
Return to Summary Table.
Status Clear Register 2
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0708h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | STATUS_SYS_PCIE_PTM_CLR | STATUS_SYS_PCIE_LINK_STATE_CLR | STATUS_SYS_PCIE_HOT_RESET_CLR | STATUS_SYS_PCIE_ERROR_2_CLR | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATUS_SYS_PCIE_ERROR_1_CLR | STATUS_SYS_PCIE_ERROR_0_CLR | STATUS_SYS_PCIE_DPA_5_CLR | STATUS_SYS_PCIE_DPA_4_CLR | STATUS_SYS_PCIE_DPA_3_CLR | STATUS_SYS_PCIE_DPA_2_CLR | STATUS_SYS_PCIE_DPA_1_CLR | STATUS_SYS_PCIE_DPA_0_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | X | Reserved |
11 | STATUS_SYS_PCIE_PTM_CLR | R/W1C | 0h | Status ,write 1 to clear, for sys_en_pcie_ptm |
10 | STATUS_SYS_PCIE_LINK_STATE_CLR | R/W1C | 0h | Status ,write 1 to clear, for sys_en_pcie_link_state |
9 | STATUS_SYS_PCIE_HOT_RESET_CLR | R/W1C | 0h | Status ,write 1 to clear, for sys_en_pcie_hot_reset |
8 | STATUS_SYS_PCIE_ERROR_2_CLR | R/W1C | 0h | Status ,write 1 to clear, for sys_en_pcie_error_2 |
7 | STATUS_SYS_PCIE_ERROR_1_CLR | R/W1C | 0h | Status ,write 1 to clear, for sys_en_pcie_error_1 |
6 | STATUS_SYS_PCIE_ERROR_0_CLR | R/W1C | 0h | Status ,write 1 to clear, for sys_en_pcie_error_0 |
5 | STATUS_SYS_PCIE_DPA_5_CLR | R/W1C | 0h | Status ,write 1 to clear, for sys_en_pcie_dpa_5 |
4 | STATUS_SYS_PCIE_DPA_4_CLR | R/W1C | 0h | Status ,write 1 to clear, for sys_en_pcie_dpa_4 |
3 | STATUS_SYS_PCIE_DPA_3_CLR | R/W1C | 0h | Status ,write 1 to clear, for sys_en_pcie_dpa_3 |
2 | STATUS_SYS_PCIE_DPA_2_CLR | R/W1C | 0h | Status ,write 1 to clear, for sys_en_pcie_dpa_2 |
1 | STATUS_SYS_PCIE_DPA_1_CLR | R/W1C | 0h | Status ,write 1 to clear, for sys_en_pcie_dpa_1 |
0 | STATUS_SYS_PCIE_DPA_0_CLR | R/W1C | 0h | Status ,write 1 to clear, for sys_en_pcie_dpa_0 |
PCIE_INTD_INTR_VECTOR_REG_SYS is shown in Figure 12-1790 and described in Table 12-3528.
Return to Summary Table.
Interrupt Vector for sys
Instance | Physical Address |
---|---|
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG | 0291 0A80h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTR_VECTOR_SYS | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | INTR_VECTOR_SYS | R | 0h | Interrupt Vector |