SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-1793 lists the memory-mapped registers for the CPSW0_SGMII. All register offset addresses not listed in Table 12-1793 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0000h |
Offset | Acronym | Register Name | CPSW0_NUSS_SGMII Physical Address |
---|---|---|---|
100h + formula (1) | CPSW_SGMII_IDVER_REG_j | Identification and Version Register | 0C00 0100h + formula |
104h + formula | CPSW_SGMII_SOFT_RESET_REG_j | SGMII Software Reset Register | 0C00 0104h + formula |
110h + formula | CPSW_SGMII_CONTROL_REG_j | SGMII Control Register | 0C00 0110h + formula |
114h + formula | CPSW_SGMII_STATUS_REG_j | SGMII Status Register | 0C00 0114h + formula |
118h + formula | CPSW_SGMII_MR_ADV_ABILITY_REG_j | Advertised Ability Register | 0C00 0118h + formula |
11Ch + formula | CPSW_SGMII_MR_NP_TX_REG_j | Next Page Transmit Register | 0C00 011Ch + formula |
120h + formula | CPSW_SGMII_MR_LP_ADV_ABILITY_REG_j | Link Partner Advertised Ability Register | 0C00 0120h + formula |
124h + formula | CPSW_SGMII_MR_LP_NP_RX_REG_j | Link Partner Next Page Received Register | 0C00 0124h + formula |
130h + formula | CPSW_SGMII_TX_CFG_REG_j | SGMII Transmit Config Register | 0C00 0130h + formula |
134h + formula | CPSW_SGMII_RX_CFG_REG_j | SGMII Receive Config Register | 0C00 0134h + formula |
138h + formula | CPSW_SGMII_AUX_CFG_REG_j | SGMII Auxiliary Configuration Register | 0C00 0138h + formula |
140h + formula | CPSW_SGMII_DIAG_CLEAR_REG_j | Diagnostics Clear Register | 0C00 0140h + formula |
144h + formula | CPSW_SGMII_DIAG_CONTROL_REG_j | Diagnostics Control Register | 0C00 0144h + formula |
148h + formula | CPSW_SGMII_DIAG_STATUS_REG_j | Diagnostics Status Register | 0C00 0148h + formula |
CPSW_SGMII_IDVER_REG_j is shown in Figure 12-937 and described in Table 12-1795.
Return to Summary Table.
SGMII IDVER register.
Offset = 100h + (j * 100h); where j = 0h to 7h.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0100h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TX_IDENT | |||||||||||||||
R-4EC2h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL_VER | MAJOR_VER | MINOR_VER | |||||||||||||
R-2h | R-1h | R-2h | |||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | TX_IDENT | R | 4EC2h | MODULE value |
15-11 | RTL_VER | R | 2h | RTL version value |
10-8 | MAJOR_VER | R | 1h | Major version value |
7-0 | MINOR_VER | R | 2h | Minor version value |
CPSW_SGMII_SOFT_RESET_REG_j is shown in Figure 12-938 and described in Table 12-1797.
Return to Summary Table.
SGMII Soft Reset Register.
Offset = 104h + (j * 100h); where j = 0h to 7h.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0104h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RT_SOFT_RESET | SOFT_RESET | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | RT_SOFT_RESET | R/W | 0h | Transmit and Receive Software Reset. This bit is intended to be used when changing between loopback mode and normal mode of operation. |
0 | SOFT_RESET | R/W | 0h | Software Reset. |
CPSW_SGMII_CONTROL_REG_j is shown in Figure 12-939 and described in Table 12-1799.
Return to Summary Table.
SGMII Control Register
Offset = 110h + (j * 100h); where j = 0h to 7h.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0110h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TEST_PATTERN_EN | MASTER | LOOPBACK | MR_NP_LOADED | FAST_LINK_TIMER | MR_AN_RESTART | MR_AN_ENABLE |
R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R/W | X | |
6 | TEST_PATTERN_EN | R/W | 0h | Test Pattern Enable. |
5 | MASTER | R/W | 0h | Master Mode. |
4 | LOOPBACK | R/W | 0h | Loopback mode. |
3 | MR_NP_LOADED | R/W | 0h | Next Page Loaded. |
2 | FAST_LINK_TIMER | R/W | 0h | Fast Link Timer. |
1 | MR_AN_RESTART | R/W | 0h | Auto Negotiation Restart. |
0 | MR_AN_ENABLE | R/W | 0h | Auto Negotiation Enable. |
CPSW_SGMII_STATUS_REG_j is shown in Figure 12-940 and described in Table 12-1801.
Return to Summary Table.
SGMII Status Register
Offset = 114h + (j * 100h); where j = 0h to 7h.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0114h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FIB_SIG_DETECT | LOCK | MR_PAGE_RX | MR_AN_COMPLETE | AN_ERROR | LINK | |
R-X | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | X | |
5 | FIB_SIG_DETECT | R | 0h | Fiber Signal Detect. |
4 | LOCK | R | 0h | Lock. |
3 | MR_PAGE_RX | R | 0h | Next Page Received. |
2 | MR_AN_COMPLETE | R | 0h | Auto negotiation complete. |
1 | AN_ERROR | R | 0h | Auto negotiation error. |
0 | LINK | R | 0h | Link indicator. |
CPSW_SGMII_MR_ADV_ABILITY_REG_j is shown in Figure 12-941 and described in Table 12-1803.
Return to Summary Table.
SGMII MR Advertized Ability Register.
Offset = 118h + (j * 100h); where j = 0h to 7h.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0118h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MR_ADV_ABILITY | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | MR_ADV_ABILITY | R/W | 0h | Advertised Ability. |
CPSW_SGMII_MR_NP_TX_REG_j is shown in Figure 12-942 and described in Table 12-1805.
Return to Summary Table.
SGMII Next Pate Transmit Register.
Offset = 11Ch + (j * 100h); where j = 0h to 7h.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 011Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MR_NP_TX | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | MR_NP_TX | R/W | 0h | Next Page Transmit. |
CPSW_SGMII_MR_LP_ADV_ABILITY_REG_j is shown in Figure 12-943 and described in Table 12-1807.
Return to Summary Table.
SGMII Link Partner Advertized Ability Register.
Offset = 120h + (j * 100h); where j = 0h to 7h.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0120h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MR_LP_ADV_ABILITY | |||||||||||||||
R-0h | |||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | MR_LP_ADV_ABILITY | R | 0h | Link Partner Advertised Ability. |
CPSW_SGMII_MR_LP_NP_RX_REG_j is shown in Figure 12-944 and described in Table 12-1809.
Return to Summary Table.
SGMII Link Partner Next Page Receive Register
Offset = 124h + (j * 100h); where j = 0h to 7h.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0124h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MR_LP_NP_RX | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | MR_LP_NP_RX | R | 0h | Link Partner Next Page Received. |
CPSW_SGMII_TX_CFG_REG_j is shown in Figure 12-945 and described in Table 12-1811.
Return to Summary Table.
SGMII Transmit Configuration Register
Offset = 130h + (j * 100h); where j = 0h to 7h.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0130h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_CFG | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TX_CFG | R/W | 0h | Transmit configuration register output |
CPSW_SGMII_RX_CFG_REG_j is shown in Figure 12-946 and described in Table 12-1813.
Return to Summary Table.
SGMII Receive Configuration Register
Offset = 134h + (j * 100h); where j = 0h to 7h.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0134h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_CFG | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_CFG | R/W | 0h | Receive configuration register output |
CPSW_SGMII_AUX_CFG_REG_j is shown in Figure 12-947 and described in Table 12-1815.
Return to Summary Table.
SGMII Auxiliary Configuration Register.
Offset = 138h + (j * 100h); where j = 0h to 7h.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0138h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUX_CFG | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | AUX_CFG | R/W | 0h | Auxiliary configuration register output |
CPSW_SGMII_DIAG_CLEAR_REG_j is shown in Figure 12-948 and described in Table 12-1817.
Return to Summary Table.
SGMII Diagnostics Clear Register
Offset = 140h + (j * 100h); where j = 0h to 7h
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0140h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIAG_CLEAR | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | DIAG_CLEAR | R/W | 0h | Diagnostics Clear. |
CPSW_SGMII_DIAG_CONTROL_REG_j is shown in Figure 12-949 and described in Table 12-1819.
Return to Summary Table.
SGMII Diagnostics Control Register
Offset = 144h + (j * 100h); where j = 0h to 7h.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0144h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIAG_SM_SEL | RESERVED | DIAG_EDGE_SEL | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R/W | X | |
6-4 | DIAG_SM_SEL | R/W | 0h | Diagnostic Select. |
3-2 | RESERVED | R/W | X | |
1-0 | DIAG_EDGE_SEL | R/W | 0h | Diagnostis Hold Signals Edge Select |
CPSW_SGMII_DIAG_STATUS_REG_j is shown in Figure 12-950 and described in Table 12-1821.
Return to Summary Table.
SGMII Diagnostics Status Register
Offset = 148h + (j * 100h); where j = 0h to 7h.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SGMII | 0C00 0148h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIAG_STATUS | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | DIAG_STATUS | R | 0h | Diagnostics status. |