SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes the A72SS integration in the device, including information about clocks, resets, and hardware requests.
Figure 6-16 shows the A72SS integration.
Table 6-36 through Table 6-38 summarize the A72SS integration.
Module Instance | Attributes | ||||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | ||
A72SS0 | A72 cluster | PSC0 | PD14 | LPSC78 | CBASS0(1) |
A72SS0_CORE0 | PSC0 | PD15 | LPSC80 | CBASS0(1) | |
A72SS0_CORE1 | PSC0 | PD16 | LPSC81 | CBASS0(1) |
Clocks | |||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description | |
A72SS0 | A72SS0_CLK | MAIN_PLL8_HSDIV0_CLKOUT | PLL8 | A72SS0 clock | |
Resets | |||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description | |
A72SS0 | A72 cluster | A72SS0_RST | MOD_G_RST | LPSC78 | A72 cluster reset |
A72SS0_CORE0 | A72SS0_CORE0_RST | MOD_G_RST | LPSC80 | A72SS0_CORE0 reset | |
A72SS0_CORE1 | A72SS0_CORE1_RST | MOD_G_RST | LPSC81 | A72SS0_CORE1 reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
A72SS0 | A72SS0_COMMIRQ0_0 | GIC500_PPI0_0_IN_22 | COMPUTE_CLUSTER0 | A72SS0_CORE0 DCC comms channel interrupt | Level |
A72SS0_PMUIRQ0_0 | GIC500_PPI0_0_IN_23 | COMPUTE_CLUSTER0 | A72SS0_CORE0 PMU counter overflow interrupt | Level | |
A72SS0_CTIIRQ0_0 | GIC500_PPI0_0_IN_24 | COMPUTE_CLUSTER0 | A72SS0_CORE0 cross trigger interface interrupt | Level | |
A72SS0_VCPUMNTIRQ0_0 | GIC500_PPI0_0_IN_25 | COMPUTE_CLUSTER0 | A72SS0_CORE0 virtual CPU maintenance interrupt | Level | |
A72SS0_CNTHPIRQ0_0 | GIC500_PPI0_0_IN_26 | COMPUTE_CLUSTER0 | A72SS0_CORE0 hypervisor timer interrupt | Level | |
A72SS0_CNTVIRQ0_0 | GIC500_PPI0_0_IN_27 | COMPUTE_CLUSTER0 | A72SS0_CORE0 virtual timer interrupt | Level | |
A72SS0_CNTPSIRQ0_0 | GIC500_PPI0_0_IN_29 | COMPUTE_CLUSTER0 | A72SS0_CORE0 secure physical timer interrupt | Level | |
A72SS0_CNTPNSIRQ0_0 | GIC500_PPI0_0_IN_30 | COMPUTE_CLUSTER0 | A72SS0_CORE0 non-secure physical timer interrupt | Level | |
A72SS0_COMMIRQ1_0 | GIC500_PPI0_1_IN_22 | COMPUTE_CLUSTER0 | A72SS0_CORE1 DCC comms channel interrupt | Level | |
A72SS0_PMUIRQ1_0 | GIC500_PPI0_1_IN_23 | COMPUTE_CLUSTER0 | A72SS0_CORE1 PMU counter overflow interrupt | Level | |
A72SS0_CTIIRQ1_0 | GIC500_PPI0_1_IN_24 | COMPUTE_CLUSTER0 | A72SS0_CORE1 cross trigger interface interrupt | Level | |
A72SS0_VCPUMNTIRQ1_0 | GIC500_PPI0_1_IN_25 | COMPUTE_CLUSTER0 | A72SS0_CORE1 virtual CPU maintenance interrupt | Level | |
A72SS0_CNTHPIRQ1_0 | GIC500_PPI0_1_IN_26 | COMPUTE_CLUSTER0 | A72SS0_CORE1 hypervisor timer interrupt | Level | |
A72SS0_CNTVIRQ1_0 | GIC500_PPI0_1_IN_27 | COMPUTE_CLUSTER0 | A72SS0_CORE1 virtual timer interrupt | Level | |
A72SS0_CNTPSIRQ1_0 | GIC500_PPI0_1_IN_29 | COMPUTE_CLUSTER0 | A72SS0_CORE1 secure physical timer interrupt | Level | |
A72SS0_CNTPNSIRQ1_0 | GIC500_PPI0_1_IN_30 | COMPUTE_CLUSTER0 | A72SS0_CORE1 non-secure physical timer interrupt | Level | |
A72SS0_INTERRIRQ_0 | ESM0_LVL_IN_40 | ESM0 | A72 cluster cache ECC error interrupt | Level | |
A72SS0_EXTERRIRQ_0 | ESM0_LVL_IN_41 | ESM0 | A72 cluster memory bus error interrupt | Level |