SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes module integration in the device, including information about clocks, resets, and hardware requests.
This section describes the MCRC integration in the main Navigator subsystem (NAVSS0). For MCU_NAVSS0_MCRC0 integration, please see MCU Navigator Subsystem (MCU_NAVSS).
Figure 12-2980 shows the MCRC integration.
Table 12-5702 and Table 12-5703 summarize the integration of the module in the device.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
NAVSS0_MCRC0 | PSC0 | GP | LPSC0 | MODSS_CBASS |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
NAVSS0_MCRC0 | MCRC0_FICLK | MODSS_VBUS_D2_CLK | MAIN_SYSCLK0 | MCRC0 clock. This clock is used for all interface and functional operations. |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
NAVSS0_MCRC0 | MCRC0_RST | MODSS_RST | LPSC0 | MCRC0 hardware reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
NAVSS0_MCRC0 | INT_MCRC_INTR | IN_INTR[388] | INTR_ROUTER0 | MCRC Interrupt signal | Level |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
NAVSS0_MCRC0 | DMA_EVENT_INTR0 | IN_INTR[384] | INTR_ROUTER0 | MCRC DMA event for channel 1 | Pulse |
INTAGGR_LEVI_PEND[0] | UDMASS_INTR_AGGR0 | ||||
DMA_EVENT_INTR1 | IN_INTR[385] | INTR_ROUTER0 | MCRC DMA event for channel 2 | Pulse | |
INTAGGR_LEVI_PEND[1] | UDMASS_INTR_AGGR0 | ||||
DMA_EVENT_INTR2 | IN_INTR[386] | INTR_ROUTER0 | MCRC DMA event for channel 3 | Pulse | |
INTAGGR_LEVI_PEND[2] | UDMASS_INTR_AGGR0 | ||||
DMA_EVENT_INTR3 | IN_INTR[387] | INTR_ROUTER0 | MCRC DMA event for channel 4 | Pulse | |
INTAGGR_LEVI_PEND[3] | UDMASS_INTR_AGGR0 |
If DMA_EVENT_INTR[0-3] needs to be converted to level interrupts, then UDMASS_INTR_AGGR0 can be used to generate events to the PSILSS. PSILSS would route events back to the interrupt aggregator to be turned into level output interrupts.