SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There are eight MCSPI modules integrated in the device MAIN domain - MCSPI0 through MCSPI7. Figure 12-329 shows their integration in the device.
Table 12-615 through Table 12-617 summarize the integration of MCSPI0 through MCSPI7 in device MAIN domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
MCSPI0 | PSC0 | PD2 | LPSC52 | CBASS0 |
MCSPI1 | PSC0 | PD2 | LPSC52 | CBASS0 |
MCSPI2 | PSC0 | PD2 | LPSC52 | CBASS0 |
MCSPI3 | PSC0 | PD2 | LPSC52 | CBASS0 |
MCSPI4 | PSC0 | PD2 | LPSC53 | CBASS0 |
MCSPI5 | PSC0 | PD2 | LPSC53 | CBASS0 |
MCSPI6 | PSC0 | PD2 | LPSC53 | CBASS0 |
MCSPI7 | PSC0 | PD2 | LPSC53 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
MCSPI0 | MCSPI0_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | MCSPI0 Interface Clock |
MCSPI0_FCLK | MAIN_PLL0_HSDIV5_CLKOUT | PLL0_HSDIV | MCSPI0 Functional Clock | |
MCSPI1 | MCSPI1_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | MCSPI1 Interface Clock |
MCSPI1_FCLK | MAIN_PLL0_HSDIV5_CLKOUT | PLL0_HSDIV | MCSPI1 Functional Clock | |
MCSPI2 | MCSPI2_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | MCSPI2 Interface Clock |
MCSPI2_FCLK | MAIN_PLL0_HSDIV5_CLKOUT | PLL0_HSDIV | MCSPI2 Functional Clock | |
MCSPI3 | MCSPI3_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | MCSPI3 Interface Clock |
MCSPI3_FCLK | MAIN_PLL0_HSDIV5_CLKOUT | PLL0_HSDIV | MCSPI3 Functional Clock | |
MCSPI4 | MCSPI4_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | MCSPI4 Interface Clock |
MCSPI4_FCLK | MAIN_PLL0_HSDIV5_CLKOUT | PLL0_HSDIV | MCSPI4 Functional Clock | |
MCSPI5 | MCSPI5_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | MCSPI5 Interface Clock |
MCSPI5_FCLK | MAIN_PLL0_HSDIV5_CLKOUT | PLL0_HSDIV | MCSPI5 Functional Clock | |
MCSPI6 | MCSPI6_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | MCSPI6 Interface Clock |
MCSPI6_FCLK | MAIN_PLL0_HSDIV5_CLKOUT | PLL0_HSDIV | MCSPI6 Functional Clock | |
MCSPI7 | MCSPI7_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | MCSPI7 Interface Clock |
MCSPI7_FCLK | MAIN_PLL0_HSDIV5_CLKOUT | PLL0_HSDIV | MCSPI7 Functional Clock | |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
MCSPI0 | MCSPI0_RST | MOD_G_RST | LPSC52 | MCSPI0 Asynchronous Reset |
MCSPI0_POR_RST | MOD_POR_RST | LPSC52 | MCSPI0 Power-On Reset | |
MCSPI1 | MCSPI1_RST | MOD_G_RST | LPSC52 | MCSPI1 Asynchronous Reset |
MCSPI1_POR_RST | MOD_POR_RST | LPSC52 | MCSPI1 Power-On Reset | |
MCSPI2 | MCSPI2_RST | MOD_G_RST | LPSC52 | MCSPI2 Asynchronous Reset |
MCSPI3_POR_RST | MOD_POR_RST | LPSC52 | MCSPI2 Power-On Reset | |
MCSPI3 | MCSPI3_RST | MOD_G_RST | LPSC52 | MCSPI3 Asynchronous Reset |
MCSPI3_POR_RST | MOD_POR_RST | LPSC52 | MCSPI3 Power-On Reset | |
MCSPI4 | MCSPI4_RST | MOD_G_RST | LPSC53 | MCSPI4 Asynchronous Reset |
MCSPI4_POR_RST | MOD_POR_RST | LPSC53 | MCSPI4 Power-On Reset | |
MCSPI5 | MCSPI5_RST | MOD_G_RST | LPSC53 | MCSPI5 Asynchronous Reset |
MCSPI5_POR_RST | MOD_POR_RST | LPSC53 | MCSPI5 Power-On Reset | |
MCSPI6 | MCSPI6_RST | MOD_G_RST | LPSC53 | MCSPI6 Asynchronous Reset |
MCSPI6_POR_RST | MOD_POR_RST | LPSC53 | MCSPI6 Power-On Reset | |
MCSPI7 | MCSPI7_RST | MOD_G_RST | LPSC53 | MCSPI7 Asynchronous Reset |
MCSPI7_POR_RST | MOD_POR_RST | LPSC53 | MCSPI7 Power-On Reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
MCSPI0 | MCSPI0_INTR_SPI_0 | GIC500_SPI_IN_216 | COMPUTE_CLUSTER0 | MCSPI0 Interrupt Request | Level |
MAIN2MCU_LVL_INTRTR0_IN_48 | MAIN2MCU_LVL_INTRTR0 | MCSPI0 Interrupt Request | Level | ||
R5FSS0_CORE0_INTR_IN_152 | R5FSS0_CORE0 | MCSPI0 Interrupt Request | Level | ||
R5FSS0_CORE1_INTR_IN_152 | R5FSS0_CORE1 | MCSPI0 Interrupt Request | Level | ||
MCSPI1 | MCSPI1_INTR_SPI_0 | GIC500_SPI_IN_217 | COMPUTE_CLUSTER0 | MCSPI1 Interrupt Request | Level |
MAIN2MCU_LVL_INTRTR0_IN_49 | MAIN2MCU_LVL_INTRTR0 | MCSPI1 Interrupt Request | Level | ||
R5FSS0_CORE0_INTR_IN_153 | R5FSS0_CORE0 | MCSPI1 Interrupt Request | Level | ||
R5FSS0_CORE1_INTR_IN_153 | R5FSS0_CORE1 | MCSPI1 Interrupt Request | Level | ||
MCSPI2 | MCSPI2_INTR_SPI_0 | GIC500_SPI_IN_218 | COMPUTE_CLUSTER0 | MCSPI2 Interrupt Request | Level |
MAIN2MCU_LVL_INTRTR0_IN_50 | MAIN2MCU_LVL_INTRTR0 | MCSPI2 Interrupt Request | Level | ||
R5FSS0_CORE0_INTR_IN_268 | R5FSS0_CORE0 | MCSPI2 Interrupt Request | Level | ||
R5FSS0_CORE1_INTR_IN_268 | R5FSS0_CORE1 | MCSPI2 Interrupt Request | Level | ||
MCSPI3 | MCSPI3_INTR_SPI_0 | GIC500_SPI_IN_219 | COMPUTE_CLUSTER0 | MCSPI3 Interrupt Request | Level |
MAIN2MCU_LVL_INTRTR0_IN_51 | MAIN2MCU_LVL_INTRTR0 | MCSPI3 Interrupt Request | Level | ||
R5FSS0_CORE0_INTR_IN_269 | R5FSS0_CORE0 | MCSPI3 Interrupt Request | Level | ||
R5FSS0_CORE1_INTR_IN_269 | R5FSS0_CORE1 | MCSPI3 Interrupt Request | Level | ||
MCSPI4 | MCSPI4_INTR_SPI_0 | GIC500_SPI_IN_220 | COMPUTE_CLUSTER0 | MCSPI4 Interrupt Request | Level |
MAIN2MCU_LVL_INTRTR0_IN_52 | MAIN2MCU_LVL_INTRTR0 | MCSPI4 Interrupt Request | Level | ||
R5FSS0_CORE0_INTR_IN_270 | R5FSS0_CORE0 | MCSPI4 Interrupt Request | Level | ||
R5FSS0_CORE1_INTR_IN_270 | R5FSS0_CORE1 | MCSPI4 Interrupt Request | Level | ||
MCSPI5 | MCSPI5_INTR_SPI_0 | GIC500_SPI_IN_221 | COMPUTE_CLUSTER0 | MCSPI5 Interrupt Request | Level |
MAIN2MCU_LVL_INTRTR0_IN_53 | MAIN2MCU_LVL_INTRTR0 | MCSPI5 Interrupt Request | Level | ||
R5FSS0_CORE0_INTR_IN_271 | R5FSS0_CORE0 | MCSPI5 Interrupt Request | Level | ||
R5FSS0_CORE1_INTR_IN_271 | R5FSS0_CORE1 | MCSPI5 Interrupt Request | Level | ||
MCSPI6 | MCSPI6_INTR_SPI_0 | GIC500_SPI_IN_222 | COMPUTE_CLUSTER0 | MCSPI6 Interrupt Request | Level |
MAIN2MCU_LVL_INTRTR0_IN_54 | MAIN2MCU_LVL_INTRTR0 | MCSPI6 Interrupt Request | Level | ||
R5FSS0_CORE0_INTR_IN_272 | R5FSS0_CORE0 | MCSPI6 Interrupt Request | Level | ||
R5FSS0_CORE1_INTR_IN_272 | R5FSS0_CORE1 | MCSPI6 Interrupt Request | Level | ||
MCSPI7 | MCSPI7_INTR_SPI_0 | GIC500_SPI_IN_223 | COMPUTE_CLUSTER0 | MCSPI7 Interrupt Request | Level |
MAIN2MCU_LVL_INTRTR0_IN_55 | MAIN2MCU_LVL_INTRTR0 | MCSPI7 Interrupt Request | Level | ||
R5FSS0_CORE0_INTR_IN_273 | R5FSS0_CORE0 | MCSPI7 Interrupt Request | Level | ||
R5FSS0_CORE1_INTR_IN_273 | R5FSS0_CORE1 | MCSPI7 Interrupt Request | Level | ||
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
MCSPI0 | MCSPI0_DMA_WRITE_EVENT0 | MCSPI0_TX0 | PDMA9 - PDMA_SPI_G0 | MCSPI0 Channel 0 Transmit (Write) Request Line | Pulse |
MCSPI0_DMA_READ_EVENT0 | MCSPI0_RX0 | PDMA9 - PDMA_SPI_G0 | MCSPI0 Channel 0 Receive (Read) Request Line | Pulse | |
MCSPI0_DMA_WRITE_EVENT1 | MCSPI0_TX1 | PDMA9 - PDMA_SPI_G0 | MCSPI0 Channel 1 Transmit (Write) Request Line | Pulse | |
MCSPI0_DMA_READ_EVENT1 | MCSPI0_RX1 | PDMA9 - PDMA_SPI_G0 | MCSPI0 Channel 1 Receive (Read) Request Line | Pulse | |
MCSPI0_DMA_WRITE_EVENT2 | MCSPI0_TX2 | PDMA9 - PDMA_SPI_G0 | MCSPI0 Channel 2 Transmit (Write) Request Line | Pulse | |
MCSPI0_DMA_READ_EVENT2 | MCSPI0_RX2 | PDMA9 - PDMA_SPI_G0 | MCSPI0 Channel 2 Receive (Read) Request Line | Pulse | |
MCSPI0_DMA_WRITE_EVENT3 | MCSPI0_TX3 | PDMA9 - PDMA_SPI_G0 | MCSPI0 Channel 3 Transmit (Write) Request Line | Pulse | |
MCSPI0_DMA_READ_EVENT3 | MCSPI0_RX3 | PDMA9 - PDMA_SPI_G0 | MCSPI0 Channel 3 Receive (Read) Request Line | Pulse | |
MCSPI1 | MCSPI1_DMA_WRITE_EVENT0 | MCSPI1_TX0 | PDMA9 - PDMA_SPI_G0 | MCSPI1 Channel 0 Transmit (Write) Request Line | Pulse |
MCSPI1_DMA_READ_EVENT0 | MCSPI1_RX0 | PDMA9 - PDMA_SPI_G0 | MCSPI1 Channel 0 Receive (Read) Request Line | Pulse | |
MCSPI1_DMA_WRITE_EVENT1 | MCSPI1_TX1 | PDMA9 - PDMA_SPI_G0 | MCSPI1 Channel 1 Transmit (Write) Request Line | Pulse | |
MCSPI1_DMA_READ_EVENT1 | MCSPI1_RX1 | PDMA9 - PDMA_SPI_G0 | MCSPI1 Channel 1 Receive (Read) Request Line | Pulse | |
MCSPI1_DMA_WRITE_EVENT2 | MCSPI1_TX2 | PDMA9 - PDMA_SPI_G0 | MCSPI1 Channel 2 Transmit (Write) Request Line | Pulse | |
MCSPI1_DMA_READ_EVENT2 | MCSPI1_RX2 | PDMA9 - PDMA_SPI_G0 | MCSPI1 Channel 2 Receive (Read) Request Line | Pulse | |
MCSPI1_DMA_WRITE_EVENT3 | MCSPI1_TX3 | PDMA9 - PDMA_SPI_G0 | MCSPI1 Channel 3 Transmit (Write) Request Line | Pulse | |
MCSPI1_DMA_READ_EVENT3 | MCSPI1_RX3 | PDMA9 - PDMA_SPI_G0 | MCSPI1 Channel 3 Receive (Read) Request Line | Pulse | |
MCSPI2 | MCSPI2_DMA_WRITE_EVENT0 | MCSPI2_TX0 | PDMA9 - PDMA_SPI_G0 | MCSPI2 Channel 0 Transmit (Write) Request Line | Pulse |
MCSPI2_DMA_READ_EVENT0 | MCSPI2_RX0 | PDMA9 - PDMA_SPI_G0 | MCSPI2 Channel 0 Receive (Read) Request Line | Pulse | |
MCSPI2_DMA_WRITE_EVENT1 | MCSPI2_TX1 | PDMA9 - PDMA_SPI_G0 | MCSPI2 Channel 1 Transmit (Write) Request Line | Pulse | |
MCSPI2_DMA_READ_EVENT1 | MCSPI2_RX1 | PDMA9 - PDMA_SPI_G0 | MCSPI2 Channel 1 Receive (Read) Request Line | Pulse | |
MCSPI2_DMA_WRITE_EVENT2 | MCSPI2_TX2 | PDMA9 - PDMA_SPI_G0 | MCSPI2 Channel 2 Transmit (Write) Request Line | Pulse | |
MCSPI2_DMA_READ_EVENT2 | MCSPI2_RX2 | PDMA9 - PDMA_SPI_G0 | MCSPI2 Channel 2 Receive (Read) Request Line | Pulse | |
MCSPI2_DMA_WRITE_EVENT3 | MCSPI2_TX3 | PDMA9 - PDMA_SPI_G0 | MCSPI2 Channel 3 Transmit (Write) Request Line | Pulse | |
MCSPI2_DMA_READ_EVENT3 | MCSPI2_RX3 | PDMA9 - PDMA_SPI_G0 | MCSPI2 Channel 3 Receive (Read) Request Line | Pulse | |
MCSPI3 | MCSPI3_DMA_WRITE_EVENT0 | MCSPI3_TX0 | PDMA9 - PDMA_SPI_G0 | MCSPI3 Channel 0 Transmit (Write) Request Line | Pulse |
MCSPI3_DMA_READ_EVENT0 | MCSPI3_RX0 | PDMA9 - PDMA_SPI_G0 | MCSPI3 Channel 0 Receive (Read) Request Line | Pulse | |
MCSPI3_DMA_WRITE_EVENT1 | MCSPI3_TX1 | PDMA9 - PDMA_SPI_G0 | MCSPI3 Channel 1 Transmit (Write) Request Line | Pulse | |
MCSPI3_DMA_READ_EVENT1 | MCSPI3_RX1 | PDMA9 - PDMA_SPI_G0 | MCSPI3 Channel 1 Receive (Read) Request Line | Pulse | |
MCSPI3_DMA_WRITE_EVENT2 | MCSPI3_TX2 | PDMA9 - PDMA_SPI_G0 | MCSPI3 Channel 2 Transmit (Write) Request Line | Pulse | |
MCSPI3_DMA_READ_EVENT2 | MCSPI3_RX2 | PDMA9 - PDMA_SPI_G0 | MCSPI3 Channel 2 Receive (Read) Request Line | Pulse | |
MCSPI3_DMA_WRITE_EVENT3 | MCSPI3_TX3 | PDMA9 - PDMA_SPI_G0 | MCSPI3 Channel 3 Transmit (Write) Request Line | Pulse | |
MCSPI3_DMA_READ_EVENT3 | MCSPI3_RX3 | PDMA9 - PDMA_SPI_G0 | MCSPI3 Channel 3 Receive (Read) Request Line | Pulse | |
MCSPI4 | MCSPI4_DMA_WRITE_EVENT0 | MCSPI4_TX0 | PDMA10 - PDMA_SPI_G1 | MCSPI4 Channel 0 Transmit (Write) Request Line | Pulse |
MCSPI4_DMA_READ_EVENT0 | MCSPI4_RX0 | PDMA10 - PDMA_SPI_G1 | MCSPI4 Channel 0 Receive (Read) Request Line | Pulse | |
MCSPI4_DMA_WRITE_EVENT1 | MCSPI4_TX1 | PDMA10 - PDMA_SPI_G1 | MCSPI4 Channel 1 Transmit (Write) Request Line | Pulse | |
MCSPI4_DMA_READ_EVENT1 | MCSPI4_RX1 | PDMA10 - PDMA_SPI_G1 | MCSPI4 Channel 1 Receive (Read) Request Line | Pulse | |
MCSPI4_DMA_WRITE_EVENT2 | MCSPI4_TX2 | PDMA10 - PDMA_SPI_G1 | MCSPI4 Channel 2 Transmit (Write) Request Line | Pulse | |
MCSPI4_DMA_READ_EVENT2 | MCSPI4_RX2 | PDMA10 - PDMA_SPI_G1 | MCSPI4 Channel 2 Receive (Read) Request Line | Pulse | |
MCSPI4_DMA_WRITE_EVENT3 | MCSPI4_TX3 | PDMA10 - PDMA_SPI_G1 | MCSPI4 Channel 3 Transmit (Write) Request Line | Pulse | |
MCSPI4_DMA_READ_EVENT3 | MCSPI4_RX3 | PDMA10 - PDMA_SPI_G1 | MCSPI4 Channel 3 Receive (Read) Request Line | Pulse | |
MCSPI5 | MCSPI5_DMA_WRITE_EVENT0 | MCSPI5_TX0 | PDMA10 - PDMA_SPI_G1 | MCSPI5 Channel 0 Transmit (Write) Request Line | Pulse |
MCSPI5_DMA_READ_EVENT0 | MCSPI5_RX0 | PDMA10 - PDMA_SPI_G1 | MCSPI5 Channel 0 Receive (Read) Request Line | Pulse | |
MCSPI5_DMA_WRITE_EVENT1 | MCSPI5_TX1 | PDMA10 - PDMA_SPI_G1 | MCSPI5 Channel 1 Transmit (Write) Request Line | Pulse | |
MCSPI5_DMA_READ_EVENT1 | MCSPI5_RX1 | PDMA10 - PDMA_SPI_G1 | MCSPI5 Channel 1 Receive (Read) Request Line | Pulse | |
MCSPI5_DMA_WRITE_EVENT2 | MCSPI5_TX2 | PDMA10 - PDMA_SPI_G1 | MCSPI5 Channel 2 Transmit (Write) Request Line | Pulse | |
MCSPI5_DMA_READ_EVENT2 | MCSPI5_RX2 | PDMA10 - PDMA_SPI_G1 | MCSPI5 Channel 2 Receive (Read) Request Line | Pulse | |
MCSPI5_DMA_WRITE_EVENT3 | MCSPI5_TX3 | PDMA10 - PDMA_SPI_G1 | MCSPI5 Channel 3 Transmit (Write) Request Line | Pulse | |
MCSPI5_DMA_READ_EVENT3 | MCSPI5_RX3 | PDMA10 - PDMA_SPI_G1 | MCSPI5 Channel 3 Receive (Read) Request Line | Pulse | |
MCSPI6 | MCSPI6_DMA_WRITE_EVENT0 | MCSPI6_TX0 | PDMA10 - PDMA_SPI_G1 | MCSPI6 Channel 0 Transmit (Write) Request Line | Pulse |
MCSPI6_DMA_READ_EVENT0 | MCSPI6_RX0 | PDMA10 - PDMA_SPI_G1 | MCSPI6 Channel 0 Receive (Read) Request Line | Pulse | |
MCSPI6_DMA_WRITE_EVENT1 | MCSPI6_TX1 | PDMA10 - PDMA_SPI_G1 | MCSPI6 Channel 1 Transmit (Write) Request Line | Pulse | |
MCSPI6_DMA_READ_EVENT1 | MCSPI6_RX1 | PDMA10 - PDMA_SPI_G1 | MCSPI6 Channel 1 Receive (Read) Request Line | Pulse | |
MCSPI6_DMA_WRITE_EVENT2 | MCSPI6_TX2 | PDMA10 - PDMA_SPI_G1 | MCSPI6 Channel 2 Transmit (Write) Request Line | Pulse | |
MCSPI6_DMA_READ_EVENT2 | MCSPI6_RX2 | PDMA10 - PDMA_SPI_G1 | MCSPI6 Channel 2 Receive (Read) Request Line | Pulse | |
MCSPI6_DMA_WRITE_EVENT3 | MCSPI6_TX3 | PDMA10 - PDMA_SPI_G1 | MCSPI6 Channel 3 Transmit (Write) Request Line | Pulse | |
MCSPI6_DMA_READ_EVENT3 | MCSPI6_RX3 | PDMA10 - PDMA_SPI_G1 | MCSPI6 Channel 3 Receive (Read) Request Line | Pulse | |
MCSPI7 | MCSPI7_DMA_WRITE_EVENT0 | MCSPI7_TX0 | PDMA10 - PDMA_SPI_G1 | MCSPI7 Channel 0 Transmit (Write) Request Line | Pulse |
MCSPI7_DMA_READ_EVENT0 | MCSPI7_RX0 | PDMA10 - PDMA_SPI_G1 | MCSPI7 Channel 0 Receive (Read) Request Line | Pulse | |
MCSPI7_DMA_WRITE_EVENT1 | MCSPI7_TX1 | PDMA10 - PDMA_SPI_G1 | MCSPI7 Channel 1 Transmit (Write) Request Line | Pulse | |
MCSPI7_DMA_READ_EVENT1 | MCSPI7_RX1 | PDMA10 - PDMA_SPI_G1 | MCSPI7 Channel 1 Receive (Read) Request Line | Pulse | |
MCSPI7_DMA_WRITE_EVENT2 | MCSPI7_TX2 | PDMA10 - PDMA_SPI_G1 | MCSPI7 Channel 2 Transmit (Write) Request Line | Pulse | |
MCSPI7_DMA_READ_EVENT2 | MCSPI7_RX2 | PDMA10 - PDMA_SPI_G1 | MCSPI7 Channel 2 Receive (Read) Request Line | Pulse | |
MCSPI7_DMA_WRITE_EVENT3 | MCSPI7_TX3 | PDMA10 - PDMA_SPI_G1 | MCSPI7 Channel 3 Transmit (Write) Request Line | Pulse | |
MCSPI7_DMA_READ_EVENT3 | MCSPI7_RX3 | PDMA10 - PDMA_SPI_G1 | MCSPI7 Channel 3 Receive (Read) Request Line | Pulse |