SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-3796 lists the memory-mapped registers for the PCIE_DAT1. All register offset addresses not listed in Table 12-3796 should be considered as reserved locations and the register contents should not be modified.
PCIE data region1
Instance | Base Address |
---|---|
PCIE1_DAT1 | 410000 0000h |
Offset | Acronym | Register Name | PCIE1_DAT1 Physical Address |
---|---|---|---|
0h + formula | PCIE_DATA_MEM_y | PCIe data region1 | 410000 0000h + formula |
PCIE_DATA_MEM_y is shown in Figure 12-1918 and described in Table 12-3798.
Return to Summary Table.
PCIE data region1
Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh
Instance | Physical Address |
---|---|
PCIE1_DAT1 | 410000 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCIE_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PCIE_DATA | R/W | 0h | PCIE data region1 |