SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-3458 lists the PCIE_CORE_EP_VF registers. All register offset addresses not listed in Table 12-3458 should be considered as reserved locations and the register contents should not be modified.
EP mode virtual function (VF) PCIE core registers. There are a total of 16 Virtual Functions, which may be assigned among the 6 Physical Functions.
Instance | Base Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 0000h |
Offset | Acronym | Register Name | PCIE1_CORE_DBN_CFG_PCIE_CORE Physical Address |
---|---|---|---|
6000h + formula | PCIE_CORE_VFm_I_VENDOR_ID_DEVICE_ID | 0D80 6000h + formula | |
6004h + formula | PCIE_CORE_VFm_I_COMMAND_STATUS | 0D80 6004h + formula | |
6008h + formula | PCIE_CORE_VFm_I_REVISION_ID_CLASS_CODE | 0D80 6008h + formula | |
600Ch + formula | PCIE_CORE_VFm_I_BIST_HEADER_LATENCY_CACHE_LINE | 0D80 600Ch + formula | |
6010h + formula | PCIE_CORE_VFm_I_BAR_0_REG | 0D80 6010h + formula | |
6014h + formula | PCIE_CORE_VFm_I_BAR_1_REG | 0D80 6014h + formula | |
6018h + formula | PCIE_CORE_VFm_I_BAR_2_REG | 0D80 6018h + formula | |
601Ch + formula | PCIE_CORE_VFm_I_BAR_3_REG | 0D80 601Ch + formula | |
6020h + formula | PCIE_CORE_VFm_I_BAR_4_REG | 0D80 6020h + formula | |
6024h + formula | PCIE_CORE_VFm_I_BAR_5_REG | 0D80 6024h + formula | |
6028h + formula | PCIE_CORE_VFm_RSVD_0A | 0D80 6028h + formula | |
602Ch + formula | PCIE_CORE_VFm_I_SUBSYSTEM_VENDOR_ID_SUBSYSTEM_I | 0D80 602Ch + formula | |
6030h + formula | PCIE_CORE_VFm_I_EXPANSN_ROM_BAR_REG | 0D80 6030h + formula | |
6034h + formula | PCIE_CORE_VFm_I_CAPABILITIES_POINTER | 0D80 6034h + formula | |
6038h + formula | PCIE_CORE_VFm_RSVD_0E | 0D80 6038h + formula | |
603Ch + formula | PCIE_CORE_VFm_I_INTRPT_LINE_INTRPT_PIN_REG | 0D80 603Ch + formula | |
6040h + formula | PCIE_CORE_VFm_RSVD_010_01F | 0D80 6040h + formula | |
6080h + formula | PCIE_CORE_VFm_I_PWR_MGMT_CAP | 0D80 6080h + formula | |
6084h + formula | PCIE_CORE_VFm_I_PWR_MGMT_CTRL_STAT_REP | 0D80 6084h + formula | |
6088h + formula | PCIE_CORE_VFm_RSVD_022_023 | 0D80 6088h + formula | |
6090h + formula | PCIE_CORE_VFm_I_MSI_CTRL_REG | 0D80 6090h + formula | |
6094h + formula | PCIE_CORE_VFm_I_MSI_MSG_LOW_ADDR | 0D80 6094h + formula | |
6098h + formula | PCIE_CORE_VFm_I_MSI_MSG_HI_ADDR | 0D80 6098h + formula | |
609Ch + formula | PCIE_CORE_VFm_I_MSI_MSG_DATA | 0D80 609Ch + formula | |
60A0h + formula | PCIE_CORE_VFm_I_MSI_MASK | 0D80 60A0h + formula | |
60A4h + formula | PCIE_CORE_VFm_I_MSI_PENDING_BITS | 0D80 60A4h + formula | |
60A8h + formula | PCIE_CORE_VFm_RSVD_02A_02B | 0D80 60A8h + formula | |
60B0h + formula | PCIE_CORE_VFm_I_MSIX_CTRL | 0D80 60B0h + formula | |
60B4h + formula | PCIE_CORE_VFm_I_MSIX_TBL_OFFSET | 0D80 60B4h + formula | |
60B8h + formula | PCIE_CORE_VFm_I_MSIX_PENDING_INTRPT | 0D80 60B8h + formula | |
60BCh + formula | PCIE_CORE_VFm_RSVD_02F | 0D80 60BCh + formula | |
60C0h + formula | PCIE_CORE_VFm_I_PCIE_CAP_LIST | 0D80 60C0h + formula | |
60C4h + formula | PCIE_CORE_VFm_I_PCIE_DEV_CAP | 0D80 60C4h + formula | |
60C8h + formula | PCIE_CORE_VFm_I_PCIE_DEV_CTRL_STATUS | 0D80 60C8h + formula | |
60CCh + formula | PCIE_CORE_VFm_I_LINK_CAP | 0D80 60CCh + formula | |
60D0h + formula | PCIE_CORE_VFm_RSVD_034_038 | 0D80 60D0h + formula | |
60E4h + formula | PCIE_CORE_VFm_I_PCIE_DEV_CAP_2 | 0D80 60E4h + formula | |
60E8h + formula | PCIE_CORE_VFm_RSVD_03A_03F | 0D80 60E8h + formula | |
6100h + formula | PCIE_CORE_VFm_I_AER_ENHANCED_CAP_HDR | 0D80 6100h + formula | |
6104h + formula | PCIE_CORE_VFm_I_UNCORR_ERR_STATUS | 0D80 6104h + formula | |
6108h + formula | PCIE_CORE_VFm_I_UNCORR_ERR_MASK | 0D80 6108h + formula | |
610Ch + formula | PCIE_CORE_VFm_I_UNCORR_ERR_SEVERITY | 0D80 610Ch + formula | |
6110h + formula | PCIE_CORE_VFm_I_CORR_ERR_STATUS | 0D80 6110h + formula | |
6114h + formula | PCIE_CORE_VFm_I_CORR_ERR_MASK | 0D80 6114h + formula | |
6118h + formula | PCIE_CORE_VFm_I_ADVCD_ERR_CAP_CTRL | 0D80 6118h + formula | |
611Ch + formula | PCIE_CORE_VFm_I_HDR_LOG_0 | 0D80 611Ch + formula | |
6120h + formula | PCIE_CORE_VFm_I_HDR_LOG_1 | 0D80 6120h + formula | |
6124h + formula | PCIE_CORE_VFm_I_HDR_LOG_2 | 0D80 6124h + formula | |
6128h + formula | PCIE_CORE_VFm_I_HDR_LOG_3 | 0D80 6128h + formula | |
612Ch + formula | PCIE_CORE_VFm_RSVD_04B_04D | 0D80 612Ch + formula | |
6138h + formula | PCIE_CORE_VFm_I_TLP_PRE_LOG_0 | 0D80 6138h + formula | |
6140h + formula | PCIE_CORE_VFm_I_ARI_EXT_CAP_HDR | 0D80 6140h + formula | |
6144h + formula | PCIE_CORE_VFm_I_ARI_CAP_AND_CTRL | 0D80 6144h + formula | |
6148h + formula | PCIE_CORE_VFm_RSVD_052_09C | 0D80 6148h + formula | |
65C0h + formula | PCIE_CORE_VFm_ATS_CAP_HEADER | 0D80 65C0h + formula | |
65C4h + formula | PCIE_CORE_VFm_ATS_CAP_CONTROL | 0D80 65C4h + formula |
PCIE_CORE_VFm_I_VENDOR_ID_DEVICE_ID is shown in Figure 12-1433 and described in Table 12-2806.
Return to the Summary Table.
Hardwired to all 1's
Offset = 6000h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DID | VID | ||||||||||||||||||||||||||||||
R-FFFFh | R-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | DID | R | FFFFh | Device ID assigned by the manufacturer of the device. On power-up, the core sets it to the value defined in the RTL file reg_defaults.h. This field can be written independently for each Function from the local management bus. |
15-0 | VID | R | FFFFh | A read to this register returns FFFFh for VFs |
PCIE_CORE_VFm_I_COMMAND_STATUS is shown in Figure 12-1434 and described in Table 12-2808.
Return to the Summary Table.
This location contains the 16-bit Command Register and the 16-bit Status Register
defined in PCI Specifications 3.0.
Offset = 6004h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6004h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DPE | SSE | RMA | RTA | STA | R5 | MDPE | |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R-0h | R/W1C-0h | |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
R4 | CL | IS | R3 | ||||
R-0h | R-1h | R-0h | R-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
R3 | IMD | R2 | SE | ||||
R-0h | R-0h | R-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R1 | PERE | R0 | BME | MSE | IOSE | ||
R-0h | R-0h | R-0h | R/W-0h | R-0h | R-0h | ||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | DPE | R/W1C | 0h | This bit is set when the core has received a Poisoned TLP targeted at this VF. The Parity Error Response enable bit [bit 6] in the PCI Command Register of the associated PF has no effect on the setting of this bit. STICKY. |
30 | SSE | R/W1C | 0h | If the SERR enable bit in the PCI Command Register of the associated Physical Function is 1, this bit is set when this VF has sent out a fatal or non-fatal error message on the link to the Root Complex. If the SERR enable bit is 0, this bit remains 0. This field can also be cleared from the local management bus by writing a 1 into this bit position. STICKY. |
29 | RMA | R/W1C | 0h | This bit is set when this VF has received a completion from the link with the Unsupported Request status. This field can also be cleared from the local management bus by writing a 1 into this bit position. STICKY. |
28 | RTA | R/W1C | 0h | This bit is set when this Virtual Function has received a completion from the link with the Completer Abort status. This field can also be cleared from the local management bus by writing a 1 into this bit position. STICKY. |
27 | STA | R/W1C | 0h | This bit is set when the core has sent a completion from this VF to the link with the Completer Abort status. This field can also be cleared from the local management bus by writing a 1 into this bit position. STICKY. |
26-25 | R5 | R | 0h | Reserved |
24 | MDPE | R/W1C | 0h | When the Parity Error Response enable bit in the PCI Command Register of the associated Physical Function is set, the core sets this bit when it detects the following error conditions: [i] The core receives a Poisoned Completion TLP from the link in response to a request from this VF. [ii] The core sends out a poisoned write request on the link from this VF. [This bit remains 0 when the Parity Error Response enable bit in the PCI Command Register of the associated Physical Function is 0]. This field can also be cleared from the local management bus by writing a 1 into this bit position. STICKY. |
23-21 | R4 | R | 0h | Reserved |
20 | CL | R | 1h | Indicates the presence of PCI Extended Capabilities registers. This bit is hardwired to 1. |
19 | IS | R | 0h | Reserved |
18-11 | R3 | R | 0h | Reserved |
10 | IMD | R | 0h | Reserved |
9 | R2 | R | 0h | Reserved |
8 | SE | R | 0h | Reserved |
7 | R1 | R | 0h | Reserved |
6 | PERE | R | 0h | Reserved |
5-3 | R0 | R | 0h | Reserved |
2 | BME | R/W | 0h | Enables the device to issue memory requests from this Function. This field can be written from the local management bus. |
1 | MSE | R | 0h | Reserved |
0 | IOSE | R | 0h | Reserved |
PCIE_CORE_VFm_I_REVISION_ID_CLASS_CODE is shown in Figure 12-1435 and described in Table 12-2810.
Return to the Summary Table.
This register contains the Revision ID and Class Code associated with the device
incorporating the PCIe core.
Offset = 6008h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6008h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CC | SCC | PIB | RID | ||||||||||||||||||||||||||||
R-0h | R-0h | R-0h | R-0h | ||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | CC | R | 0h | Identifies the function of the device. This field reflects the setting of the corresponding register in the configuration space of the associated Physical Function. |
23-16 | SCC | R | 0h | Identifies a sub-category within the selected function. This field reflects the setting of the corresponding register in the configuration space of the associated Physical Function. |
15-8 | PIB | R | 0h | Identifies the register set layout of the device. This field reflects the setting of the corresponding register in the configuration space of the associated Physical Function. |
7-0 | RID | R | 0h | Assigned by the manufacturer of the device to identify the revision number of the device. This field reflects the setting of the corresponding register in the configuration space of the associated Physical Function. |
PCIE_CORE_VFm_I_BIST_HEADER_LATENCY_CACHE_LINE is shown in Figure 12-1436 and described in Table 12-2812.
Return to the Summary Table.
This location contains the BIST, header-type, Latency Timer and Cache Line Size
Registers.
Offset = 600Ch + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 600Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BR | DT | HT | |||||||||||||
R-0h | R-0h | R-0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LT | CLS | ||||||||||||||
R-0h | R-0h | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | BR | R | 0h | Reserved |
23 | DT | R | 0h | Identifies whether the device supports a single Function or multiple Functions. This bit is read as 0 when only Function 0 has been enabled in the Physical Function Configuration Register [in the local management block]. Reserved for VFs |
22-16 | HT | R | 0h | Reserved |
15-8 | LT | R | 0h | Reserved |
7-0 | CLS | R | 0h | Reserved |
PCIE_CORE_VFm_I_BAR_0_REG is shown in Figure 12-1437 and described in Table 12-2814.
Return to the Summary Table.
Not Implemented
Offset = 6010h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6010h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NI | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NI | R | 0h | N/A |
PCIE_CORE_VFm_I_BAR_1_REG is shown in Figure 12-1438 and described in Table 12-2816.
Return to the Summary Table.
Not Implemented
Offset = 6014h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6014h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NI | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NI | R | 0h | N/A |
PCIE_CORE_VFm_I_BAR_2_REG is shown in Figure 12-1439 and described in Table 12-2818.
Return to the Summary Table.
Not Implemented
Offset = 6018h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6018h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NI | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NI | R | 0h | N/A |
PCIE_CORE_VFm_I_BAR_3_REG is shown in Figure 12-1440 and described in Table 12-2820.
Return to the Summary Table.
Not Implemented
Offset = 601Ch + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 601Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NI | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NI | R | 0h | N/A |
PCIE_CORE_VFm_I_BAR_4_REG is shown in Figure 12-1441 and described in Table 12-2822.
Return to the Summary Table.
Not Implemented
Offset = 6020h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6020h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NI | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NI | R | 0h | N/A |
PCIE_CORE_VFm_I_BAR_5_REG is shown in Figure 12-1442 and described in Table 12-2824.
Return to the Summary Table.
Not Implemented
Offset = 6024h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6024h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NI | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NI | R | 0h | N/A |
PCIE_CORE_VFm_RSVD_0A is shown in Figure 12-1443 and described in Table 12-2826.
Return to the Summary Table.
Reserved
Offset = 6028h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6028h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RSVD | R | 0h | Reserved |
PCIE_CORE_VFm_I_SUBSYSTEM_VENDOR_ID_SUBSYSTEM_I is shown in Figure 12-1444 and described in Table 12-2828.
Return to the Summary Table.
This register contains the Subsystem Vendor ID and Subsystem ID associated with the
device incorporating the PCIe core.
Offset = 602Ch + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 602Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SID | SVID | ||||||||||||||||||||||||||||||
R-0h | R-17CDh | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SID | R | 0h | Specifies the Subsystem ID assigned by the manufacturer of the device. This field reflects the setting of the corresponding register in the configuration space of the associated Physical Function. |
15-0 | SVID | R | 17CDh | Specifies the Subsystem Vendor ID assigned by the PCI SIG to the manufacturer of the device. Its value comes from the Subsystem Vendor ID Register in the local management register block. |
PCIE_CORE_VFm_I_EXPANSN_ROM_BAR_REG is shown in Figure 12-1445 and described in Table 12-2830.
Return to the Summary Table.
Not Implemented
Offset = 6030h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6030h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NI | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NI | R | 0h | N/A |
PCIE_CORE_VFm_I_CAPABILITIES_POINTER is shown in Figure 12-1446 and described in Table 12-2832.
Return to the Summary Table.
This location contains the pointer to the first PCI Capability Structure. Its default
value is defined in the RTL file reg_defaults.h.
Offset = 6034h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6034h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R6 | CP | ||||||||||||||||||||||||||||||
R-0h | R/W-80h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | R6 | R | 0h | Reserved |
7-0 | CP | R/W | 80h | Contains pointer to the first PCI Capability Structure. This field is set by default to point to the Power Management Capability Structure. It can be modified by writing to VF 0 from the local management bus, and the setting is common across all VFs. |
PCIE_CORE_VFm_RSVD_0E is shown in Figure 12-1447 and described in Table 12-2834.
Return to the Summary Table.
Reserved
Offset = 6038h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6038h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RSVD | R | 0h | Reserved |
PCIE_CORE_VFm_I_INTRPT_LINE_INTRPT_PIN_REG is shown in Figure 12-1448 and described in Table 12-2836.
Return to the Summary Table.
Not Implemented
Offset = 6003Ch + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 603Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NI | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NI | R | 0h | N/A |
PCIE_CORE_VFm_RSVD_010_01F is shown in Figure 12-1449 and described in Table 12-2838.
Return to the Summary Table.
Reserved
Offset = 6040h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6040h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RSVD | R | 0h | Reserved |
PCIE_CORE_VFm_I_PWR_MGMT_CAP is shown in Figure 12-1450 and described in Table 12-2840.
Return to the Summary Table.
This location contains the Power Management Capabilities Register, its Capability ID,
and a pointer to the next capability. This version of the core supports the PCI power states D0
,D1 and D3.
Offset = 6080h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6080h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PSDCS | PSDHS | PSD2S | PSD1S | PSD0S | D2S | D1S | MCRAPS |
R-0h | R/W-1h | R-0h | R/W-1h | R/W-1h | R-0h | R/W-1h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MCRAPS | DSI | R0 | PC | VID | |||
R-0h | R-0h | R-0h | R-0h | R/W-3h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CP | |||||||
R/W-90h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CID | |||||||
R/W-1h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PSDCS | R | 0h | Indicates whether the Function is capable of sending PME messages when in the D3cold state. Because the device does not have aux power, this bit is hardwired to 0. |
30 | PSDHS | R/W | 1h | Indicates whether the Function is capable of sending PME messages when in the D3hot state. This bit is set to 1 by default, but can be modified from the local management bus by writing into Function 0. All other Functions assume the value set in Function 0s Power Management Capabilities Register. |
29 | PSD2S | R | 0h | Indicates whether the Function is capable of sending PME messages when in the D2 state. This bit is hardwired to 0 because D2 state is not supported. |
28 | PSD1S | R/W | 1h | Indicates whether the Function is capable of sending PME messages when in the D1 state. This bit is set to 1 by default, but can be modified from the local management bus by writing into Function 0. All other Functions assume the value set in Function 0s Power Management Capabilities Register. |
27 | PSD0S | R/W | 1h | Indicates whether the Function is capable of sending PME messages when in the D0 state. This bit is set to 1 by default, but can be modified from the local management bus by writing into Function 0. All other Functions assume the value set in Function 0s Power Management Capabilities Register. |
26 | D2S | R | 0h | Set if the Function supports the D2 power state. Currently hardwired to 0. |
25 | D1S | R/W | 1h | Set if the Function supports the D1 power state. This bit can be modified from the local management bus by writing into Function 0. All other Functions assume the value set in Function 0s Power Management Capabilities Register. |
24-22 | MCRAPS | R | 0h | Specifies the maximum current drawn by the device from the aux power source in the D3cold state. This field is not implemented in devices not supporting PME notification when in the D3cold state, and is therefore hardwired to 0. |
21 | DSI | R | 0h | This bit, when set, indicates that the device requires additional configuration steps beyond setting up its PCI configuration space, to bring it to the D0active state from the D0uninitialized state. This bit is hardwired to 0. |
20 | R0 | R | 0h | Reserved |
19 | PC | R | 0h | Not applicable to PCI Express. This bit is hardwired to 0. |
18-16 | VID | R/W | 3h | Indicates the version of the PCI Bus Power Management Specifications that the Function implements. This field is set by default to 011 [Version 1.2]. It can be re-written independently for each Function from the local management bus. |
15-8 | CP | R/W | 90h | Contains pointer to the next PCI Capability Structure. The core sets it to the value defined in the RTL file reg_defaults.h. By default, this points to the MSI Capability Structure. This field can be re-written independently for each Function from the local management bus. |
7-0 | CID | R/W | 1h | Identifies that the capability structure is for Power Management. This field is set by default to 01 hex. It can be re-written independently for each Function from the local management bus. |
PCIE_CORE_VFm_I_PWR_MGMT_CTRL_STAT_REP is shown in Figure 12-1451 and described in Table 12-2842.
Return to the Summary Table.
This location contains the 16-bit Power Management Control/Status Register.
Offset = 6084h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6084h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DR | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
R1 | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PMES | R2 | PE | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R3 | NSR | R4 | PS | ||||
R-0h | R/W-1h | R-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | DR | R | 0h | This optional register is not implemented in the PCIe core. This field is hardwired to 0. |
23-16 | R1 | R | 0h | Reserved |
15 | PMES | R/W | 0h | When PME notification is enabled, writing a 1 into this bit position from the local management bus sets this bit and causes the core to send a PME message from the associated Function. When the Root Complex processes this message, it will turn off this bit by writing a 1 into this bit position though a Config Write. This bit can be set or cleared from the local management bus, by writing a 1 or 0, respectively. It can only be cleared from the configuration path [by writing a 1]. |
14-9 | R2 | R | 0h | Reserved |
8 | PE | R/W | 0h | Setting this bit enables the notification of PME events from the associated Function. This bit can be set also by writing into this register from the local management bus. |
7-4 | R3 | R | 0h | Reserved |
3 | NSR | R/W | 1h | When this bit is set to 1, the Function will maintain all its state in the PM state D3hot. The software is not required to re-initialize the Function registers on the transition back to D0. This bit is set to 1 by default, but can be modified independently for each VF from the local management bus. |
2 | R4 | R | 0h | Reserved |
1-0 | PS | R/W | 0h | Indicates the power state this Function is currently in. This field can be read by the software to monitor the current power state, or can be written to cause a transition to a new state. The valid settings are 00 [state D0], 01 [state D1] and 11 [state D3hot]. The software should not write any other value into this field. This field can also be written from the local management bus independently for each VF Function. |
PCIE_CORE_VFm_RSVD_022_023 is shown in Figure 12-1452 and described in Table 12-2844.
Return to the Summary Table.
Reserved
Offset = 6088h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6088h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RSVD | R | 0h | Reserved |
PCIE_CORE_VFm_I_MSI_CTRL_REG is shown in Figure 12-1453 and described in Table 12-2846.
Return to the Summary Table.
This register is used only when the core is configured to support Message Signaled
Interrupts (MSIs). In addition to the MSI control bits, this location also contains the MSI
Capability ID and the pointer to the next PCI Capability Structure.
Offset = 6090h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6090h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
R0 | MC | ||||||
R-0h | R/W-1h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
AC64 | MME | MMC | ME | ||||
R/W-1h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CP | |||||||
R-B0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CID | |||||||
R-5h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | R0 | R | 0h | Reserved |
24 | MC | R/W | 1h | can be modified using localmanagement interface |
23 | AC64 | R/W | 1h | Set to 1 to indicate that the device is capable of generating 64-bit addresses for MSI messages. |
22-20 | MME | R/W | 0h | Encodes the number of distinct messages that the core is programmed to generate for this Function [000 = 1, 001 = 2, 010 = 4, 011 = 8, 100 = 16, 101 = 32]. This setting must be based on the number of interrupt inputs of the core that are actually used by this Function. This field can be written from the local management bus. |
19-17 | MMC | R/W | 0h | Encodes the number of distinct messages that the core is capable of generating for this Function [000 = 1, 001 = 2, 010 = 4, 011 = 8, 100 = 16, 101 = 32]. Thus, this field defines the number of the interrupt vectors for this Function. The core allows up to 32 distinct messages, but the setting of this field must be based on the number of interrupt inputs of the core that are actually used by the client. For example, if the client logic uses 8 of the 32 distinct MSI interrupt inputs of the core for this Function, then the value of this field must be set to 011. This field can be written from the local management bus. Please see the define den_db_VF_MSI_MULTIPLE_MSG_CAPABLE for default value in the reg_defaults.v files. |
16 | ME | R/W | 0h | Set by the configuration program to enable the MSI feature. This field can also be written from the local management bus. |
15-8 | CP | R | B0h | Pointer to the next PCI Capability Structure. The value read from this read-only field is the corresponding pointer in the MSI Capability Structure of the Physical Function this VF is attached to. The setting is common across all the Virtual Functions. |
7-0 | CID | R | 5h | Specifies that the capability structure is for MSI. Hardwired to 05 hex. |
PCIE_CORE_VFm_I_MSI_MSG_LOW_ADDR is shown in Figure 12-1454 and described in Table 12-2848.
Return to the Summary Table.
This register contains the first 32 bits of the address to be used in the MSI messages
generated by the core for this Function. This address is taken as a 32-bit address if the value
programmed in the MSI Message High Address Register is 0. Otherwise, this address is taken as
the least significant 32 bits of the 64-bit address sent in MSI messages.
Offset = 6094h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6094h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAL | R1 | ||||||||||||||||||||||||||||||
R/W-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | MAL | R/W | 0h | Lower bits of the address to be used in MSI messages. This field can also be written from the local management bus. |
1-0 | R1 | R | 0h | The two lower bits of the address are hardwired to 0 to align the address on a double-word boundary. |
PCIE_CORE_VFm_I_MSI_MSG_HI_ADDR is shown in Figure 12-1455 and described in Table 12-2850.
Return to the Summary Table.
This register contains the 32 most significant bits of the 64-bit address sent by the
core in MSI messages. A value of all zeroes in thei register is taken to mean that the core
should use 32-bit addresses in the messages.
Offset = 6098h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6098h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MAH | R/W | 0h | Contains bits 63:32 of the 64-bit address to be used in MSI Messages. A value of 0 specifies that 32-bit addresses are to be used in the messages. This field can also be written from the local management bus. |
PCIE_CORE_VFm_I_MSI_MSG_DATA is shown in Figure 12-1456 and described in Table 12-2852.
Return to the Summary Table.
This register contains the write data to be used in the MSI messages to be generated for
the associated PCI Function. When the number of distinct messages programmed in the MSI Control
Register is 1, the 32-bit value from this register is used as the data value in the MSI packets
generated by the core for this Function. If the number of distinct messages is more than 1, the
least significant bits of the programmed value are replaced with the encoded interrupt vector
[31:0] of the specific message to generate the write data value for the message.
Offset = 609Ch + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 609Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R2 | MD | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | R2 | R | 0h | Hardwired to 0 |
15-0 | MD | R/W | 0h | Message data to be used for this Function. This field can also be written from the local management bus. |
PCIE_CORE_VFm_I_MSI_MASK is shown in Figure 12-1457 and described in Table 12-2854.
Return to the Summary Table.
This register contains the MSI mask bits, one for each of the interrupt levels.
Offset = 60A0h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60A0h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
R0 | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R0 | MM | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | R0 | R | 0h | Please note that if the Multiple Message Capable field is changed from the local management APBbus, then the width of this field also changes correspondingly |
0 | MM | R/W | 0h | Mask bits for MSI interrupts. The Multiple Message Capable field of the MSI Control Register specifies the number of distinct interrupts for the Function, which determines the number of valid mask bits. Please note that if the Multiple Message Capable field is changed from the local management APBbus, then the width of the MSI Mask field also changes correspondingly |
PCIE_CORE_VFm_I_MSI_PENDING_BITS is shown in Figure 12-1458 and described in Table 12-2856.
Return to the Summary Table.
This register contains the MSI pending interrupt bits, one for each of the interrupt
levels. This field can be written from the local management APBbus.
Offset = 60A4h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60A4h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
R0 | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R0 | MP | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | R0 | R | 0h | Please note that if the Multiple Message Capable field is changed from the local management APBbus, then the width of this field also changes correspondingly |
0 | MP | R/W | 0h | Pending bits for MSI interrupts. This register contains the MSI pending interrupt bits, one for each of the interrupt levels. This field can be written from the local management APBbus. The Multiple Message Capable field of the MSI Control Register specifies the number of distinct interrupts for the Function, which determines the number of valid pending bits. Please note that if the Multiple Message Capable field is changed from the local management APBbus, then the width of the MSI Pending Bits field also changes correspondingly |
PCIE_CORE_VFm_RSVD_02A_02B is shown in Figure 12-1459 and described in Table 12-2858.
Return to the Summary Table.
Reserved
Offset = 60A8h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60A8h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RSVD | R | 0h | Reserved |
PCIE_CORE_VFm_I_MSIX_CTRL is shown in Figure 12-1460 and described in Table 12-2860.
Return to the Summary Table.
This register contains the MSI-X configuration bits, the Capability ID for MSI-X,
and the pointer to the next PCI Capability structure.
Offset = 60B0h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60B0h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
MSIXE | FM | R0 | MSIXTS | ||||
R/W-0h | R/W-0h | R-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MSIXTS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CP | |||||||
R-C0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CID | |||||||
R/W-11h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | MSIXE | R/W | 0h | Set by the configuration program to enable the MSI-X feature. This field can also be written from the local management bus. |
30 | FM | R/W | 0h | This bit serves as a global mask to all the interrupt conditions associated with this Function. When this bit is set, the core will not send out MSI messages from this Function. This field can also be written from the local management bus. |
29-27 | R0 | R | 0h | Reserved |
26-16 | MSIXTS | R/W | 0h | Specifies the size of the MSI-X Table, that is, the number of interrupt vectors defined for the Function. The programmed value is 1 minus the size of the table [that is, this field is set to 0 if the table size is 1.]. It can be re-written independently for each Function from the local management bus. |
15-8 | CP | R | C0h | Contains a pointer to the next PCI Capability Structure. The value read from this read-only field is the corresponding pointer in the MSI-X Capability Structure of the Physical Function this VF is attached to. |
7-0 | CID | R/W | 11h | Identifies that the capability structure is for MSI-X. This field is set by default to 11 hex. It can be rewritten independently for each Function from the local management bus. |
PCIE_CORE_VFm_I_MSIX_TBL_OFFSET is shown in Figure 12-1461 and described in Table 12-2862.
Return to the Summary Table.
This register is used to specify the location of the MSI-X Table in memory. All of the
32 bits of this register can be re-written independently for each Virtual Function from the
local management bus.
Offset = 60B4h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60B4h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TO | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO | BARI | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | TO | R/W | 0h | Offset of the memory address where the MSI-X Table is located, relative to the selected BAR. The three least significant bits of the address are omitted, as the addresses are QWORD aligned. |
2-0 | BARI | R/W | 0h | Identifies the BAR corresponding to the memory address range where the MSI-X Table is located [000 = BAR 0, 001 = BAR 1, ... , 101 = BAR 5]. |
PCIE_CORE_VFm_I_MSIX_PENDING_INTRPT is shown in Figure 12-1462 and described in Table 12-2864.
Return to the Summary Table.
This register is used to specify the location of the MSI-X Pending Bit Array (PBA). The
PBA is a structure in memory containing the pending interrupt bits. All the 32 bits of this
register can be re-written independently for each Virtual Function from the local management
bus.
Offset = 60B8h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60B8h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PO | |||||||||||||||
R/W-1h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PO | BARI | ||||||||||||||
R/W-1h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | PO | R/W | 1h | Offset of the memory address where the PBA is located, relative to the selected BAR. The three least significant bits of the address are omitted, as the addresses are QWORD aligned. |
2-0 | BARI | R/W | 0h | Identifies the BAR corresponding to the memory address range where the PBA Structure is located [000 = BAR 0, 001 = BAR 1, ... , 101 = BAR 5]. The value programmed must be the same as the BAR Indicator configured in the MSI-X Table Offset Register.Identifies the BAR corresponding to the memory address range where the PBA Structure is located [000 = BAR 0, 001 = BAR 1, ... , 101 = BAR 5]. The value programmed must be the same as the BAR Indicator configured in the MSI-X Table Offset Register. |
PCIE_CORE_VFm_RSVD_02F is shown in Figure 12-1463 and described in Table 12-2866.
Return to the Summary Table.
Reserved
Offset = 60BCh + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60BCh + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RSVD | R | 0h | Reserved |
PCIE_CORE_VFm_I_PCIE_CAP_LIST is shown in Figure 12-1464 and described in Table 12-2868.
Return to the Summary Table.
This location identifies the PCI Express device type and its capabilities. It also
contains the Capability ID for the PCI Express Structure and the pointer to the next capability
structure.
Offset = 60C0h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60C0h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
R0 | TRS | IMN | SS | DT | CV | ||||||||||
R-0h | R-0h | R-0h | R-0h | R-0h | R-2h | ||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCP | CID | ||||||||||||||
R-0h | R-10h | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | R0 | R | 0h | Reserved |
30 | TRS | R | 0h | When set to 1, this bit indicates that the device supports routing of Trusted Configuration Requests. Not valid for Endpoints. Hardwired to 0. |
29-25 | IMN | R | 0h | Identifies the MSI or MSI-X interrupt vector for the interrupt message generated corresponding to the status bits in the Slot Status Register, Root Status Register, or this capability structure. This field must be defined based on the chosen interrupt mode - MSI or MSI-X. This field is hardwired to 0. |
24 | SS | R | 0h | Set to 1 when the link connected to a slot. Hardwired to 0. |
23-20 | DT | R | 0h | Indicates the type of device implementing this Function. This field is hardwired to 0 in the EP mode. |
19-16 | CV | R | 2h | Identifies the version number of the capability structure. This field is set to 2 by default to indicate that the Controller is compatible to PCI Express Base Specification Revision 3.0. |
15-8 | NCP | R | 0h | Points to the next PCI capability structure. Set to 0 because this is the last capability structure. |
7-0 | CID | R | 10h | Specifies Capability ID assigned by PCI SIG for this structure. This field is hardwired to 10 hex. |
PCIE_CORE_VFm_I_PCIE_DEV_CAP is shown in Figure 12-1465 and described in Table 12-2870.
Return to the Summary Table.
This register advertises the capabilities of the PCI Express device encompassing this
Function.
Offset = 60C4h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60C4h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
R3 | FLRC | CPLS | CSPLV | ||||
R-0h | R-1h | R-0h | R-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CSPLV | R2 | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RBER | R1 | AL1SL | AL0SL | ||||
R-1h | R-0h | R-0h | R-4h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AL0SL | ETFS | PFS | MPS | ||||
R-4h | R-0h | R-0h | R-1h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | R3 | R | 0h | Reserved |
28 | FLRC | R | 1h | Set when device has Function-Level Reset capability. Hardwired to 1. |
27-26 | CPLS | R | 0h | This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0. |
25-18 | CSPLV | R | 0h | This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0. |
17-16 | R2 | R | 0h | Reserved |
15 | RBER | R | 1h | This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0. |
14-12 | R1 | R | 0h | Reserved |
11-9 | AL1SL | R | 0h | Specifies acceptable latency that the Endpoint can tolerate while transitioning from L1 to L0. This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0. |
8-6 | AL0SL | R | 4h | Specifies acceptable latency that the Endpoint can tolerate while transitioning from L0S to L0. This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0. |
5 | ETFS | R | 0h | Set when device allows the tag field to be extended from 5 to 8 bits. This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0. |
4-3 | PFS | R | 0h | This field is used to extend the tag field by combining unused Function bits with the tag bits. This field is hardwired to 00 to disable this feature. |
2-0 | MPS | R | 1h | Specifies maximum payload size supported by the device. This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0 |
PCIE_CORE_VFm_I_PCIE_DEV_CTRL_STATUS is shown in Figure 12-1466 and described in Table 12-2872.
Return to the Summary Table.
This register contains control and status bits associated with the device implementing
this Function. All the read-write bits in this register can also be written from the local
management bus. Likewise, bits designated as RW1C can also be cleared by writing a 1 from the
local management bus.
Offset = 60C8h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60C8h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
R4 | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
R4 | TP | APD | URD | FED | NFER | CED | |
R-0h | R-0h | R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FLR | MRRS | EBS | EAP | EPF | ETFE | ||
R/W-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPS | ERO | EURR | EFER | ENFER | ECER | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | R4 | R | 0h | Reserved |
21 | TP | R | 0h | Indicates if any of the Non-Posted requests issued by the VF are still pending. |
20 | APD | R | 0h | Reserved |
19 | URD | R/W1C | 0h | Set to 1 by the core when it receives an unsupported request, regardless of whether its reporting is enabled or not. |
18 | FED | R/W1C | 0h | Set to 1 by the core when it detects a fatal error, regardless of whether error reporting is enabled or not, and regardless of whether the error is masked. |
17 | NFER | R/W1C | 0h | Set to 1 by the core when it detects a non-fatal error, regardless of whether error reporting is enabled or not, and regardless of whether the error is masked. |
16 | CED | R/W1C | 0h | Set to 1 by the core when it detects a correctable error, regardless of whether error reporting is enabled or not, and regardless of whether the error is masked |
15 | FLR | R/W | 0h | Writing a 1 into this bit position generated a Function-Level Reset for the selected VF. This bit reads as 0. |
14-12 | MRRS | R | 0h | Reserved |
11 | EBS | R | 0h | Reserved |
10 | EAP | R | 0h | Reserved |
9 | EPF | R | 0h | Reserved |
8 | ETFE | R | 0h | Reserved |
7-5 | MPS | R | 0h | Reserved |
4 | ERO | R | 0h | Reserved |
3 | EURR | R | 0h | Reserved |
2 | EFER | R | 0h | Reserved |
1 | ENFER | R | 0h | Reserved |
0 | ECER | R | 0h | Reserved |
PCIE_CORE_VFm_I_LINK_CAP is shown in Figure 12-1467 and described in Table 12-2874.
Return to the Summary Table.
This register advertises the link-specific capabilities of the device incorporating the
PCIe core. There are no writable bits at this location. A read to this address
returns the Link Capability Register fields of Physical Function m.
Offset = 60CCh + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60CCh + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PN | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
R5 | AOC | LBNC | DLLARC | SDERC | CPM | L1EL | |
R-0h | R-1h | R-0h | R-0h | R-0h | R-0h | R-3h | |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
L1EL | L0SEL | ASPM | MLW | ||||
R-3h | R-2h | R-3h | R-2h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MLW | MLS | ||||||
R-4h | R-4h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | PN | R | 0h | Specifies the port number assigned to the PCI Express link connected to this device. |
23 | R5 | R | 0h | Reserved |
22 | AOC | R | 1h | Setting this bit indicates that the device supports the ASPM Optionality feature. It can be turned off by writing a 0 to this bit position through the local management bus. |
21 | LBNC | R | 0h | A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. Reserved for Endpoint. |
20 | DLLARC | R | 0h | Set to 1 if the device is capable of reporting that the DL Control and Management State Machine has reached the DL_Active state. This bit is hardwired to 0, as this version of the core does not support the feature. |
19 | SDERC | R | 0h | Indicates the capability of the device to report a Surprise Down error condition. This bit is hardwired to 0, as this version of the core does not support the feature. |
18 | CPM | R | 0h | Indicates that the device supports removal of referenc clocks. It is set by default to the value of the define in reg_defaults.h. It can be re-written independently for each function from the local management bus. |
17-15 | L1EL | R | 3h | Specifies the exit latency from L1 state. This parameter is dependent on the Physical Layer implementation. It is set by default to the value define in reg_defaults.h. It can be re-written independently for each Function from the local management bus. |
14-12 | L0SEL | R | 2h | Specifies the time required for the device to transition from L0S to L0. This parameter is dependent on the Physical Layer implementation. It is set by default to the value define in reg_defaults.h. It can be re-written independently for each Function from the local management bus. |
11-10 | ASPM | R | 3h | Indicates the level of ASPM support provided by the device. This field can be re-written independently for each Function from the local management bus. When SRIS is enabled in local management register bit, L0s capability is not supported and is forced low. |
9-4 | MLW | R | 4h | Indicates the maximum number of lanes supported by the device. This field is hardwired based on the setting of the LANE_COUNT_IN strap input. |
3-0 | MLS | R | 4h | Indicates the maximum speed supported by the link. [2.5 GT/s, 5 GT/s, 8 GT/s , 16 GT/s per lane]. This field is hardwired to 0001 [2.5GT/s] when the strap input PCIE_GENERATION_SEL is set to 0, to 0010 [5 GT/s] when the strap is set to 1, and to 0011 [8 GT/s] when the strap input is set to 10,to 0100 [16 GT/s] when the strap input is set to 11. |
PCIE_CORE_VFm_RSVD_034_038 is shown in Figure 12-1468 and described in Table 12-2876.
Return to the Summary Table.
Reserved
Offset = 60D0h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60D0h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RSVD | R | 0h | Reserved |
PCIE_CORE_VFm_I_PCIE_DEV_CAP_2 is shown in Figure 12-1469 and described in Table 12-2878.
Return to the Summary Table.
This register is not implemented for Virtual Functions. A read to this address returns
the Device Capabilities 2 Register fields of Physical Function 0.
Offset = 60E4h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60E4h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
R14 | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MEEP | EEPS | EXFS | OPFFS | T10RS | T10CS | ||
R-1h | R-1h | R-1h | R-1h | R-0h | R-1h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
R13 | TCS | LMS | R12 | BAOCS128 | BAOCS64 | ||
R-0h | R-0h | R-1h | R-0h | R-0h | R-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BAOCS32 | OPRS | AFS | CTDS | CTR | |||
R-0h | R-0h | R-0h | R-1h | R-2h | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | R14 | R | 0h | Reserved |
23-22 | MEEP | R | 1h | Indicates the maximum number of End-End TLP Prefixes supported by the Function. The supported values are: 01b 1 End-End TLP Prefix 10b 2 End-End TLP Prefixes |
21 | EEPS | R | 1h | Indicates whether the Function supports End-End TLP Prefixes. A 1 in this field indicates that the Function supports receiving TLPs containing End-End TLP Prefixes. |
20 | EXFS | R | 1h | Indicates that the Function supports the 3-bit definition of the Fmt field in the TLP header. This bit is hardwired to 1 for all Physical Functions. |
19-18 | OPFFS | R | 1h | A 1 in this bit position indicates that the Function supports the Optimized Buffer Flush/Fill [OBFF] capability using message signaling. |
17 | T10RS | R | 0h | If set function supports 10-bit requester capability otherwise, the function does not. This field reflects the value in SRIOV capability register |
16 | T10CS | R | 1h | If set function supports 10-bit completer capability otherwise, the function does not. This field is identical to the PF value. |
15-14 | R13 | R | 0h | Reserved |
13-12 | TCS | R | 0h | Hardwired to 0. |
11 | LMS | R | 1h | A 1 in this bit position indicates that the Function supports the Latency Tolerance Reporting [LTR] Capability. This bit is set to 1 by default, but can be turned off for all Physical Functions by writing into PF 0. |
10 | R12 | R | 0h | Reserved |
9 | BAOCS128 | R | 0h | Hardwired to 0. |
8 | BAOCS64 | R | 0h | Hardwired to 0. |
7 | BAOCS32 | R | 0h | Hardwired to 0. |
6 | OPRS | R | 0h | Atomic OP routing supported. |
5 | AFS | R | 0h | ARI forwarding supported. |
4 | CTDS | R | 1h | A 1 in this field indicates that the associated Function supports the capability to turn off its Completion timeout. This bit is set to 1 by default, but can be re-written independently for each Function from the local management bus. |
3-0 | CTR | R | 2h | Specifies the Completion Timeout values supported by the device. This field is set by default to 0010 [10 ms - 250 ms]. The actual timeout values are in two programmable local management registers, which allow the timeout settings of the two sub-ranges within Range B to be programmed independently. |
PCIE_CORE_VFm_RSVD_03A_03F is shown in Figure 12-1470 and described in Table 12-2880.
Return to the Summary Table.
Reserved
Offset = 60E8h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 60E8h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RSVD | R | 0h | Reserved |
PCIE_CORE_VFm_I_AER_ENHANCED_CAP_HDR is shown in Figure 12-1471 and described in Table 12-2882.
Return to the Summary Table.
This is the first register in the PCI Express Advanced Error Reporting Capability
Structure of a Virtual Function. This register contains the PCI Express Extended Capability ID,
the capability version, and the pointer to the next capability structure.
Offset = 6100h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6100h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCO | CV | PECID | |||||||||||||||||||||||||||||
R-140h | R-2h | R-1h | |||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | NCO | R | 140h | Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set. |
19-16 | CV | R | 2h | Specifies the SIG assigned value for the version of the capability structure. This field reflects the setting of the corresponding field in the AER Enhanced Capability Header Register of PF 0. |
15-0 | PECID | R | 1h | This field is hardwired to the Capability ID assigned by PCI SIG to the PCI Express AER Extended Capability Structure [0001 hex]. |
PCIE_CORE_VFm_I_UNCORR_ERR_STATUS is shown in Figure 12-1472 and described in Table 12-2884.
Return to the Summary Table.
This register provides the status of the various uncorrectable errors detected by the
PCI Express core. Software may clear any error bit by writing a 1 into the corresponding bit
position. The states of the bits in the Uncorrectable Error Mask Register have no effect on the
status bits of this register. The setting of an uncorrectable error status bit causes the core
to generate an ERR_FATAL message if the corresponding severity bit of the Uncorrectable Error
Severity Register is 1. If the severity bit is 0, however, there are two separate ways the error
could be processed: (i) In certain cases, the uncorrectable error is treated as an Advisory
Non-Fatal Error. These cases are treated as similar to correctable errors, causing the core to
generate an ERR_COR message instead of an ERR_NONFATL message. For details on these special
cases, refer to Section 6.2.3.2.4 of the PCI Express Base Specifications, Version 1.1. (ii) In
all other cases, the core sends an ERR_NONFATAL message when the error is detected. In all
cases, the sending of the error message can be suppressed by setting the bit corresponding to
the error type in the Uncorrectable Error Mask Register. For errors that are not
Function-specific, the error status bus is set in the registers belonging to all the Functions
associated with the link, but only a single message is generated for the entire link. In the
case of certain errors detected by the Transaction Layer, the associated TLP header is logged in
the Shared VF Header Log Registers. All the RW1C bits can also be cleared from the local management bus by
writing a 1 into the bit position.
Offset = 6104h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6104h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
R3 | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
R3 | UNCORR_INT_ERR_STATUS | R2 | URES | ECRC_ERR_STATUS | MALFORMED_TLP_STATUS | RCVR_OVERFLOW_STATUS | UCS |
R-0h | R-0h | R-0h | R/W1C-0h | R-0h | R-0h | R-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CAS | CTS | FCPES | PTS | R1 | |||
R/W1C-0h | R/W1C-0h | R-0h | R/W1C-0h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R1 | DLPER | R0 | |||||
R-0h | R-0h | R-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | R3 | R | 0h | Reserved |
22 | UNCORR_INT_ERR_STATUS | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
21 | R2 | R | 0h | Reserved |
20 | URES | R/W1C | 0h | This bit is set when the core has received a request from the link that it does not support. This error is not Function-specific. This error is considered non-fatal by default. In the special case described in Sections 6.2.3.2.4.1 of the PCI Express Specifications, the error is reported by sending an ERR_COR message. In all other cases, the error is reported by sending an ERR_NONFATAL message. The header of the received request that caused the error is logged in the Shared VF Header Log Registers. STICKY. |
19 | ECRC_ERR_STATUS | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
18 | MALFORMED_TLP_STATUS | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
17 | RCVR_OVERFLOW_STATUS | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
16 | UCS | R/W1C | 0h | This bit is set when the core has received an unexpected Completion packet from the link. This error is not Function-specific. STICKY. |
15 | CAS | R/W1C | 0h | This bit is set when the core has returned the Completer Abort [CA] status to a request received from the link. This error is Function-specific. The header of the received request that caused the error is logged in the Shared VF Header Log Registers. STICKY. |
14 | CTS | R/W1C | 0h | This bit is set when the completion timer associated with an outstanding request times out. This error is Function-specific. This error is considered non-fatal by default. STICKY. |
13 | FCPES | R | 0h | This bit is is not implemented for Virtual Functions. Hardwired to 0. |
12 | PTS | R/W1C | 0h | This bit is set when the core receives a poisoned TLP from the link, targeted at this VF. This error is Function-specific. This error is considered non-fatal by default. The error is reported by sending an ERR_NONFATAL message. The header of the received TLP with error is logged in the Shared VF Header Log Registers associated with the VF. STICKY. |
11-5 | R1 | R | 0h | Reserved |
4 | DLPER | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
3-0 | R0 | R | 0h | Reserved |
PCIE_CORE_VFm_I_UNCORR_ERR_MASK is shown in Figure 12-1473 and described in Table 12-2886.
Return to the Summary Table.
This register is not implemented for Virtual Functions. The setting of the mask bits in
the Uncorrectable Error Mask Register of the Physical Function apply to all associated VFs.
Offset = 6108h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6108h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R4 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | R4 | R | 0h | N/A |
PCIE_CORE_VFm_I_UNCORR_ERR_SEVERITY is shown in Figure 12-1474 and described in Table 12-2888.
Return to the Summary Table.
This register is not implemented for Virtual Functions. The settings of the severity
bits in the Uncorrectable Error Severity Register of the Physical Function apply to all
associated VFs.
Offset = 610Ch + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 610Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R8 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | R8 | R | 0h | N/A |
PCIE_CORE_VFm_I_CORR_ERR_STATUS is shown in Figure 12-1475 and described in Table 12-2890.
Return to the Summary Table.
This register provides the status of the various correctable errors detected by the PCI
Express core. Software may clear any error bit by writing a 1 into the corresponding bit
position. The states of the bits in the Correctable Error Mask Register have no effect on the
status bits of this register. The setting of a correctable error status bit causes the core to
generate an ERR_COR error message to the Root Complex if the error is not masked in the
Correctable Error Mask Register. For errors that are not Function-specific, the error status bus
is set in the registers belonging to all the Functions associated with the link, but only a
single message is generated for the entire link. Header logging of received TLPs does not apply
to correctable errors. All the RW1C bits can also be cleared from the local management bus by
writing a 1 into the bit position.
Offset = 6110h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6110h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
R14 | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
R14 | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
HLOS | CIES | ANFES | RTTS | R13 | RNRS | ||
R/W1C-0h | R-0h | R/W1C-0h | R-0h | R-0h | R-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BDS | BTPS | R12 | RES | ||||
R-0h | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | R14 | R | 0h | Reserved |
15 | HLOS | R/W1C | 0h | This bit is set on a Header Log Register overflow, that is, when the header could not be logged in the Header Log Register because it is occupied by a previous header. As per SR-IOV specification, this bit is hardwired to 0 since the Header Log is Shared among VFs. |
14 | CIES | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
13 | ANFES | R/W1C | 0h | This bit is set when an uncorrectable error occurs, which is determined to belong to one of the special cases described in Section 6.2.3.2.4 of the PCI Express 2.0 Specifications. This causes the core to generate an ERR_COR message in place of an ERR_NONFATAL message. STICKY. |
12 | RTTS | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
11-9 | R13 | R | 0h | Reserved |
8 | RNRS | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
7 | BDS | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
6 | BTPS | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
5-1 | R12 | R | 0h | Reserved |
0 | RES | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
PCIE_CORE_VFm_I_CORR_ERR_MASK is shown in Figure 12-1476 and described in Table 12-2892.
Return to the Summary Table.
The mask bits in this register control the reporting of correctable errors. For each error type
in the Correctable Error Status Register, there is a corresponding bit in this register to mask
its reporting. When a mask bit is set, the occurrence of the error is not reported (by asserting
the CORRECTABLE_ERROR_OUT output).
Offset = 6114h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6114h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
R17 | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
R17 | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
HLOM | CIEM | ANFEM | RTTM | R16 | RNRM | ||
R/W-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BDM | BTM | R15 | REM | ||||
R-0h | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | R17 | R | 0h | N/A |
15 | HLOM | R/W | 0h | This bit, when set, masks the generation of error messages in response to a Header Log register overflow. STICKY. Header logs are shared across Vfs hence this field is reserved. This field is reserved since Header log sharing is selected for this configuration. |
14 | CIEM | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
13 | ANFEM | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
12 | RTTM | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
11-9 | R16 | R | 0h | Reserved |
8 | RNRM | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
7 | BDM | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
6 | BTM | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
5-1 | R15 | R | 0h | Reserved |
0 | REM | R | 0h | This bit is not implemented for Virtual Functions. Hardwired to 0. |
PCIE_CORE_VFm_I_ADVCD_ERR_CAP_CTRL is shown in Figure 12-1477 and described in Table 12-2894.
Return to the Summary Table.
This location contains a pointer to the first error that is reported in the
Uncorrectable Error Status Register.
Offset = 6118h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6118h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
R18 | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
R18 | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
R18 | MHRE | MHRC | ECC | ||||
R-0h | R-0h | R-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECCAP | EEG | EGC | FER | ||||
R-0h | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | R18 | R | 0h | Reserved |
10 | MHRE | R | 0h | Setting this bit enables the Function to log multiple error headers in its Header Log Registers. It is hardwired to 0 |
9 | MHRC | R | 0h | This bit is set when the Function has the capability to log more than one error header in its Header Log Registers. It is hardwired to 0. |
8 | ECC | R | 0h | Setting this bit enables ECRC checking on the receive side of the core. This bit is hardwired to 0. The setting of the corresponding bit in the Advanced Error Capabilities and Control Register of PF 0 applies to all Virtual Functions. |
7 | ECCAP | R | 0h | This read-only bit indicates to the software that the device is capable of checking ECRC in packets received from the link. This bit is hardwired to 0. This setting of the corresponding bit in the Advanced Error Capabilities and Control Register of PF 0 applies to all Virtual Functions. |
6 | EEG | R | 0h | Enables the ECRC generation on the transmit side of the core. This bit is hardwired to 0. The setting of the corresponding bit in the Advanced Error Capabilities and Control Register of PF 0 applies to all Virtual Functions. |
5 | EGC | R | 0h | This read-only bit indicates to the software that the device is capable of generating ECRC in packets transmitted on the link. This bit is hardwired to 0. The setting of the corresponding bit in the Advanced Error Capabilities and Control Register of PF 0 applies to all Virtual Functions. |
4-0 | FER | R | 0h | This is a 5-bit pointer to the bit position in the Uncorrectable Error Status Register corresponding to the error that was detected first. When there are multiple bits set in the Uncorrectable Error Status Register, this field informs the software which error was observed first. To prevent the field from being overwritten before software was able to read it, this field is not updated while the status bit pointed by it in the Uncorrectable Error Status Register remains set. After the software clears this status bit, a subsequent error condition that sets any bit in the Uncorrectable Error Status Register will update the First Error Pointer. Any uncorrectable error type, including the special cases where the error is reported using an ERR_COR message, will set the First Error Pointer [assuming the software has reset the error pointed by it in the Uncorrectable Error Status Register]. STICKY. |
PCIE_CORE_VFm_I_HDR_LOG_0 is shown in Figure 12-1478 and described in Table 12-2896.
Return to the Summary Table.
This is the first of a set of four registers used to capture the header of a TLP
received by the core from the link upon detection of an uncorrectable error.
The Controller implements Shared Header Log for VFs.
All Virtual Functions associated with the same PF share the same Header Log.
When multiple bits are set in the Uncorrectable Error Status Registers of the VFs,
the captured header corresponds to the error that was detected first, that is, the error pointed by the First Error Pointer, of the associated VF.
To prevent the captured header from being over-written before the software is able to read it,
this register is not updated while the status bit pointed by the First Error Pointer in the
Uncorrectable Error Status Register remains set. After the software clears this status bit, a
subsequent error condition that sets any bit in the Uncorrectable Error Status Register will
also cause the Header Log Registers to be updated. The doublewords of the TLP header are
stored in the Header Log Registers with their bytes transposed. That is the byte containing
the Type/Format fields of the header is stored at bit positions 31:24 of the Header Log
Register 0.
Offset = 611Ch + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 611Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HD0 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | HD0 | R | 0h | First DWORD of captured TLP header STICKY. |
PCIE_CORE_VFm_I_HDR_LOG_1 is shown in Figure 12-1479 and described in Table 12-2898.
Return to the Summary Table.
This location contains the second Dword of the captured header of a TLP received from
the link The bytes are stored in transposed order.
Offset = 6120h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6120h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HD1 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | HD1 | R | 0h | Second DWORD of captured TLP header STICKY. |
PCIE_CORE_VFm_I_HDR_LOG_2 is shown in Figure 12-1480 and described in Table 12-2900.
Return to the Summary Table.
This location contains the third Dword of the captured header of a TLP received from
the link The bytes are stored in transposed order.
Offset = 6124h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6124h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HD2 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | HD2 | R | 0h | Third DWORD of captured TLP header STICKY. |
PCIE_CORE_VFm_I_HDR_LOG_3 is shown in Figure 12-1481 and described in Table 12-2902.
Return to the Summary Table.
If the captured TLP header is 4 Dwords long, this location contains the last Dword of
the captured header of a TLP received from the link. If the captured header is a 3-Dword header,
this register is unused. The bytes of the Dword are stored in this register in transposed
order.
Offset = 6128h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6128h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HD3 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | HD3 | R | 0h | Fourth DWORD of captured TLP header STICKY. |
PCIE_CORE_VFm_RSVD_04B_04D is shown in Figure 12-1482 and described in Table 12-2904.
Return to the Summary Table.
Reserved
Offset = 612Ch + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 612Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RSVD | R | 0h | Reserved |
PCIE_CORE_VFm_I_TLP_PRE_LOG_0 is shown in Figure 12-1483 and described in Table 12-2906.
Return to the Summary Table.
First TLP Prefix (if present) associated with the TLP whose header is in the Header Log Register.
The bytes are in transposed order.
Offset = 6138h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6138h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HD1 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | HD1 | R | 0h | First TLP Prefix of captured TLP STICKY. |
PCIE_CORE_VFm_I_ARI_EXT_CAP_HDR is shown in Figure 12-1484 and described in Table 12-2908.
Return to the Summary Table.
This register is used to enable
the Alternate Routing ID interpretation. This register contains the PCI Express Extended
Capability ID, the capability version, and the pointer to the next capability structure.
Offset = 6140h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6140h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCO | CV | PCCID | |||||||||||||||||||||||||||||
R/W-5C0h | R-1h | R-Eh | |||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | NCO | R/W | 5C0h | Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set. |
19-16 | CV | R | 1h | Specifies the SIG-assigned value for the version of the capability structure. This field is taken from the setting of the corresponding field in the ARI Extended Capability Header Register of PF 0. |
15-0 | PCCID | R | Eh | This field is hardwired to the Capability ID assigned by PCI-SIG to the ARI Extended Capability [000E hex]. |
PCIE_CORE_VFm_I_ARI_CAP_AND_CTRL is shown in Figure 12-1485 and described in Table 12-2910.
Return to the Summary Table.
This location contains the ARI Capability Register and the ARI Control Register. All the
fields in this register are hardwired to 0.
Offset = 6144h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6144h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R13 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | R13 | R | 0h | Reserved |
PCIE_CORE_VFm_RSVD_052_09C is shown in Figure 12-1486 and described in Table 12-2912.
Return to the Summary Table.
Reserved
Offset = 6148h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 6148h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RSVD | R | 0h | Reserved |
PCIE_CORE_VFm_ATS_CAP_HEADER is shown in Figure 12-1487 and described in Table 12-2914.
Return to the Summary Table.
This location contains the ATS Extended Capabilities Register, its Capability ID, Version,
and a pointer to the next capability.
Offset = 65C0h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 65C0h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ATSNXTCAP | ATSCAPVER | ||||||||||||||
R/W-0h | R/W-1h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ATSCAPID | |||||||||||||||
R-Fh | |||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | ATSNXTCAP | R/W | 0h | Indicates offset to the next PCI Express capability structure. |
19-16 | ATSCAPVER | R/W | 1h | Specifies the SIG assigned value for the version of the capability structure. |
15-0 | ATSCAPID | R | Fh | Indicates the ATS Extended Capability structure. This field must return a Capability ID of 000Fh indicating that this is an ATS Extended Capability structure. |
PCIE_CORE_VFm_ATS_CAP_CONTROL is shown in Figure 12-1488 and described in Table 12-2916.
Return to the Summary Table.
ATS Capability and Control Register
Offset = 65C4h + (m * 1000h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_DBN_CFG_PCIE_CORE | 0D80 65C4h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ATSEN | R30 | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
R30 | ATSSTU | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ATSGIS | ATSPGALNREQ | ATSINVQD | ||||
R/W-X | R/W-1h | R/W-1h | R/W-1h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ATSEN | R/W | 0h | When Set, the Function is enabled to cache translations. Default value is 0b. |
30-21 | R30 | R | 0h | Reserved |
20-16 | ATSSTU | R/W | 0h | This value indicates to the Function the minimum number of 4096-byte blocks that is indicated in a Translation Completions or Invalidate Requests. This is a power of 2 multiplier and the number of blocks is 2STU. A value of 0 0000b indicates one block and a value of 1 1111b indicates 231 blocks. |
15-7 | RESERVED | R/W | X | |
6 | ATSGIS | R/W | 1h | If Set, the Function supports InvalidationRequests that have the Global Invalidate bit Set. If Clear, the Function ignores the Global Invalidate bit in all Invalidate Requests. |
5 | ATSPGALNREQ | R/W | 1h | If Set, indicates the Untranslated Address is always aligned to a 4096 byte boundary. |
4-0 | ATSINVQD | R/W | 1h | The number of Invalidate Requests that the Function can accept before putting backpressure on the upstream connection. If 0 0000b, the Function can accept 32 Invalidate Requests. |