SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Enable interrupt event | MAILBOX_IRQ_ENABLE_SET_j[0 + y*2] | 0x1 |
User (processor) can perform another task until interrupt occurs See Section 7.1.4.1.3.2 for interrupt handling in receiving mode |