SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 9-81 shows the mapping of events to the WKUP_ESM0. Note that pulse event inputs are triple redundent so that there are three separate inputs for each pulse event (all to the same source signal) but only one connection is shown here.
Interrupt Input Line | Interrupt ID | Interrupt Name |
---|---|---|
WKUP_ESM0_LVL_IN_0 | 0 | WKUP_DMSC0_DMTIMER_0_INTR_PEND_0 |
WKUP_ESM0_LVL_IN_1 | 1 | WKUP_DMSC0_DMTIMER_1_INTR_PEND_0 |
WKUP_ESM0_LVL_IN_2 | 2 | WKUP_DMSC0_DMTIMER_2_INTR_PEND_0 |
WKUP_ESM0_LVL_IN_3 | 3 | WKUP_DMSC0_DMTIMER_3_INTR_PEND_0 |
WKUP_ESM0_LVL_IN_4 | 4 | WKUP_DMSC0_RTI_0_INTR_WWD_0 |
WKUP_ESM0_LVL_IN_5 | 5 | WKUP_DMSC0_RAT_0_EXP_INTR_0 |
WKUP_ESM0_LVL_IN_6 | 6 | WKUP_DMSC0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0 |
WKUP_ESM0_LVL_IN_7 | 7 | WKUP_DMSC0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0 |
WKUP_ESM0_LVL_IN_8 | 8 | WKUP_VTM0_THERM_LVL_GT_TH1_INTR_0 |
WKUP_ESM0_LVL_IN_9 | 9 | WKUP_VTM0_THERM_LVL_LT_TH0_INTR_0 |
WKUP_ESM0_LVL_IN_10 | 10 | WKUP_VTM0_THERM_LVL_GT_TH2_INTR_0 |
WKUP_ESM0_LVL_IN_11 | 11 | WKUP_VTM0_CORR_LEVEL_0 |
WKUP_ESM0_LVL_IN_12 | 12 | WKUP_VTM0_UNCORR_LEVEL_0 |
WKUP_ESM0_LVL_IN_13 | 13 | GLUELOGIC_HFOSC0_CLKLOSS_GLUE_REF_CLK_LOSS_DETECT_OUT_0 |
WKUP_ESM0_LVL_IN_14 | 14 | WKUP_ECC_AGGR0_CORR_LEVEL_0 |
WKUP_ESM0_LVL_IN_15 | 15 | WKUP_ECC_AGGR0_UNCORR_LEVEL_0 |
WKUP_ESM0_LVL_IN_16 | 16 | WKUP_TIMEOUT_INFRA0_SAFEG_TRANS_ERR_LVL_0 |
WKUP_ESM0_LVL_IN_17 | 17 | WKUP_PORZ_SYNC0_PORZ_TIMEOUT_0 |
WKUP_ESM0_LVL_IN_20 | 20 | WKUP_WAKEUP0_VDD_MCU_GLDTC_STAT_THRESH_LOW_FLAG_IPCFG_0 |
WKUP_ESM0_LVL_IN_21 | 21 | WKUP_WAKEUP0_VDD_MCU_GLDTC_STAT_THRESH_HI_FLAG_IPCFG_0 |
WKUP_ESM0_LVL_IN_22 | 22 | WKUP_WAKEUP0_VDDR_MCU_GLDTC_STAT_THRESH_LOW_FLAG_IPCFG_0 |
WKUP_ESM0_LVL_IN_23 | 23 | WKUP_WAKEUP0_VDDR_MCU_GLDTC_STAT_THRESH_HI_FLAG_IPCFG_0 |
WKUP_ESM0_LVL_IN_24 | 24 | MAIN0_VDD_CORE_GLDTC_STAT_THRESH_LOW_FLAG_IPCFG_0 |
WKUP_ESM0_LVL_IN_25 | 25 | MAIN0_VDD_CORE_GLDTC_STAT_THRESH_HI_FLAG_IPCFG_0 |
WKUP_ESM0_LVL_IN_26 | 26 | MAIN0_VDDR_CORE_GLDTC_STAT_THRESH_LOW_FLAG_IPCFG_0 |
WKUP_ESM0_LVL_IN_27 | 27 | MAIN0_VDDR_CORE_GLDTC_STAT_THRESH_HI_FLAG_IPCFG_0 |
WKUP_ESM0_LVL_IN_28 | 28 | MAIN0_VDD_CPU_GLDTC_STAT_THRESH_LOW_FLAG_IPCFG_0 |
WKUP_ESM0_LVL_IN_29 | 29 | MAIN0_VDD_CPU_GLDTC_STAT_THRESH_HI_FLAG_IPCFG_0 |
WKUP_ESM0_LVL_IN_30 | 30 | MAIN0_VDDR_CPU_GLDTC_STAT_THRESH_LOW_FLAG_IPCFG_0 |
WKUP_ESM0_LVL_IN_31 | 31 | MAIN0_VDDR_CPU_GLDTC_STAT_THRESH_HI_FLAG_IPCFG_0 |
WKUP_ESM0_LVL_IN_32 | 32 | WKUP_PSC0_PSC_MOD_WKLP_WKUP_ALWAYSON_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_33 | 33 | WKUP_PSC0_PSC_MOD_WKLP_DMSC_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_34 | 34 | WKUP_PSC0_PSC_MOD_WKLP_DEBUG2DMSC_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_35 | 35 | WKUP_PSC0_PSC_MOD_WKLP_WKUP_GPIO_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_36 | 36 | WKUP_PSC0_PSC_MOD_WKLP_WKUPMCU2MAIN_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_37 | 37 | WKUP_PSC0_PSC_MOD_WKLP_MAIN2WKUPMCU_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_38 | 38 | WKUP_PSC0_PSC_MOD_WKLP_MCU_TEST_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_39 | 39 | WKUP_PSC0_PSC_MOD_WKLP_MCU_DEBUG_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_40 | 40 | WKUP_PSC0_PSC_MOD_WKLP_MCU_MCAN_0_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_41 | 41 | WKUP_PSC0_PSC_MOD_WKLP_MCU_MCAN_1_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_42 | 42 | WKUP_PSC0_PSC_MOD_WKLP_MCU_OSPI_0_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_43 | 43 | WKUP_PSC0_PSC_MOD_WKLP_MCU_OSPI_1_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_44 | 44 | WKUP_PSC0_PSC_MOD_WKLP_MCU_HYPERBUS_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_45 | 45 | WKUP_PSC0_PSC_MOD_WKLP_MCU_I3C_0_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_46 | 46 | WKUP_PSC0_PSC_MOD_WKLP_MCU_I3C_1_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_47 | 47 | WKUP_PSC0_PSC_MOD_WKLP_MCU_ADC_0_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_48 | 48 | WKUP_PSC0_PSC_MOD_WKLP_MCU_ADC_1_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_49 | 49 | WKUP_PSC0_PSC_MOD_WKLP_WKUP_SPARE0_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_50 | 50 | WKUP_PSC0_PSC_MOD_WKLP_WKUP_SPARE1_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_51 | 51 | WKUP_PSC0_PSC_MOD_WKLP_MCU_R5_0_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_52 | 52 | WKUP_PSC0_PSC_MOD_WKLP_MCU_R5_1_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_LVL_IN_53 | 53 | WKUP_PSC0_PSC_MOD_WKLP_MCU_PULSAR_PBIST_0_CS1_CLKSTOP_REQ_0 |
WKUP_ESM0_PLS_IN_64 | 64 | WKUP_PRG_MCU_3POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_0 |
WKUP_ESM0_PLS_IN_65 | 65 | WKUP_PRG_MCU_3POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_0 |
WKUP_ESM0_PLS_IN_66 | 66 | WKUP_PRG_MCU_3POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_1 |
WKUP_ESM0_PLS_IN_67 | 67 | WKUP_PRG_MCU_3POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_1 |
WKUP_ESM0_PLS_IN_68 | 68 | WKUP_PRG_MCU_3POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_2 |
WKUP_ESM0_PLS_IN_69 | 69 | WKUP_PRG_MCU_3POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_2 |
WKUP_ESM0_PLS_IN_72 | 72 | WKUP_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_0 |
WKUP_ESM0_PLS_IN_74 | 74 | WKUP_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_1 |
WKUP_ESM0_PLS_IN_76 | 76 | WKUP_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_2 |
WKUP_ESM0_PLS_IN_78 | 78 | WKUP_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_3 |
WKUP_ESM0_PLS_IN_80 | 80 | WKUP_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_4 |
WKUP_ESM0_PLS_IN_88 | 88 | WKUP_PRG0_POK_PGOOD_UV_OUT_N_TO_ESM_0 |
WKUP_ESM0_PLS_IN_89 | 89 | WKUP_PRG0_POK_PGOOD_OV_OUT_N_TO_ESM_0 |
WKUP_ESM0_PLS_IN_90 | 90 | WKUP_PRG0_POK_PGOOD_UV_OUT_N_TO_ESM_1 |
WKUP_ESM0_PLS_IN_91 | 91 | WKUP_PRG0_POK_PGOOD_OV_OUT_N_TO_ESM_1 |
WKUP_ESM0_PLS_IN_92 | 92 | WKUP_PRG0_POK_PGOOD_UV_OUT_N_TO_ESM_2 |
WKUP_ESM0_PLS_IN_93 | 93 | WKUP_PRG0_POK_PGOOD_OV_OUT_N_TO_ESM_2 |
WKUP_ESM0_PLS_IN_94 | 94 | WKUP_PRG0_POK_PGOOD_UV_OUT_N_TO_ESM_3 |
WKUP_ESM0_PLS_IN_95 | 95 | WKUP_PRG0_POK_PGOOD_OV_OUT_N_TO_ESM_3 |
WKUP_ESM0_PLS_IN_96 | 96 | WKUP_PRG0_POK_PGOOD_UV_OUT_N_TO_ESM_4 |
WKUP_ESM0_PLS_IN_97 | 97 | WKUP_PRG0_POK_PGOOD_OV_OUT_N_TO_ESM_4 |
WKUP_ESM0_PLS_IN_98 | 98 | WKUP_PRG0_POK_PGOOD_UV_OUT_N_TO_ESM_5 |
WKUP_ESM0_PLS_IN_99 | 99 | WKUP_PRG0_POK_PGOOD_OV_OUT_N_TO_ESM_5 |
WKUP_ESM0_PLS_IN_120 | 120 | WKUP_GPIOMUX_INTRTR0_OUTP_8 |
WKUP_ESM0_PLS_IN_121 | 121 | WKUP_GPIOMUX_INTRTR0_OUTP_9 |
WKUP_ESM0_PLS_IN_122 | 122 | WKUP_GPIOMUX_INTRTR0_OUTP_10 |
WKUP_ESM0_PLS_IN_123 | 123 | WKUP_GPIOMUX_INTRTR0_OUTP_11 |
WKUP_ESM0_PLS_IN_124 | 124 | WKUP_GPIOMUX_INTRTR0_OUTP_12 |
WKUP_ESM0_PLS_IN_125 | 125 | WKUP_GPIOMUX_INTRTR0_OUTP_13 |
WKUP_ESM0_PLS_IN_126 | 126 | WKUP_GPIOMUX_INTRTR0_OUTP_14 |
WKUP_ESM0_PLS_IN_127 | 127 | WKUP_GPIOMUX_INTRTR0_OUTP_15 |