SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-426 lists the memory-mapped registers for the NAVSS0_UDMASS_RINGACC0_GCFG. All register offset addresses not listed in Table 10-426 should be considered as reserved locations and the register contents should not be modified.
The Ring Accelerator Global Control /Status Registers region is accessed by setting the cfg_rsel signal to 0 during the access. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_RINGACC0_GCFG | 3116 0000h |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG | 285D 0000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_RINGACC0_GCFG Physical Address | MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG Physical Address |
---|---|---|---|---|
0h | RINGACC_REVISION | Revision Register | 3116 0000h | 285D 0000h |
10h | RINGACC_TRACE_CTL | Trace Control Register | 3116 0010h | 285D 0010h |
20h | RINGACC_OVRFLOW | Overflow Queue Register | 3116 0020h | 285D 0020h |
40h | RINGACC_ERROR_EVT | Error Event Register | 3116 0040h | 285D 0040h |
44h | RINGACC_ERROR_LOG | Error Log Register | 3116 0044h | 285D 0044h |
RINGACC_REVISION is shown in Figure 10-157 and described in Table 10-428.
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The Revision Register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_GCFG | 3116 0000h |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG | 285D 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODID | |||||||||||||||
R-663Ch | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-13h | R-1h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODID | R | 663Ch | Module ID field |
15-11 | REVRTL | R | 13h | RTL revision - for this device. |
10-8 | REVMAJ | R | 1h | Major revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | REVMIN | R | 0h | Minor revision |
RINGACC_TRACE_CTL is shown in Figure 10-158 and described in Table 10-430.
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Trace Control Register
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_GCFG | 3116 0010h |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG | 285D 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EN | ALL_QUEUES | MSG | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-X | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
QUEUE | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUEUE | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | EN | R/W | 0h | Trace enable 0 = disable 1 = enable. |
30 | ALL_QUEUES | R/W | 0h | Trace everything 0 = only the selected queue 1 = every queue. |
29 | MSG | R/W | 0h | Trace message data 0 = include only the operation 1 = include message data. |
28-16 | RESERVED | R/W | X | |
15-0 | QUEUE | R/W | 0h | Queue number when tracing a single queue. |
RINGACC_OVRFLOW is shown in Figure 10-159 and described in Table 10-432.
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Overflow Queue Register
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_GCFG | 3116 0020h |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG | 285D 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | QUEUE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | QUEUE | R/W | 0h | Queue to send overflow messages. |
RINGACC_ERROR_EVT is shown in Figure 10-160 and described in Table 10-434.
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Error Event Register
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_GCFG | 3116 0040h |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG | 285D 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVT | ||||||||||||||||||||||||||||||
R/W-X | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | EVT | R/W | FFFFh | Event to send when detecting a bus error. |
RINGACC_ERROR_LOG is shown in Figure 10-161 and described in Table 10-436.
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Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event is pending.
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_GCFG | 3116 0044h |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG | 285D 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PUSH | RESERVED | ||||||
R-0h | R-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
QUEUE | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUEUE | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PUSH | R | 0h | Bus error was caused by a push. 0 = pop. 1 = push. |
30-16 | RESERVED | R | X | |
15-0 | QUEUE | R | 0h | Queue that received the bus error. |