SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-448 lists the memory-mapped registers for the NAVSS0_UDMASS_RINGACC0_CFG_RT. All register offset addresses not listed in Table 10-448 should be considered as reserved locations and the register contents should not be modified.
The Ring Accelerator Control /Status Registers region is accessed by setting the cfg_rsel signal to 2 during the access. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG_RT | 3C00 0000h |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT | 2B80 0000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_RINGACC0_CFG_RT Physical Address | MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT Physical Address |
---|---|---|---|---|
10h + formula | RINGACC_DB_j | Realtime Ring N Doorbell Register | 3C00 0010h + formula | 2B80 0010h + formula |
18h + formula | RINGACC_OCC_j | Realtime Ring N Occupancy Register | 3C00 0018h + formula | 2B80 0018h + formula |
1Ch + formula | RINGACC_INDX_j | Realtime Ring N Current Index Register | 3C00 001Ch + formula | 2B80 001Ch + formula |
20h + formula | RINGACC_HWOCC_j | Realtime Ring N Hardware Occupancy Register | 3C00 0020h + formula | 2B80 0020h + formula |
24h + formula | RINGACC_HWINDX_j | Realtime Ring N Current Index Register | 3C00 0024h + formula | 2B80 0024h + formula |
RINGACC_DB_j is shown in Figure 10-166 and described in Table 10-450.
Return to Summary Table.
The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation.
Offset = 10h + (j * 1000h); where
j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG_RT
j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG_RT | 3C00 0010h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT | 2B80 0010h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CNT | ||||||||||||||||||||||||||||||
W-X | W-0h | ||||||||||||||||||||||||||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | W | X | |
7-0 | CNT | W | 0h | Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation, this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ absolute value will increase or decrease based on the sign of the tentry_cnt). |
RINGACC_OCC_j is shown in Figure 10-167 and described in Table 10-452.
Return to Summary Table.
The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be used for triggering hardware operations and/or for generating interrupts to the host.
Offset = 18h + (j * 1000h); where
j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG_RT
j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG_RT | 3C00 0018h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT | 2B80 0018h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CNT | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-21 | RESERVED | R | X | |
20-0 | CNT | R | 0h | Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed. |
RINGACC_INDX_j is shown in Figure 10-168 and described in Table 10-454.
Return to Summary Table.
The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel.
Offset = 1Ch + (j * 1000h); where
j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG_RT
j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG_RT | 3C00 001Ch + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT | 2B80 001Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IDX | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | X | |
19-0 | IDX | R | 0h | Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size Register for the ring the index will be reset back to 0. |
RINGACC_HWOCC_j is shown in Figure 10-169 and described in Table 10-456.
Return to Summary Table.
The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be used for triggering hardware operations and/or for generating interrupts to the host.
Offset = 20h + (j * 1000h); where
j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG_RT
j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG_RT | 3C00 0020h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT | 2B80 0020h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CNT | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-21 | RESERVED | R | X | |
20-0 | CNT | R | 0h | Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed. |
RINGACC_HWINDX_j is shown in Figure 10-170 and described in Table 10-458.
Return to Summary Table.
The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel.
Offset = 24h + (j * 1000h); where
j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG_RT
j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_RINGACC0_CFG_RT | 3C00 0024h + formula |
MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT | 2B80 0024h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IDX | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | X | |
19-0 | IDX | R | 0h | Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size Register for the ring the index will be reset back to 0. |