SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 5-1379 lists the memory-mapped registers for the WKUP_VTM0_MMR_VBUSP_CFG1 registers. All register offset addresses not listed in Table 5-1379 should be considered as reserved locations and the register contents should not be modified.
All the MMRs in this region by default use mod_g_rst_n as their reset unless specified otherwise.
Instance | Base Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0000h |
WKUP_VTM_PID is shown in Figure 5-664 and described in Table 5-1381.
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VTM Peripheral Identification Register
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | FUNC | |||||||||||||
R-1h | R-2h | R-61Bh | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R_RTL | X_MAJOR | CUSTOM | Y_MINOR | ||||||||||||
R-9h | R-1h | R-0h | R-1h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | PID scheme |
29-28 | BU | R | 2h | BU |
27-16 | FUNC | R | 61Bh | Module functional identifier |
15-11 | R_RTL | R | 9h | RTL revision number |
10-8 | X_MAJOR | R | 1h | Major revision number |
7-6 | CUSTOM | R | 0h | Custom revision number |
5-0 | Y_MINOR | R | 1h | Minor revision number |
WKUP_VTM_DEVINFO_PWR0 is shown in Figure 5-665 and described in Table 5-1383.
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Device specific voltage domain and temp sensor information register.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | VTM_VD_MAP | ||||||
R-X | R-X | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VD_RTC | RESERVED | |||||
R-X | R-X | R-X | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TMPSENS_CT | CVD_CT | ||||||
R-X | R-X | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | X | |
19-16 | VTM_VD_MAP | R | X | Core voltage domain, cVD, global mapping 4-bit code, in the context of this SoC. |
15-13 | RESERVED | R | X | |
12 | VD_RTC | R | X | RTC voltage domain presence. |
11-8 | RESERVED | R | X | |
7-4 | TMPSENS_CT | R | X | Number of temperature sensors associated with this
VTM. |
3-0 | CVD_CT | R | X | Number of core voltage domains in device. |
WKUP_VTM_VD_DEVINFO_j is shown in Figure 5-666 and described in Table 5-1385.
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Voltage domain a information register. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if necessary.
Offset = 100h + (j * 20h); where j = 0h to 7h
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0100h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | AVS0_SUP | VD_MAP | |||||
R/W-X | R/W-X | R-X | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-X | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R/W | X | |
12 | AVS0_SUP | R/W | X | Indicates VD0 AVS class0 support. |
11-8 | VD_MAP | R | X | Indicates the core voltage domain mapping of VTM VD. |
7-0 | RESERVED | R/W | X |
WKUP_VTM_VD_OPPVID_j is shown in Figure 5-667 and described in Table 5-1387.
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Voltage domain a VID actual code used as reference by Firmware to set the various voltage domain supply voltages. Reset defaults are sourced from efuse for each OPP. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if necessary.
Offset = 104h + (j * 20h); where j = 0h to 7h
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0104h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OPP_3 | OPP_2 | OPP_1 | OPP_0 | ||||||||||||||||||||||||||||
R/W-X | R/W-X | R/W-X | R/W-X | ||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | OPP_3 | R/W | X | OPP 3 default VID. |
23-16 | OPP_2 | R/W | X | OPP 2 default VID. |
15-8 | OPP_1 | R/W | X | OPP 1 default VID. |
7-0 | OPP_0 | R/W | X | OPP 0 default VID. |
WKUP_VTM_GT_TH1_INT_RAW_STAT_SET is shown in Figure 5-668 and described in Table 5-1389.
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Interrupt RAW event status and set MMR for interrupt GT_TH1 for each voltage domain. NOTE: This MMR and the companion MMR, WKUP_VTM_GT_TH1_INT_EN_STAT_CLR are fully linked for write operation, but partially linked for reads, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR. However the reads to these 2 MMRs don't yield the same read data. Reads to *_INT_RAW_STAT_SET return the full "raw" events contents of the common linked MMR, whereas reads to MMR *_INT_EN_STAT_CLR will yield the masked-content of the linked MMR. The mask for the read is defined by the contents of the related MMR *_INT_EN_SET/CLR.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||||||||||||||||||
R/W-X | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | INT_VD | R/W1S | 0h | Interrupt pending bit set for gt_th1_int from VD[7:0]. |
WKUP_VTM_VD_EVT_STAT_j is shown in Figure 5-669 and described in Table 5-1391.
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Voltage domain a event and control status register.
Offset = 108h + (j * 20h); where j = 0h to 7h
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0108h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LT_TH0_ALERT | GT_TH2_ALERT | GT_TH1_ALERT | ||||
R-X | R-X | R-X | R-X | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | X | |
2 | LT_TH0_ALERT | R | X | This bit reflects the status of the TH0 undertemp alert resulting from the AND of all the similar alerts produced by the temp sensors selected by VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel. |
1 | GT_TH2_ALERT | R | X | This bit reflects the status of the merged temperature alert resulting from the combination of all the similar alerts produced by the temp-monitors selected as showed in field VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel. |
0 | GT_TH1_ALERT | R | X | This bit reflects the status of the merged temperature alert resulting from the OR of all the similar alerts produced by the temp-monitors selected as showed in field VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel. |
WKUP_VTM_GT_TH1_INT_EN_STAT_CLR is shown in Figure 5-670 and described in Table 5-1393.
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Enabled interrupt event status and clear MMR for interrupt GT_TH1 per voltage domain. NOTE: This MMR and the companion MMR, WKUP_VTM_GT_TH1_INT_RAW_STAT_SET are fully linked for write operation, but partially linked for reads, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR. However the reads to these 2 MMRs don't yield the same read data. Reads to *_INT_RAW_STAT_SET return the full "raw" events contents of the common linked MMR, whereas reads to MMR *_INT_EN_STAT_CLR will yield the masked-content of the linked MMR. The mask for the read is defined by the contents of the related MMR *_INT_EN_SET/CLR.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||||||||||||||||||
R/W-X | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | INT_VD | R/W1C | 0h | Interrupt masked pending bit for gt_th1_int from VD[7:0]. |
WKUP_VTM_VD_EVT_SEL_SET_j is shown in Figure 5-671 and described in Table 5-1395.
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Voltage domain a event select and control set register. NOTE: This MMR and the companion MMR VTM_VD[a]_EVT_SEL_CLR are linked, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR and reads to either of these 2 MMRs read the same content.
Offset = 10Ch + (j * 20h); where j = 0h to 7h
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 010Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TSENS_EVT_SEL | ||||||||||||||
R/W-X | R/W1S-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-16 | TSENS_EVT_SEL | R/W1S | 0h | In this field we select which of the event contributions of the |
15-0 | RESERVED | R/W | X |
WKUP_VTM_VD_EVT_SEL_CLR_j is shown in Figure 5-672 and described in Table 5-1397.
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Voltage domain a event select and control clear register. NOTE: This MMR and the companion MMR VTM_VD[a]_EVT_SEL_SET are linked, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR and reads to either of these 2 MMRs read the same content.
Offset = 110h + (j * 20h); where j = 0h to 7h
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0110h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TSENS_EVT_SEL | ||||||||||||||
R/W-X | R/W1C-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-16 | TSENS_EVT_SEL | R/W1C | 0h | In this field we select which of the event contributions of the 8-maximum possible temp-monitors controlled by this VTM will contribute to generate the merged event/alerts of this VD. |
15-0 | RESERVED | R/W | X |
WKUP_VTM_GT_TH1_INT_EN_SET is shown in Figure 5-673 and described in Table 5-1399.
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Enable set MMR for interrupt GT_TH1 for each voltage domain. NOTE: This MMR and the companion MMR, WKUP_VTM_GT_TH1_INT_EN_CLR are linked, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR and reads to either of these 2 MMRs read the same content.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0214h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||||||||||||||||||
R/W-X | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | INT_VD | R/W1S | 0h | Interrupt enable bit for gt_th1_int from VD[7:0]. |
WKUP_VTM_GT_TH1_INT_EN_CLR is shown in Figure 5-674 and described in Table 5-1401.
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Enable clear MMR for interrupt GT_TH1 for each voltage domain. NOTE: This MMR and the companion MMR, WKUP_VTM_GT_TH1_INT_EN_SET are linked, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR and reads to either of these 2 MMRs read the same content.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0218h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||||||||||||||||||
R/W-X | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | INT_VD | R/W1C | 0h | Interrupt enable bit for gt_th1_int from VD[7:0]. |
WKUP_VTM_GT_TH2_INT_RAW_STAT_SET is shown in Figure 5-675 and described in Table 5-1403.
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Interrupt RAW event status and set MMR for interrupt GT_TH2 for each voltage domain. NOTE: This MMR and the companion MMR, WKUP_VTM_GT_TH2_INT_EN_STAT_CLR are fully linked for write operation, but partially linked for reads, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR. However the reads to these 2 MMRs don't yield the same read data. Reads to *_INT_RAW_STAT_SET return the full "raw" events contents of the common linked MMR, whereas reads to MMR *_INT_EN_STAT_CLR will yield the masked-content of the linked MMR. The mask for the read is defined by the contents of the related MMR *_INT_EN_SET/CLR.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0224h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||||||||||||||||||
R/W-X | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | INT_VD | R/W1S | 0h | Interrupt pending bit set for gt_th2_int from VD[7:0]. |
WKUP_VTM_GT_TH2_INT_EN_STAT_CLR is shown in Figure 5-676 and described in Table 5-1405.
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Enabled interrupt event status and clear MMR for interrupt GT_TH2 per voltage domain. NOTE: This MMR and the companion MMR, WKUP_VTM_GT_TH2_INT_RAW_STAT_SET are fully linked for write operation, but partially linked for reads, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR. However the reads to these 2 MMRs don't yield the same read data. Reads to *_INT_RAW_STAT_SET return the full "raw" events contents of the common linked MMR, whereas reads to MMR *_INT_EN_STAT_CLR will yield the masked-content of the linked MMR. The mask for the read is defined by the contents of the related MMR *_INT_EN_SET/CLR.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0228h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||||||||||||||||||
R/W-X | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | INT_VD | R/W1C | 0h | Interrupt enabled pending bit for gt_th2_int from VD[7:0]. |
WKUP_VTM_GT_TH2_INT_EN_SET is shown in Figure 5-677 and described in Table 5-1407.
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Enable set MMR for interrupt GT_TH2 for each voltage domain. NOTE: This MMR and the companion MMR, WKUP_VTM_GT_TH2_INT_EN_CLR are linked, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR and reads to either of these 2 MMRs read the same content.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0234h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||||||||||||||||||
R/W-X | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | INT_VD | R/W1S | 0h | Interrupt enable bit for gt_th2_int from VD[7:0]. |
WKUP_VTM_GT_TH2_INT_EN_CLR is shown in Figure 5-678 and described in Table 5-1409.
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Enable clear MMR for interrupt GT_TH2 for each voltage domain. NOTE: This MMR and the companion MMR, WKUP_VTM_GT_TH2_INT_EN_SET are linked, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR and reads to either of these 2 MMRs read the same content.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0238h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||||||||||||||||||
R/W-X | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | INT_VD | R/W1C | 0h | Interrupt enable bit for gt_th2_int from VD[7:0]. |
WKUP_VTM_LT_TH0_INT_RAW_STAT_SET is shown in Figure 5-679 and described in Table 5-1411.
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Interrupt RAW event status and set MMR for interrupt LT_TH0 for each voltage domain. NOTE: This MMR and the companion MMR, WKUP_VTM_LT_TH0_INT_EN_STAT_CLR are fully linked for write operation, but partially linked for reads, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR. However the reads to these 2 MMRs don't yield the same read data. Reads to *_INT_RAW_STAT_SET return the full "raw" events contents of the common linked MMR, whereas reads to MMR *_INT_EN_STAT_CLR will yield the masked-content of the linked MMR. The mask for the read is defined by the contents of the related MMR *_INT_EN_SET/CLR.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0244h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||||||||||||||||||
R/W-X | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | INT_VD | R/W1S | 0h | Interrupt pending bit set for lt_th0_int from VD[7:0]. |
WKUP_VTM_LT_TH0_INT_EN_STAT_CLR is shown in Figure 5-680 and described in Table 5-1413.
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Enabled interrupt event status and clear MMR for interrupt LT_TH0 per voltage domain. NOTE: This MMR and the companion MMR, WKUP_VTM_LT_TH0_INT_RAW_STAT_SET are fully linked for write operation, but partially linked for reads, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR. However the reads to these 2 MMRs don't yield the same read data. Reads to *_INT_RAW_STAT_SET return the full "raw" events contents of the common linked MMR, whereas reads to MMR *_INT_EN_STAT_CLR will yield the masked-content of the linked MMR. The mask for the read is defined by the contents of the related MMR *_INT_EN_SET/CLR.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0248h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||||||||||||||||||
R/W-X | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | INT_VD | R/W1C | 0h | Interrupt enabled pending status bit for lt_th0_int from VD[7:0]. |
WKUP_VTM_LT_TH0_INT_EN_SET is shown in Figure 5-681 and described in Table 5-1415.
Return to Summary Table.
Enable set MMR for interrupt LT_TH0 for each voltage domain. NOTE: This MMR and the companion MMR, WKUP_VTM_LT_TH0_INT_EN_CLR are linked, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR and reads to either of these 2 MMRs read the same content.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0254h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||||||||||||||||||
R/W-X | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | INT_VD | R/W1S | 0h | Interrupt enable bit for lt_th0_int from VD[7:0]. |
WKUP_VTM_LT_TH0_INT_EN_CLR is shown in Figure 5-682 and described in Table 5-1417.
Return to Summary Table.
Enable clear MMR for interrupt LT_TH0 for each voltage domain. NOTE: This MMR and the companion MMR, WKUP_VTM_LT_TH0_INT_EN_SET are linked, which means that they are in fact a single common MMR, with 2 different write addresses/mechanisms, and thus the single common MMR updates with the writes to either MMR and reads to either of these 2 MMRs read the same content.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0258h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_VD | ||||||||||||||||||||||||||||||
R/W-X | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | INT_VD | R/W1C | 0h | Interrupt enable bit for lt_th0_int from VD[7:0]. |
WKUP_VTM_TMPSENS_CTRL_j is shown in Figure 5-683 and described in Table 5-1419.
Return to Summary Table.
Temperature Sensor Band-gap control register for sensor a.
Offset = 300h + (j * 20h); where j = 0h to 7h
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0300h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | LT_TH0_EN | GT_TH2_EN | GT_TH1_EN | ||||
R/W-X | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-X | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R/W | X | |
10 | LT_TH0_EN | R/W | 0h | Enable under-threshold0 event. |
9 | GT_TH2_EN | R/W | 0h | Enable over-threshold2 event. |
8 | GT_TH1_EN | R/W | 0h | Enable over-threshold1 event. |
7-0 | RESERVED | R/W | X |
WKUP_VTM_TMPSENS_STAT_j is shown in Figure 5-684 and described in Table 5-1421.
Return to Summary Table.
Temperature Sensor Band-gap Status register for sensor a.
Offset = 308h + (j * 20h); where j = 0h to 7h
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0308h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | VD_MAP | ||||||
R-X | R-X | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MAXT_OUTRG_ALERT | LT_TH0_ALERT | GT_TH2_ALERT | GT_TH1_ALERT | EOC_FC_UPDATE | DATA_VALID | DATA_OUT | |
R-X | R-0h | R-0h | R-0h | R-0h | R-X | R-X | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_OUT | |||||||
R-X | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | X | |
19-16 | VD_MAP | R | X | Indicates the core voltage domain placement of the temp sensor. |
15 | MAXT_OUTRG_ALERT | R | X | This bit will be driven to a level 1 for a given temperature monitor if it has its corresponding bit maxt_outrg_en = 1, and the temperature reading is reporting to be outside the max temperature supported, temp > programmed value. |
14 | LT_TH0_ALERT | R | 0h | This field reflects the status of the lt_th0_alert comparator result. |
13 | GT_TH2_ALERT | R | 0h | This field reflects the status of the gt_th2_alert comparator result. |
12 | GT_TH1_ALERT | R | 0h | This field reflects the status of the gt_th1_alert comparator result. |
11 | EOC_FC_UPDATE | R | 0h | First time end of conversion. |
10 | DATA_VALID | R | X | Data_valid signal value from sensor: ADC End of Conversion. |
9-0 | DATA_OUT | R | X | Data_out signal value from sensor: Temperature data from the ADC in monitor. |
WKUP_VTM_TMPSENS_TH_j is shown in Figure 5-685 and described in Table 5-1423.
Return to Summary Table.
Temperature Sensor Band-gap Threshold register for sensor a.
Offset = 30Ch + (j * 20h); where j = 0h to 7h
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 030Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TH1_VAL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TH0_VAL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R/W | X | |
25-16 | TH1_VAL | R/W | 0h | Threshold point-1, thpt1, temp-value. |
15-10 | RESERVED | R/W | X | |
9-0 | TH0_VAL | R/W | 0h | Threshold point-0, thpt0, temp-value. |
WKUP_VTM_TMPSENS_TH2_j is shown in Figure 5-686 and described in Table 5-1425.
Return to Summary Table.
Temperature Sensor Band-gap Threshold register 2 for sensor a.
Offset = 310h + (j * 20h); where j = 0h to 7h
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG1 | 4204 0310h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TH2_VAL | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | TH2_VAL | R/W | 0h | Threshold point-2, thpt2, temp-value. |
Table 5-1427 lists the memory-mapped registers for the WKUP_VTM0_MMR_VBUSP_CFG2 registers. All register offset addresses not listed in Table 5-1427 should be considered as reserved locations and the register contents should not be modified.
This region contains critical control MMRs that should be protected and only accessed by a trusted entity. All the MMRs in this region by default use mod_g_rst_n as their reset unless specified otherwise.
Instance | Base Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG2 | 4204 0000h |
Offset | Acronym | Register Name | WKUP_VTM0_MMR_VBUSP_CFG2 Physical Address |
---|---|---|---|
8h | WKUP_VTM_CLK_CTRL | 4205 0008h | |
Ch | WKUP_VTM_MISC_CTRL | 4205 000Ch | |
10h | WKUP_VTM_MISC_CTRL2 | 4205 0010h | |
20h | WKUP_VTM_SAMPLE_CTRL | 4205 0020h | |
300h + formula | WKUP_VTM_TMPSENS_CTRL_j | 4205 0300h + formula | |
304h + formula | WKUP_VTM_TMPSENS_TRIM_j | 4205 0304h + formula |
WKUP_VTM_CLK_CTRL is shown in Figure 5-687 and described in Table 5-1429.
Return to Summary Table.
VTM clock related control MMR. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if necessary. The e-fuse value is sampled from input port efuse_tsens_clk_src_div. The tsens_clks_src_div field is Device specific.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG2 | 4205 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TSENS_CLK_SEL | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TSENS_CLK_DIV | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | TSENS_CLK_SEL | R/W | 0h | Temperature sensor clock source selector. |
30-5 | RESERVED | R/W | X | |
4-0 | TSENS_CLK_DIV | R/W | 0h | Temperature sensor clock source divider selector. |
WKUP_VTM_MISC_CTRL is shown in Figure 5-688 and described in Table 5-1431.
Return to Summary Table.
VTM miscellaneous control bits.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG2 | 4205 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ANY_MAXT_OUTRG_ALERT_EN | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | ANY_MAXT_OUTRG_ALERT_EN | R/W | 0h | This bit when enabled will cause the VTM's output therm_maxtemp_outrange_alert to be driven high, if any of the sources for the maxt_outrg_alert, is set high. |
WKUP_VTM_MISC_CTRL2 is shown in Figure 5-689 and described in Table 5-1433.
Return to Summary Table.
VTM miscellaneous control bits.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG2 | 4205 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | MAXT_OUTRG_ALERT_THR0 | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MAXT_OUTRG_ALERT_THR | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R/W | X | |
25-16 | MAXT_OUTRG_ALERT_THR0 | R/W | 0h | This defines the global max temperature out of range safe sample value. |
15-10 | RESERVED | R/W | X | |
9-0 | MAXT_OUTRG_ALERT_THR | R/W | 0h | This defines the global max temperature out of range sample value. |
WKUP_VTM_SAMPLE_CTRL is shown in Figure 5-690 and described in Table 5-1435.
Return to Summary Table.
VTM sample related control MMR. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if necessary. The e-fuse value is sampled from input port efuse_sample_clk_cnt. The sample_clk_cnt field is Device specific.
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG2 | 4205 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SAMPLE_PER_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | SAMPLE_PER_CNT | R/W | 0h | Temperature sensor sample period count selector. |
WKUP_VTM_TMPSENS_CTRL_j is shown in Figure 5-691 and described in Table 5-1437.
Return to Summary Table.
Temperature Sensor Band-gap control register for sensor a.
Offset = 300h + (j * 20h); where j = 0h to 7h
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG2 | 4205 0300h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MAXT_OUTRG_EN | RESERVED | |||||
R/W-X | R/W-0h | R/W-X | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLRZ | SOC | CONT | RESERVED | |||
R/W-X | R/W-1h | R/W-0h | R/W-0h | R/W-X | |||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R/W | X | |
11 | MAXT_OUTRG_EN | R/W | 0h | Enable out-of-range event. |
10-7 | RESERVED | R/W | X | |
6 | CLRZ | R/W | 1h | Temp-Monitor control: |
5 | SOC | R/W | 0h | Temp-Monitor control: ADC Start of Conversion. |
4 | CONT | R/W | 0h | Temp-Monitor control: ADC Continuous mode. |
3-0 | RESERVED | R/W | X |
WKUP_VTM_TMPSENS_TRIM_j is shown in Figure 5-692 and described in Table 5-1439.
Return to Summary Table.
Temperature Sensor Band-gap trim values register for sensor a. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if necessary.
Offset = 304h + (j * 20h); where j = 0h to 7h
Instance | Physical Address |
---|---|
WKUP_VTM0_MMR_VBUSP_CFG2 | 4205 0304h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TRIMO | RESERVED | TRIMG | ||||||||||||
R/W-X | R/W-X | R/W-X | R/W-X | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-8 | TRIMO | R/W | X | Trim offset bits in the temp sensor. |
7-5 | RESERVED | R/W | X | |
4-0 | TRIMG | R/W | X | Trim gain bits in the temp sensor. |
Table 5-1441 lists the memory-mapped registers for the WKUP_VTM0_ECCAGGR_CFG registers. All register offset addresses not listed in Table 5-1441 should be considered as reserved locations and the register contents should not be modified.
For more information about ECC Aggregator functionality, see ECC Aggregator.
Instance | Base Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 0000h |
Offset | Acronym | Register Name | WKUP_VTM0_ECCAGGR_CFG Physical Address |
---|---|---|---|
0h | WKUP_VTM_REV | Aggregator Revision Register | 4281 0000h |
8h | WKUP_VTM_VECTOR | ECC WKUP_VTM_VECTOR Register | 4281 0008h |
Ch | WKUP_VTM_STAT | Misc Status | 4281 000Ch |
10h + formula | WKUP_VTM_RESERVED_SVBUS_y | Reserved Area for Serial VBUS Registers | 4281 0010h + formula |
3Ch | WKUP_VTM_SEC_EOI_REG | EOI Register | 4281 003Ch |
40h | WKUP_VTM_SEC_STATUS_REG0 | Interrupt Status Register 0 | 4281 0040h |
80h | WKUP_VTM_SEC_ENABLE_SET_REG0 | Interrupt Enable Set Register 0 | 4281 0080h |
C0h | WKUP_VTM_SEC_ENABLE_CLR_REG0 | Interrupt Enable Clear Register 0 | 4281 00C0h |
13Ch | WKUP_VTM_DED_EOI_REG | EOI Register | 4281 013Ch |
140h | WKUP_VTM_DED_STATUS_REG0 | Interrupt Status Register 0 | 4281 0140h |
180h | WKUP_VTM_DED_ENABLE_SET_REG0 | Interrupt Enable Set Register 0 | 4281 0180h |
1C0h | WKUP_VTM_DED_ENABLE_CLR_REG0 | Interrupt Enable Clear Register 0 | 4281 01C0h |
200h | WKUP_VTM_AGGR_ENABLE_SET | AGGR interrupt enable set Register | 4281 0200h |
204h | WKUP_VTM_AGGR_ENABLE_CLR | AGGR interrupt enable clear Register | 4281 0204h |
208h | WKUP_VTM_AGGR_STATUS_SET | AGGR interrupt status set Register | 4281 0208h |
20Ch | WKUP_VTM_AGGR_STATUS_CLR | AGGR interrupt status clear Register | 4281 020Ch |
WKUP_VTM_REV is shown in Figure 5-693 and described in Table 5-1443.
Return to Summary Table.
Revision parameters
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1Dh | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | bu |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 1Dh | RTL version |
10-8 | REVMAJ | R | 2h | Major version |
7-6 | CUSTOM | R | 0h | Custom version |
5-0 | REVMIN | R | 0h | Minor version |
WKUP_VTM_VECTOR is shown in Figure 5-694 and described in Table 5-1445.
Return to Summary Table.
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R/W-X | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R/W-X | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | X | |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R/W | X | |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
WKUP_VTM_STAT is shown in Figure 5-695 and described in Table 5-1447.
Return to Summary Table.
Misc Status
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-X | R-4h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | X | |
10-0 | NUM_RAMS | R | 4h | Indicates the number of RAMS serviced by the ECC aggregator |
WKUP_VTM_RESERVED_SVBUS_y is shown in Figure 5-696 and described in Table 5-1449.
Return to Summary Table.
Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets.
Offset = 10h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 0010h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Serial VBUS register data |
WKUP_VTM_SEC_EOI_REG is shown in Figure 5-697 and described in Table 5-1451.
Return to Summary Table.
EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register |
WKUP_VTM_SEC_STATUS_REG0 is shown in Figure 5-698 and described in Table 5-1453.
Return to Summary Table.
Interrupt Status Register 0
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND | ECCAGG_PEND | |||
R/W-X | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend |
2 | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend |
1 | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend |
0 | ECCAGG_PEND | R/W1S | 0h | Interrupt Pending Status for eccagg_pend |
WKUP_VTM_SEC_ENABLE_SET_REG0 is shown in Figure 5-699 and described in Table 5-1455.
Return to Summary Table.
Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET | ECCAGG_ENABLE_SET | |||
R/W-X | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend |
2 | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend |
1 | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend |
0 | ECCAGG_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for eccagg_pend |
WKUP_VTM_SEC_ENABLE_CLR_REG0 is shown in Figure 5-700 and described in Table 5-1457.
Return to Summary Table.
Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 00C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR | ECCAGG_ENABLE_CLR | |||
R/W-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend |
2 | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend |
1 | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend |
0 | ECCAGG_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for eccagg_pend |
WKUP_VTM_DED_EOI_REG is shown in Figure 5-701 and described in Table 5-1459.
Return to Summary Table.
EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 013Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register |
WKUP_VTM_DED_STATUS_REG0 is shown in Figure 5-702 and described in Table 5-1461.
Return to Summary Table.
Interrupt Status Register 0
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 0140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND | ECCAGG_PEND | |||
R/W-X | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend |
2 | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend |
1 | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend |
0 | ECCAGG_PEND | R/W1S | 0h | Interrupt Pending Status for eccagg_pend |
WKUP_VTM_DED_ENABLE_SET_REG0 is shown in Figure 5-703 and described in Table 5-1463.
Return to Summary Table.
Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 0180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET | ECCAGG_ENABLE_SET | |||
R/W-X | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend |
2 | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend |
1 | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend |
0 | ECCAGG_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for eccagg_pend |
WKUP_VTM_DED_ENABLE_CLR_REG0 is shown in Figure 5-704 and described in Table 5-1465.
Return to Summary Table.
Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 01C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR | ECCAGG_ENABLE_CLR | |||
R/W-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend |
2 | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend |
1 | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend |
0 | ECCAGG_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for eccagg_pend |
WKUP_VTM_AGGR_ENABLE_SET is shown in Figure 5-705 and described in Table 5-1467.
Return to Summary Table.
AGGR interrupt enable set Register
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 0200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1S | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | interrupt enable set for parity errors |
WKUP_VTM_AGGR_ENABLE_CLR is shown in Figure 5-706 and described in Table 5-1469.
Return to Summary Table.
AGGR interrupt enable clear Register
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 0204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1C | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | interrupt enable clear for parity errors |
WKUP_VTM_AGGR_STATUS_SET is shown in Figure 5-707 and described in Table 5-1471.
Return to Summary Table.
AGGR interrupt status set Register
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 0208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R/W = Read/Write; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wincr | 0h | interrupt status set for svbus timeout errors |
1-0 | PARITY | R/Wincr | 0h | interrupt status set for parity errors |
WKUP_VTM_AGGR_STATUS_CLR is shown in Figure 5-708 and described in Table 5-1473.
Return to Summary Table.
AGGR interrupt status clear Register
Instance | Physical Address |
---|---|
WKUP_VTM0_ECCAGGR_CFG | 4281 020Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R/W = Read/Write; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wdecr | 0h | interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/Wdecr | 0h | interrupt status clear for parity errors |