SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes MCU_CTRL_MMR0 and MCU_SEC_MMR0 integration in the device, including information about clocks, resets, and hardware requests.
One MCU_CTRL_MMR0 and one MCU_SEC_MMR0 modules are integrated in the device MCU domain. Figure 5-227 shows their integration.
Table 5-461 through Table 5-463 summarize the integration of the MCU_CTRL_MMR0 and MCU_SEC_MMR0 modules in the device MCU domain.
Module Instance | Attributes | ||||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | ||
MCU_CTRL_MMR0 MCU_SEC_MMR0 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
MCU_CTRL_MMR0 | MCU_CTRL_MMR0_FICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | Functional and interface clock for the MCU_CTRL_MMR0 module with frequency equal to MCU_SYSCLK0 divided by 6. |
MCU_SEC_MMR0 | MCU_SEC_MMR0_FICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | Functional and interface clock for the MCU_SEC_MMR0 module with frequency equal to MCU_SYSCLK0 divided by 6. |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
MCU_CTRL_MMR0 | MCU_CTRL_MMR0_RST | MOD_G_RST | LPSC0 | Module level main reset |
MCU_CTRL_MMR0_POR_RST | MOD_POR_RST | LPSC0 | Module power-on reset | |
MCU_SEC_MMR0 | MCU_SEC_MMR0_RST | MOD_G_RST | LPSC0 | MCU_SEC_MMR0 module reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
MCU_CTRL_MMR0 | MCU_CTRL_MMR0_ACCESS_ERR_0 | GIC500_SPI_IN_781 | GIC500 | Interrupt indicating protection, addressing, lock violation. | Level |
WKUP_DMSC0_INTR_IN_43 | WKUP_DMSC0 | ||||
R5FSS0_CORE0_INTR_IN_480 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_480 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_46 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_46 | MCU_R5FSS0_CORE1 | ||||
MCU_CTRL_MMR0_IPC_SET0_IPC_SET_IPCFG_0 | MCU_R5FSS0_CORE0_INTR_IN_44 | MCU_R5FSS0_CORE0 | Interrupt generated by writing 1h to CTRLMMR_MCU_IPC_SET0[0]. | Level | |
MCU_R5FSS0_CORE1_INTR_IN_44 | MCU_R5FSS0_CORE1 | ||||
MCU_CTRL_MMR0_IPC_SET1_IPC_SET_IPCFG_0 | MCU_R5FSS0_CORE0_INTR_IN_45 | MCU_R5FSS0_CORE0 | Interrupt generated by writing 1h to CTRLMMR_MCU_IPC_SET1[0]. | Level | |
MCU_R5FSS0_CORE1_INTR_IN_45 | MCU_R5FSS0_CORE1 | ||||
MCU_CTRL_MMR0_IPC_SET8_IPC_SET_IPCFG_0 | WKUP_DMSC0_INTR_IN_42 | WKUP_DMSC0 | Interrupt generated by writing 1h to CTRLMMR_MCU_IPC_SET8[0]. | Level | |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
MCU_CTRL_MMR0 | - | - | - | - | - |
For more information about MCU_CTRL_MMR0_ACCESS_ERR_0, see Section 5.1.2.3.1.2.
For more information about MCU_IPC_INTx, see Section 5.1.2.3.1.3.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.