SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The General-Purpose Input/Output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an output, the user can write to an internal register to control the state driven on the output pin. When configured as an input, user can obtain the state of the input by reading the state of an internal register.
In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different interrupt/event generation modes.
The device has six instances of GPIO modules. The GPIO modules are integrated in two groups.
The corresponding groups I/O pins are multiplexed within each group modules.
The GPIO pins are grouped into banks (16 pins per bank and 9 banks per module), which means that each GPIO module provides up to 144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 288 (2 group instances × (9 banks × 16 pins)) I/O pins. Since WKUP_GPIOu_[32:42], WKUP_GPIOu_[82:83], WKUP_GPIOu_[85:143] (u = 0, 1), and GPIOn_[69:143] (n = 0, 2, 4, 6) are reserved in this device, general purpose interface supports up to 141 I/O pins.
Table 12-108 shows GPIO modules allocation across device domains.
Instance | Domain | ||
WKUP | MCU | MAIN | |
WKUP_GPIO0 | ✓ | - | - |
WKUP_GPIO1 | ✓ | - | - |
GPIO0 | - | - | ✓ |
GPIO2 | - | - | ✓ |
GPIO4 | - | - | ✓ |
GPIO6 | - | - | ✓ |
Figure 12-53 presents the GPIO modules overview.