SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes module integration in the device, including information about clocks, resets, and hardware requests.
This section describes the Secure Proxy integration in the main Navigator subsystem (NAVSS0). For MCU_NAVSS0_SEC_PROXY0 integration, please see MCU Navigator Subsystem (MCU_NAVSS).
Figure 10-185 shows the Secure Proxy integration in the NAVSS
Table 10-501 and Table 10-502 summarize the integration of the module in the device.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
NAVSS0_SEC_PROXY0 | PSC0 | GP | LPSC0 | MODSS_CBASS |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
NAVSS0_SEC_PROXY0 | SEC_PROXY0_FICLK | MODSS_VBUS_D2_CLK | MAIN_SYSCLK0 | Proxy clock. This clock is used for all interface and functional operations. |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
NAVSS0_SEC_PROXY0 | SEC_PROXY0_RST | MODSS_RST | LPSC0 | Proxy hardware reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
NAVSS0_SEC_PROXY0 | - | - | - | No interrupts to external interrupt controllers | - |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
NAVSS0_SEC_PROXY0 | - | - | - | No PDMA channels to external DMA engines | - |