SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 11-104 lists the memory-mapped registers for the TIMERMGR_CFG_OES. All register offset addresses not listed in Table 11-104 should be considered as reserved locations and the register contents should not be modified.
Event index MMR definitions
Instance | Base Address |
---|---|
NAVSS0_TIMERMGR0_CFG_OES | 30F0 0000h |
NAVSS0_TIMERMGR1_CFG_OES | 30F0 1000h |
Offset | Acronym | Register Name | NAVSS0_TIMERMGR0_CFG_OES Physical Address | NAVSS0_TIMERMGR1_CFG_OES Physical Address |
---|---|---|---|---|
0h + formula | TIMERMGR_EVENTIDX_y | Programs the event index for a given timer | 30F0 0000h + formula | 30F0 1000h + formula |
TIMERMGR_EVENTIDX_y is shown in Figure 11-53 and described in Table 11-106.
Return to Summary Table.
This programs the event index for a given timer
Offset = 0h + (y * 4h); where y = 0h to 3FFh
Instance | Physical Address |
---|---|
NAVSS0_TIMERMGR0_CFG_OES | 30F0 0000h |
NAVSS0_TIMERMGR1_CFG_OES | 30F0 1000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL | ||||||||||||||||||||||||||||||
R/W-X | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | VAL | R/W | FFFFh | The event index for a given timer to be used on the output event interface |