SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes PCIe subsystem integration in the device MAIN domain, including information about clocks, resets, and hardware requests.
There is one PCIe subsystem integrated in the device MAIN domain: PCIE1. Figure 12-1260 shows the integration of PCIE1.
Table 12-2456 through Table 12-2458 summarize the integration of PCIE1 in the device MAIN domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
PCIE1 | PSC0 | PD0 | LPSC29 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
PCIE1 | PCIE1_FICLK | SYSCLK0 / 2 | PLLCTRL0 | PCIE1 interface bus clock (CBA_CLK). |
PCIE1_PM_CLK | CLK_12M_RC | RCOSC | PCIE1 core free-running clock used for low power state transitions and clock control generation. | |
MAIN_PLL3_HSDIV1_CLKOUT | PLL3_HSDIV | PCIE1 CPTS reference clock (RCLK). The CPTS RCLK clock frequency should be greater than or equal to the PCIE CBA_CLK clock frequency. Otherwise, the software will have to add some wait cycles before a correct event is generated by the CPTS module. Additionally, the CPTS RCLK should be set to same frequency as the PCIe core clock. The selection of the source signal (see PCIe Subsystem Integration) can be done via the CTRLMMR_PCIE1_CLKSEL[3-0] CPTS_CLKSEL register field in the device Control Module. | ||
MAIN_PLL0_HSDIV6_CLKOUT | PLL0_HSDIV | |||
MCU_CPTS_RFT_CLK | I/O pin | |||
CPTS_RFT_CLK | I/O pin | |||
MCU_EXT_REFCLK0 | I/O pin | |||
PCIE1_CPTS_RCLK | EXT_REFCLK1 | I/O pin | ||
SERDES0_IP2_LN0_TXMCLK | SERDES0 | |||
SERDES0_IP2_LN1_TXMCLK | SERDES0 | |||
SERDES0_IP2_LN2_TXMCLK | SERDES0 | |||
SERDES0_IP2_LN3_TXMCLK | SERDES0 | |||
MCU_PLL2_HSDIV1_CLKOUT | MCU_PLL2_HSDIV1 | |||
MAIN_SYSCLK0 | PLLCTRL0 | |||
PCIE1_LANE0_TXMCLK | SERDES0_IP2_LN0_TXMCLK | SERDES0 | PCIE1 core clock (CORE_CLK) driven by SERDES via lane 0. In multi-lane modes, only PCIE1_LANE0_TXMCLK is used as the core clock input for all lanes. The TXMCLKs for the rest of the lanes are left unconnected, as shown in Figure 12-1260. | |
PCIE1_LANE0_RXCLK | SERDES0_IP2_LN0_RXCLK | SERDES0 | PCIE1 PIPE interface clock driven by SERDES via lane 0. In multi-lane modes, only PCIE1_LANE0_RXCLK is used as the PIPE interface clock for all lanes. The RXCLKs for the rest of the lanes are left unconnected, as shown in Figure 12-1260. | |
SERDES0 | SERDES0_IP2_LN0_TXCLK | PCIE1_LANE0_TXCLK | PCIE1 | PCIE1 lane 0 PIPE/RAW TX return clock. |
SERDES0_IP2_LN1_TXCLK | PCIE1_LANE1_TXCLK | PCIE1 lane 1 PIPE/RAW TX return clock. | ||
SERDES0_IP2_LN2_TXCLK | PCIE1_LANE2_TXCLK | PCIE1 lane 2 PIPE/RAW TX return clock. | ||
SERDES0_IP2_LN3_TXCLK | PCIE1_LANE3_TXCLK | PCIE1 lane 3 PIPE/RAW TX return clock. | ||
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
PCIE1 | PCIE1_RST | MOD_G_RST | LPSC29 | PCIE1 reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
PCIE1 | PCIE1_DOWNSTREAM_PULSE_0 | GIC500_SPI_IN_357 | COMPUTE_CLUSTER0 | PCIE1 downstream interrupt | Pulse |
R5FSS0_CORE0_INTR_IN_302 | R5FSS0_CORE0 | Pulse | |||
R5FSS0_CORE1_INTR_IN_302 | R5FSS0_CORE1 | Pulse | |||
MAIN2MCU_PLS_INTRTR0_IN_40 | MAIN2MCU_PLS_INTRTR0 | Pulse | |||
PCIE1_ERROR_PULSE_0 | GIC500_SPI_IN_361 | COMPUTE_CLUSTER0 | PCIE1 error interrupt | Pulse | |
R5FSS0_CORE0_INTR_IN_306 | R5FSS0_CORE0 | Pulse | |||
R5FSS0_CORE1_INTR_IN_306 | R5FSS0_CORE1 | Pulse | |||
MAIN2MCU_PLS_INTRTR0_IN_42 | MAIN2MCU_PLS_INTRTR0 | Pulse | |||
PCIE1_FLR_PULSE_0 | GIC500_SPI_IN_358 | COMPUTE_CLUSTER0 | PCIE1 function level interrupt | Pulse | |
R5FSS0_CORE0_INTR_IN_303 | R5FSS0_CORE0 | Pulse | |||
R5FSS0_CORE1_INTR_IN_303 | R5FSS0_CORE1 | Pulse | |||
MAIN2MCU_PLS_INTRTR0_IN_41 | MAIN2MCU_PLS_INTRTR0 | Pulse | |||
PCIE1_HOT_RESET_PULSE_0 | GIC500_SPI_IN_365 | COMPUTE_CLUSTER0 | PCIE1 hot reset interrupt | Pulse | |
R5FSS0_CORE0_INTR_IN_310 | R5FSS0_CORE0 | Pulse | |||
R5FSS0_CORE1_INTR_IN_310 | R5FSS0_CORE1 | Pulse | |||
MAIN2MCU_PLS_INTRTR0_IN_46 | MAIN2MCU_PLS_INTRTR0 | Pulse | |||
PCIE1_LEGACY_PULSE_0 | GIC500_SPI_IN_356 | COMPUTE_CLUSTER0 | PCIE1 legacy interrupt | Pulse | |
R5FSS0_CORE0_INTR_IN_301 | R5FSS0_CORE0 | Pulse | |||
R5FSS0_CORE1_INTR_IN_301 | R5FSS0_CORE1 | Pulse | |||
MAIN2MCU_PLS_INTRTR0_IN_39 | MAIN2MCU_PLS_INTRTR0 | Pulse | |||
PCIE1_LINK_STATE_PULSE_0 | GIC500_SPI_IN_362 | COMPUTE_CLUSTER0 | PCIE1 link state interrupt | Pulse | |
R5FSS0_CORE0_INTR_IN_307 | R5FSS0_CORE0 | Pulse | |||
R5FSS0_CORE1_INTR_IN_307 | R5FSS0_CORE1 | Pulse | |||
MAIN2MCU_PLS_INTRTR0_IN_43 | MAIN2MCU_PLS_INTRTR0 | Pulse | |||
PCIE1_LOCAL_LEVEL_0 | GIC500_SPI_IN_360 | COMPUTE_CLUSTER0 | PCIE1 local interrupt | Level | |
R5FSS0_CORE0_INTR_IN_305 | R5FSS0_CORE0 | Level | |||
R5FSS0_CORE1_INTR_IN_305 | R5FSS0_CORE1 | Level | |||
MAIN2MCU_LVL_INTRTR0_IN_74 | MAIN2MCU_LVL_INTRTR0 | Level | |||
PCIE1_PWR_STATE_PULSE_0 | GIC500_SPI_IN_363 | COMPUTE_CLUSTER0 | PCIE1 power state interrupt | Pulse | |
R5FSS0_CORE0_INTR_IN_308 | R5FSS0_CORE0 | Pulse | |||
R5FSS0_CORE1_INTR_IN_308 | R5FSS0_CORE1 | Pulse | |||
MAIN2MCU_PLS_INTRTR0_IN_44 | MAIN2MCU_PLS_INTRTR0 | Pulse | |||
PCIE1_PHY_LEVEL_0 | GIC500_SPI_IN_359 | COMPUTE_CLUSTER0 | PCIE1 PHY interrupt | Level | |
R5FSS0_CORE0_INTR_IN_304 | R5FSS0_CORE0 | Level | |||
R5FSS0_CORE1_INTR_IN_304 | R5FSS0_CORE1 | Level | |||
MAIN2MCU_LVL_INTRTR0_IN_73 | MAIN2MCU_LVL_INTRTR0 | Level | |||
GIC500_SPI_IN_364 | COMPUTE_CLUSTER0 | Pulse | |||
PCIE1_PTM_VALID_PULSE_0 | R5FSS0_CORE0_INTR_IN_309 | R5FSS0_CORE0 | PCIE1 PTM valid interrupt | Pulse | |
R5FSS0_CORE1_INTR_IN_309 | R5FSS0_CORE1 | Pulse | |||
MAIN2MCU_PLS_INTRTR0_IN_45 | MAIN2MCU_PLS_INTRTR0 | Pulse | |||
PCIE1_ECC0_CORR_LEVEL_0 | ESM_LVL_IN_373 | PCIE1 ECC AGGR 0 correctable error interrupt | Level | ||
PCIE1_ECC0_UNCORR_LEVEL_0 | ESM_LVL_IN_374 | PCIE1 ECC AGGR 0 uncorrectable error interrupt | Level | ||
PCIE1_ECC1_UNCORR_LEVEL_0 | ESM_LVL_IN_375 | ESM0 | PCIE1 ECC AGGR 1 uncorrectable error interrupt | Level | |
PCIE1_ASF_NONFATAL_LEVEL_0 | ESM_LVL_IN_376 | PCIE1 active internal diagnostics interrupt | Level | ||
PCIE1_ASF_FATAL_LEVEL_0 | ESM_LVL_IN_377 | PCIE1 active internal diagnostics interrupt | Level | ||
GIC500_SPI_IN_366 | COMPUTE_CLUSTER0 | Level | |||
PCIE1_CPTS_PEND_0 | R5FSS0_CORE0_INTR_IN_311 | R5FSS0_CORE0 | PCIE1 timesync interrupt | Level | |
R5FSS0_CORE1_INTR_IN_311 | R5FSS0_CORE1 | Level | |||
MAIN2MCU_LVL_INTRTR0_IN_75 | MAIN2MCU_LVL_INTRTR0 | Level | |||
GIC500_SPI_IN_667 | COMPUTE_CLUSTER0 | Pulse | |||
PCIE1_DPA_PULSE_0 | R5FSS0_CORE0_INTR_IN_312 | R5FSS0_CORE0 | PCIE1 dynamic power allocation interrupt | Pulse | |
R5FSS0_CORE1_INTR_IN_312 | R5FSS0_CORE1 | Pulse | |||
MAIN2MCU_PLS_INTRTR0_IN_47 | MAIN2MCU_PLS_INTRTR0 | Pulse | |||
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
PCIE1 | - | - | - | The PCIe subsystem does not provide built-in DMA capabilities | - |
Time Sync and Compare Events (Output) | |||||
Module Instance | Module Event | Destination Event Input | Destination | Description | Type |
PCIE1 | PCIE1_CPTS_HW1_PUSH_0 | TIMESYNC_INTRTR0_IN_21 | TIMESYNC_INTRTR0 | PCIE1 CPTS hardware push event (HW1_TS_PUSH) | Edge |
PCIE1_CPTS_COMP_0 | CMPEVENT_INTRTR0_IN_5 | CMPEVENT_INTRTR0 | PCIE1 CPTS compare output interrupt | Edge | |
PCIE1_CPTS_SYNC_0 | TIMESYNC_INTRTR0_IN_33 | TIMESYNC_INTRTR0 | PCIE1 CPTS sync output interrupt | Edge | |
PCIE1_CPTS_GENF_0 | TIMESYNC_INTRTR0_IN_11 | TIMESYNC_INTRTR0 | PCIE1 CPTS GENF0 output interrupt | Edge | |
Time Sync Events (Input) | |||||
Module Instance | Module Event | Source Event Output | Source | Description | Type |
PCIE1 | PCIE1_CPTS_HW2_PUSH_0 | TIMESYNC_INTRTR0_OUTL_21 | TIMESYNC_INTRTR0 | PCIE1 CPTS hardware time stamp push event (HW2_TS_PUSH) | Edge |