SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 11-108 lists the memory-mapped registers for the TIMERMGR_CFG_TIMERS. All register offset addresses not listed in Table 11-108 should be considered as reserved locations and the register contents should not be modified.
Timers MMR definitions - runtime region
Instance | Base Address |
---|---|
NAVSS0_TIMERMGR0_CFG_TIMERS | 3220 0000h |
NAVSS0_TIMERMGR1_CFG_TIMERS | 3224 0000h |
Offset | Acronym | Register Name | NAVSS0_TIMERMGR0_CFG_TIMERS Physical Address | NAVSS0_TIMERMGR1_CFG_TIMERS Physical Address |
---|---|---|---|---|
0h + formula | TIMERMGR_SETUP_j_k | This reprograms timer N with the written value | 3220 0000h + formula | 3224 0000h + formula |
4h + formula | TIMERMGR_CONTROL_j_k | Modifies the behavior of timer N | 3220 0004h + formula | 3224 0004h + formula |
TIMERMGR_SETUP_j_k is shown in Figure 11-54 and described in Table 11-110.
Return to Summary Table.
This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires, if timer N and the timer manager itself are both enabled via TIMERMGR_CNTL and TIMERMGR_CONTROL_j_k
Offset = 0h + (j * 1000h) + (k * 100h); where j = 0h to 3Fh, k = 0h to Fh
Instance | Physical Address |
---|---|
NAVSS0_TIMERMGR0_CFG_TIMERS | 3220 0000h + formula |
NAVSS0_TIMERMGR1_CFG_TIMERS | 3224 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COUNT | R/W | 0h |
The number of ticks of the timer_clock before this timer would expire when reprogrammed |
TIMERMGR_CONTROL_j_k is shown in Figure 11-55 and described in Table 11-112.
Return to Summary Table.
Modifies the behavior of timer N with control signals below
Offset = 4h + (j * 1000h) + (k * 100h); where j = 0h to 3Fh, k = 0h to Fh
Instance | Physical Address |
---|---|
NAVSS0_TIMERMGR0_CFG_TIMERS | 3220 0004h + formula |
NAVSS0_TIMERMGR1_CFG_TIMERS | 3224 0004h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | AUTORESET | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXPIRED | SET | ENABLE | ||||
R/W-X | R-0h | W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R/W | X | |
8 | AUTORESET | R/W | 0h | Automatically reset the timer when it expires. Provides the option of a periodic timer, rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers, so the expirations can occur regularly without software reprogramming them. |
7-3 | RESERVED | R/W | X | |
2 | EXPIRED | R | 0h | The status of the current timer. 1 = expired |
1 | SET | W | 0h | This may be used to touch/set a timer. When a 1 is written, the corresponding timer will be refreshed with the current value in its TIMERMGR_SETUP_j_k register. Will always read 0 |
0 | ENABLE | R/W | 0h | Write 1 to enable, 0 to disable the timer. |