SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
MCU_FSS0_HPB0_MC_MTR_y
MCU_FSS0_HPB0_MC_MTR_y
Table 12-4065 lists the memory-mapped registers for the HyperBus interface (MCU_FSS0_HPB0) Subsystem. All register offset addresses not listed in Table 12-4065 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_FSS0_HPB_SS_CFG | 4703 0000h |
Offset | Acronym | Register Name | MCU_FSS0_HPB_SS_CFG Physical Address |
---|---|---|---|
0h | MCU_FSS0_HPB0_SS_REVISION_REG | Revision Register | 4703 0000h |
4h | MCU_FSS0_HPB0_SS_DLL_STAT_REG | DLL Status Register | 4703 0004h |
8h | MCU_FSS0_HPB0_SS_RAM_STAT_REG | RAM Status Register | 4703 0008h |
MCU_FSS0_HPB0_SS_REVISION_REG is shown in Figure 12-2046 and described in Table 12-4067.
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Revision Register
The Revision Register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_SS_CFG | 4703 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODID | |||||||||||||||
R-6860h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1Ch | R-1h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODID | R | 6860h | Module ID |
15-11 | REVRTL | R | 1Ch | RTL Revision |
10-8 | REVMAJ | R | 1h | Major Revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | REVMIN | R | 0h | Minor Revision |
MCU_FSS0_HPB0_SS_DLL_STAT_REG is shown in Figure 12-2047 and described in Table 12-4069.
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DLL Status Register
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_SS_CFG | 4703 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MDLL_CODE | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDLL_CODE | SDL_LOCK | MDLL_LOCK | |||||
R-0h | R-0h | R-0h | |||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-2 | MDLL_CODE | R | 0h | MDLL Code The slave delay line length that is currently enabled is determined by the MDLL Code value. |
1 | SDL_LOCK | R | 0h | MDLL Code Valid |
0 | MDLL_LOCK | R | 0h | MDLL Lock When this bit is set, it indicates that the master delay line in the MDLL is locked. |
MCU_FSS0_HPB0_SS_RAM_STAT_REG is shown in Figure 12-2048 and described in Table 12-4071.
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RAM Status Register
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_SS_CFG | 4703 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INIT_DONE | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | INIT_DONE | R | 0h | FIFO RAM Initialization Done When this bit is set, it indicates that all the FIFO RAM auto initialization is complete. Software should check that this bit is set before initiating transactions to the external memory. |
Table 12-4073 lists the memory-mapped registers for the HyperBus interface (MCU_FSS0_HPB0) Memory Controller. All register offset addresses not listed in Table 12-4073 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_FSS0_HPB_CTRL | 4703 4000h |
Offset | Acronym | Register Name | MCU_FSS0_HPB_CTRL Physical Address |
---|---|---|---|
0h | MCU_FSS0_HPB0_MC_CSR | Controller Status Register | 4703 4000h |
4h | MCU_FSS0_HPB0_MC_IER | Interrupt Enable Register | 4703 4004h |
8h | MCU_FSS0_HPB0_MC_ISR | Interrupt Status Register | 4703 4008h |
10h + formula | MCU_FSS0_HPB0_MC_MBAR_y | Memory Base Address Register | 4703 4010h to 4703 4014h |
20h + formula | MCU_FSS0_HPB0_MC_MCR_y | Memory Configuration Register | 4703 4020h to 4703 4024h |
30h + formula | MCU_FSS0_HPB0_MC_MTR_y | Memory Timing Register | 4703 4030h to 4703 4034h |
40h | MCU_FSS0_HPB0_MC_GPOR | General Purpose Output Register(1) | 4703 4040h |
44h | MCU_FSS0_HPB0_MC_WPR | Write Protection Register | 4703 4044h |
48h | MCU_FSS0_HPB0_MC_LBR | Loop Back Register | 4703 4048h |
MCU_FSS0_HPB0_MC_CSR is shown in Figure 12-2049 and described in Table 12-4075.
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Controller Status Register
The Controller Status Register is used to access the internal status of the HBMC.
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_CTRL | 4703 4000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | WRSTOERR | WTRSERR | WDECERR | ||||
R-0h | R-0h | R-0h | R-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | WACT | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RDSSTALL | RRSTOERR | RTRSERR | RDECERR | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RACT | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Reserved |
26 | WRSTOERR | R | 0h | Write RSTO Error This bit indicates whether HyperBus memory is under reset state in the latest write operation. When this bit is set, HBMC responds by AXI SLVERR. 0h = Normal operation 1h = HyperBus memory is under reset |
25 | WTRSERR | R | 0h | Write Transaction Error This bit indicates whether AXI protocol is acceptable by HBMC in the latest write transaction. When this bit is set, HBMC responds by AXI SLVERR. 0h = Normal operation 1h = This protocol is not supported |
24 | WDECERR | R | 0h | Write Decode Error This bit indicates whether access address is acceptable in the latest write transaction. When this bit is set, HBMC responds by AXI DECERR. 0h = Normal operation 1h = Access address is not reachable |
23-17 | RESERVED | R | 0h | Reserved |
16 | WACT | R | 0h | Write Active This bit indicates whether write transaction is in progress or not. When receiving write request on write address channel, this bit becomes 1h. When retrieving response signaling on write response channel, this bit becomes 0h. 0h = Write is idle 1h = Write is active |
15-12 | RESERVED | R | 0h | Reserved |
11 | RDSSTALL | R | 0h | RDS Stall This bit indicates whether read data transfer from HyperBus memory is stalled (RDS Stall remains LOW) in the latest read transaction. When this bit is set, HBMC responds by AXI SLVERR. 0h = Normal operation 1h = RDS is stalled |
10 | RRSTOERR | R | 0h | Read RSTO Error This bit indicates whether HyperBus memory is under reset state in the latest read operation. When this bit is set, HBMC responds by AXI SLVERR. 0h = Normal operation 1h = HyperBus memory is under reset |
9 | RTRSERR | R | 0h | Read Transaction Error This bit indicates whether AXI protocol is acceptable by HBMC in the latest read transaction. When this bit is set, HBMC responds by AXI SLVERR. 0h = Normal operation 1h = This protocol is not supported |
8 | RDECERR | R | 0h | Read Decode Error This bit indicates whether access address is acceptable in the latest read transaction. When this bit is set, HBMC responds by AXI DECERR. 0h = Normal operation 1h = Access address is not reachable |
7-1 | RESERVED | R | 0h | Reserved |
0 | RACT | R | 0h | Read Active This bit indicates whether read transaction is in progress or not. When receiving read request on read address channel, this bit becomes 1h. When retrieving all requested data on read data channel, this bit becomes 0h. 0h = Read is idle 1h = Read is active |
MCU_FSS0_HPB0_MC_IER is shown in Figure 12-2050 and described in Table 12-4077.
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Interrupt Enable Register
The HBMC outputs optional interrupt signal by condition enabled by the Interrupt Enable Register.
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_CTRL | 4703 4004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
INTP | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCINTE | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | INTP | R/W | 0h | Interrupt Polarity Control This bit is used to choose the polarity of optional interrupt signal (IENOn). 0h = IENOn signal is active low 1h = IENOn signal is active high (Reversed mode) |
30-1 | RESERVED | R | 0h | Reserved |
0 | RPCINTE | R/W | 0h | HyperBus Memory Interrupt Enable 0h = Disable interrupt 1h = Enable interrupt by INT# signal of HyperBus memory |
MCU_FSS0_HPB0_MC_ISR is shown in Figure 12-2051 and described in Table 12-4079.
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Interrupt Status Register
The Interrupt Status Register is used to read the status for the interrupts generated.
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_CTRL | 4703 4008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCINTS | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RPCINTS | R | 0h | HyperBus Memory Interrupt 0h = No interrupt 1h = This bit displays interrupt from INT# signal of HyperBus memory |
MCU_FSS0_HPB0_MC_MBAR_y is shown in Figure 12-2052 and described in Table 12-4081.
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Memory Base Address Register
for device connected to CS#
The base address of addressable region to Hyperflash memory can be set-up using this register. The controller can't assert two chip selects CS0# and CS1# at a time. Hence this register describes how to select chip select.
Offset = 10h + (y × 4h); where y = 0h to 1h
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_CTRL | 4703 4010h to 4703 4014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
A_MSB | A_LSB | ||||||||||||||||||||||||||||||
R/W-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | A_MSB | R/W | 0h | MSB 8 bit of the base address of addressable region to HyperBus memory |
23-0 | A_LSB | R | 0h | Since register can be set in 16 MB boundary, lower 24 bit is fixed to 0h, if read, this field will always return 0h. |
MCU_FSS0_HPB0_MC_MCR_y is shown in Figure 12-2053 and described in Table 12-4083.
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Memory Configuration Register
for CS#
Offset = 20h + (y × 4h); where y = 0h to 1h
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_CTRL | 4703 4020h to 4703 4024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
MAXEN | RESERVED | MAXLEN | |||||
R/W-0h | R-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MAXLEN | TCMO | ACS | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRT | DEVTYPE | RESERVED | WRAPSIZE | |||
R-0h | R/W-0h | R/W-0h | R-0h | R/W-3h | |||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | MAXEN | R/W | 0h | Maximum Length Enable When this bit is set to 1h, CS# low time can be configurable by MAXLEN bit. 0h = No configurable CS# low time 1h = Configurable CS# low time |
30-27 | RESERVED | R | 0h | Reserved |
26-18 | MAXLEN | R/W | 0h | Maximum Length This bit indicates maximum read/write transaction length to memory. This bit is ignored when MAXEN bit is 0h. 0h = 2 Byte (1 HyperBus CK) 1h = 4 Byte (2 HyperBus CK) 2h = 6 Byte (3 HyperBus CK) .... 1FFh = 1024 Byte (512 HyperBus CK) |
17 | TCMO | R/W | 0h | True Continuous Merge Option Note that this function can be used with the HyperFlash with specific function. Please confirm whether it is available on the corresponding HyperFlash before enabling this function. When HyperBus memory doesn't accept the 8-bit boundary address, and a wrapping burst access with ARSIZE = 0h and ARADDR0 = 1h is used, this bit must not be set to 1h. 0h = No merging WRAP and INCR 1h = Merging WRAP and INCR |
16 | ACS | R/W | 0h | Asymmetry Cache Support This function should be disabled if the HyperBus memory itself supports the asymmetry cache system. 0h = No asymmetry cache system support 1h = Asymmetry cache system support |
15-6 | RESERVED | R | 0h | Reserved |
5 | CRT | R/W | 0h | Configuration Register Target This bit indicates whether the read or write operation accesses the memory or CR space. This bit is mapped to CA-46 bit in HyperRAM. When using HyperFlash, this bit should be set to 0h. 0h = Memory space 1h = CR space |
4 | DEVTYPE | R/W | 0h | Device Type Device type for control target. 0h = HyperFlash 1h = HyperRAM |
3-2 | RESERVED | R | 0h | Reserved |
1-0 | WRAPSIZE | R/W | 3h | Wrap Size The wrap burst length of HyperBus memory. This bit is ignored when the asymmetry cache support bit is 0h. When the asymmetry cache support is 1h, this bit should be set the same as wrap size of configuration register in HyperBus memory. 0h = Reserved 1h = 64 Bytes 2h = 16 Bytes 3h = 32 Bytes |
MCU_FSS0_HPB0_MC_MTR_y is shown in Figure 12-2054 and described in Table 12-4085.
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Memory Timing Register
Memory access timings for CS# can be configured using the Memory Timing Register.
Offset = 30h + (y × 4h); where y = 0h to 1h
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_CTRL | 4703 4030h to 4703 4034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RCSHI | WCSHI | RCSS | WCSS | ||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RCSH | WCSH | RESERVED | LTCY | ||||||||||||
R/W-0h | R/W-0h | R-0h | R/W-1h | ||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RCSHI | R/W | 0h | Read Chip Select High Between Operations This bit indicates CS# high time for read between operations. 0h = corresponds to 1.5 clock cycle Fh = corresponds to 16.5 clock cycle |
27-24 | WCSHI | R/W | 0h | Write Chip Select High Between Operations This bit indicates CS# high time for write between operations. 0h = corresponds to 1.5 clock cycle Fh = corresponds to 16.5 clock cycle |
23-20 | RCSS | R/W | 0h | Read Chip Select Setup to next CK rising edge This bit indicates CS# setup time for read from CS# assertion. 0h = corresponds to 1 clock cycle Fh = corresponds to 16 clock cycle |
19-16 | WCSS | R/W | 0h | Write Chip Select Setup to next CK rising edge This bit indicates CS# setup time for write from CS# assertion. 0h = corresponds to 1 clock cycle Fh = corresponds to 16 clock cycle |
15-12 | RCSH | R/W | 0h |
NOTE: This field should be set to a value of 1h Read Chip Select Hold after CK falling edge This bit indicates CS# hold time for read to CS# de-assertion. 1h = corresponds to 2 clock cycles |
11-8 | WCSH | R/W | 0h | Write Chip Select Hold after CK falling edge This bit indicates CS# hold time for write to CS# de-assertion. 0h = corresponds to 1 clock cycle Fh = corresponding to 16 clock cycle |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | LTCY | R/W | 1h | Latency Cycle Only uses in HyperRAM This bit indicates initial latency code for read/write access. This bit is ignored when the MCU_FSS0_HPB0_MC_MCR_y[4] DEVTYPE is 0h (HyperFlash). 0h = 5 clock latency 1h = 6 clock latency 2h = Reserved .... Dh = Reserved Eh = 3 clock latency Fh = 4 clock latency |
MCU_FSS0_HPB0_MC_GPOR is shown in Figure 12-2055 and described in Table 12-4087.
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General Purpose Output Register
Output signal polarity can be configured using the General Purpose Output Register.
General Purpose Output register (MCU_FSS0_HPB0_MC_GPOR) of the HBMC is not used (see HyperBus Not Supported Features).
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_CTRL | 4703 4040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPO | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1-0 | GPO | R/W | 0h | General Purpose Output Interface 0h = Output signal polarity is LOW 1h = Output signal polarity is HIGH |
MCU_FSS0_HPB0_MC_WPR is shown in Figure 12-2056 and described in Table 12-4089.
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Write Protection Register
Write protection can be configured using the Write Protection Register.
WPn pin is not used on Cypress flash devices (see Table 12-4057).
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_CTRL | 4703 4044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WP | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | WP | R/W | 0h | Write Protection Control 0h = Not Protected WP# signal is HIGH 1h = Protected WP# signal is LOW |
MCU_FSS0_HPB0_MC_LBR is shown in Figure 12-2057 and described in Table 12-4091.
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Loop Back Register
Loopback settings can be configured using the Loop Back Register.
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_CTRL | 4703 4048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOOPBACK | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | LOOPBACK | R/W | 0h | The write transaction data written on AXI bus is looped back as the read data from RPC bus. The loop-back is performed between WDAT FIFO and RDAT FIFO in AXI interface controller. 0h = Disable loopback 1h = Enable loopback |
Table 12-4093 lists the memory-mapped registers for the HyperBus interface (MCU_FSS0_HPB0) ECC Aggregator. All register offset addresses not listed in Table 12-4093 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 0000h |
Offset | Acronym | Register Name | MCU_FSS0_HPB_ECC_AGGR Physical Address |
---|---|---|---|
0h | MCU_FSS0_HPB0_ECC_REV | Aggregator Revision Register | 4706 0000h |
8h | MCU_FSS0_HPB0_ECC_VECTOR | ECC Vector Register | 4706 0008h |
Ch | MCU_FSS0_HPB0_ECC_STAT | Misc Status Register | 4706 000Ch |
3Ch | MCU_FSS0_HPB0_ECC_SEC_EOI_REG | SEC End Of Interrupt (EOI) Register | 4706 003Ch |
40h | MCU_FSS0_HPB0_ECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 4706 0040h |
80h | MCU_FSS0_HPB0_ECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 4706 0080h |
C0h | MCU_FSS0_HPB0_ECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 4706 00C0h |
13Ch | MCU_FSS0_HPB0_ECC_DED_EOI_REG | DED End Of Interrupt (EOI) Register | 4706 013Ch |
140h | MCU_FSS0_HPB0_ECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 4706 0140h |
180h | MCU_FSS0_HPB0_ECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 4706 0180h |
1C0h | MCU_FSS0_HPB0_ECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 4706 01C0h |
200h | MCU_FSS0_HPB0_ECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 4706 0200h |
204h | MCU_FSS0_HPB0_ECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 4706 0204h |
208h | MCU_FSS0_HPB0_ECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 4706 0208h |
20Ch | MCU_FSS0_HPB0_ECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 4706 020Ch |
MCU_FSS0_HPB0_ECC_REV is shown in Figure 12-2058 and described in Table 12-4095.
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Aggregator Revision Register
Revision parameters.
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1Dh | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | Business Unit |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 1Dh | RTL Version |
10-8 | REVMAJ | R | 2h | Major Version |
7-6 | CUSTOM | R | 0h | Custom Version |
5-0 | REVMIN | R | 0h | Minor Version |
MCU_FSS0_HPB0_ECC_VECTOR is shown in Figure 12-2059 and described in Table 12-4097.
Return to Summary Table.
ECC Vector Register
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Read Done Status to indicate if read on the serial ECC interface is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read Address |
15 | RD_SVBUS | R/W1S | 0h | Read Trigger Write 1h to trigger a read on the serial ECC interface. |
14-11 | RESERVED | R | 0h | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | ECC RAM ID Value written to select the corresponding ECC RAM for control or status. |
MCU_FSS0_HPB0_ECC_STAT is shown in Figure 12-2060 and described in Table 12-4099.
Return to Summary Table.
Misc Status Register
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-Fh | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-0 | NUM_RAMS | R | Fh | Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator. |
MCU_FSS0_HPB0_ECC_SEC_EOI_REG is shown in Figure 12-2061 and described in Table 12-4101.
Return to Summary Table.
End Of Interrupt (EOI) Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI |
MCU_FSS0_HPB0_ECC_SEC_STATUS_REG0 is shown in Figure 12-2062 and described in Table 12-4103.
Return to Summary Table.
SEC Interrupt Status Register 0
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MEM_ARID_FIFO_PEND | MEM_AR_FIFO_PEND | MEM_AWID1_FIFO_PEND | MEM_WID1_FIFO_PEND | MEM_AW1_FIFO_PEND | MEM_AWID0_FIFO_PEND | MEM_WID0_FIFO_PEND |
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_AW0_FIFO_PEND | MEM_RX_FIFO_PEND | MEM_RDAT_FIFO_PEND | MEM_BDAT1_FIFO_PEND | MEM_BDAT0_FIFO_PEND | MEM_WDAT1_FIFO_PEND | MEM_WDAT0_FIFO_PEND | MEM_ADR_FIFO_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | Reserved |
14 | MEM_ARID_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_arid_fifo_pend |
13 | MEM_AR_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_ar_fifo_pend |
12 | MEM_AWID1_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_awid1_fifo_pend |
11 | MEM_WID1_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_wid1_fifo_pend |
10 | MEM_AW1_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_aw1_fifo_pend |
9 | MEM_AWID0_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_awid0_fifo_pend |
8 | MEM_WID0_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_wid0_fifo_pend |
7 | MEM_AW0_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_aw0_fifo_pend |
6 | MEM_RX_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_rx_fifo_pend |
5 | MEM_RDAT_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_rdat_fifo_pend |
4 | MEM_BDAT1_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_bdat1_fifo_pend |
3 | MEM_BDAT0_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_bdat0_fifo_pend |
2 | MEM_WDAT1_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_wdat1_fifo_pend |
1 | MEM_WDAT0_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_wdat0_fifo_pend |
0 | MEM_ADR_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_adr_fifo_pend |
MCU_FSS0_HPB0_ECC_SEC_ENABLE_SET_REG0 is shown in Figure 12-2063 and described in Table 12-4105.
Return to Summary Table.
SEC Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MEM_ARID_FIFO_ENABLE_SET | MEM_AR_FIFO_ENABLE_SET | MEM_AWID1_FIFO_ENABLE_SET | MEM_WID1_FIFO_ENABLE_SET | MEM_AW1_FIFO_ENABLE_SET | MEM_AWID0_FIFO_ENABLE_SET | MEM_WID0_FIFO_ENABLE_SET |
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_AW0_FIFO_ENABLE_SET | MEM_RX_FIFO_ENABLE_SET | MEM_RDAT_FIFO_ENABLE_SET | MEM_BDAT1_FIFO_ENABLE_SET | MEM_BDAT0_FIFO_ENABLE_SET | MEM_WDAT1_FIFO_ENABLE_SET | MEM_WDAT0_FIFO_ENABLE_SET | MEM_ADR_FIFO_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | Reserved |
14 | MEM_ARID_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_arid_fifo_pend |
13 | MEM_AR_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_ar_fifo_pend |
12 | MEM_AWID1_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_awid1_fifo_pend |
11 | MEM_WID1_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_wid1_fifo_pend |
10 | MEM_AW1_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_aw1_fifo_pend |
9 | MEM_AWID0_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_awid0_fifo_pend |
8 | MEM_WID0_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_wid0_fifo_pend |
7 | MEM_AW0_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_aw0_fifo_pend |
6 | MEM_RX_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_rx_fifo_pend |
5 | MEM_RDAT_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_rdat_fifo_pend |
4 | MEM_BDAT1_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_bdat1_fifo_pend |
3 | MEM_BDAT0_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_bdat0_fifo_pend |
2 | MEM_WDAT1_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_wdat1_fifo_pend |
1 | MEM_WDAT0_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_wdat0_fifo_pend |
0 | MEM_ADR_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_adr_fifo_pend |
MCU_FSS0_HPB0_ECC_SEC_ENABLE_CLR_REG0 is shown in Figure 12-2064 and described in Table 12-4107.
Return to Summary Table.
SEC Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 00C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MEM_ARID_FIFO_ENABLE_CLR | MEM_AR_FIFO_ENABLE_CLR | MEM_AWID1_FIFO_ENABLE_CLR | MEM_WID1_FIFO_ENABLE_CLR | MEM_AW1_FIFO_ENABLE_CLR | MEM_AWID0_FIFO_ENABLE_CLR | MEM_WID0_FIFO_ENABLE_CLR |
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_AW0_FIFO_ENABLE_CLR | MEM_RX_FIFO_ENABLE_CLR | MEM_RDAT_FIFO_ENABLE_CLR | MEM_BDAT1_FIFO_ENABLE_CLR | MEM_BDAT0_FIFO_ENABLE_CLR | MEM_WDAT1_FIFO_ENABLE_CLR | MEM_WDAT0_FIFO_ENABLE_CLR | MEM_ADR_FIFO_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | Reserved |
14 | MEM_ARID_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_arid_fifo_pend |
13 | MEM_AR_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_ar_fifo_pend |
12 | MEM_AWID1_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_awid1_fifo_pend |
11 | MEM_WID1_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_wid1_fifo_pend |
10 | MEM_AW1_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_aw1_fifo_pend |
9 | MEM_AWID0_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_awid0_fifo_pend |
8 | MEM_WID0_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_wid0_fifo_pend |
7 | MEM_AW0_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_aw0_fifo_pend |
6 | MEM_RX_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_rx_fifo_pend |
5 | MEM_RDAT_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_rdat_fifo_pend |
4 | MEM_BDAT1_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_bdat1_fifo_pend |
3 | MEM_BDAT0_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_bdat0_fifo_pend |
2 | MEM_WDAT1_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_wdat1_fifo_pend |
1 | MEM_WDAT0_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_wdat0_fifo_pend |
0 | MEM_ADR_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_adr_fifo_pend |
MCU_FSS0_HPB0_ECC_DED_EOI_REG is shown in Figure 12-2065 and described in Table 12-4109.
Return to Summary Table.
DED EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 013Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI |
MCU_FSS0_HPB0_ECC_DED_STATUS_REG0 is shown in Figure 12-2066 and described in Table 12-4111.
Return to Summary Table.
DED Interrupt Status Register 0
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 0140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MEM_ARID_FIFO_PEND | MEM_AR_FIFO_PEND | MEM_AWID1_FIFO_PEND | MEM_WID1_FIFO_PEND | MEM_AW1_FIFO_PEND | MEM_AWID0_FIFO_PEND | MEM_WID0_FIFO_PEND |
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_AW0_FIFO_PEND | MEM_RX_FIFO_PEND | MEM_RDAT_FIFO_PEND | MEM_BDAT1_FIFO_PEND | MEM_BDAT0_FIFO_PEND | MEM_WDAT1_FIFO_PEND | MEM_WDAT0_FIFO_PEND | MEM_ADR_FIFO_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | Reserved |
14 | MEM_ARID_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_arid_fifo_pend |
13 | MEM_AR_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_ar_fifo_pend |
12 | MEM_AWID1_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_awid1_fifo_pend |
11 | MEM_WID1_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_wid1_fifo_pend |
10 | MEM_AW1_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_aw1_fifo_pend |
9 | MEM_AWID0_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_awid0_fifo_pend |
8 | MEM_WID0_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_wid0_fifo_pend |
7 | MEM_AW0_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_aw0_fifo_pend |
6 | MEM_RX_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_rx_fifo_pend |
5 | MEM_RDAT_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_rdat_fifo_pend |
4 | MEM_BDAT1_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_bdat1_fifo_pend |
3 | MEM_BDAT0_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_bdat0_fifo_pend |
2 | MEM_WDAT1_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_wdat1_fifo_pend |
1 | MEM_WDAT0_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_wdat0_fifo_pend |
0 | MEM_ADR_FIFO_PEND | R/W1S | 0h | Interrupt Pending Status for mem_adr_fifo_pend |
MCU_FSS0_HPB0_ECC_DED_ENABLE_SET_REG0 is shown in Figure 12-2067 and described in Table 12-4113.
Return to Summary Table.
DED Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 0180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MEM_ARID_FIFO_ENABLE_SET | MEM_AR_FIFO_ENABLE_SET | MEM_AWID1_FIFO_ENABLE_SET | MEM_WID1_FIFO_ENABLE_SET | MEM_AW1_FIFO_ENABLE_SET | MEM_AWID0_FIFO_ENABLE_SET | MEM_WID0_FIFO_ENABLE_SET |
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_AW0_FIFO_ENABLE_SET | MEM_RX_FIFO_ENABLE_SET | MEM_RDAT_FIFO_ENABLE_SET | MEM_BDAT1_FIFO_ENABLE_SET | MEM_BDAT0_FIFO_ENABLE_SET | MEM_WDAT1_FIFO_ENABLE_SET | MEM_WDAT0_FIFO_ENABLE_SET | MEM_ADR_FIFO_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | Reserved |
14 | MEM_ARID_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_arid_fifo_pend |
13 | MEM_AR_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_ar_fifo_pend |
12 | MEM_AWID1_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_awid1_fifo_pend |
11 | MEM_WID1_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_wid1_fifo_pend |
10 | MEM_AW1_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_aw1_fifo_pend |
9 | MEM_AWID0_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_awid0_fifo_pend |
8 | MEM_WID0_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_wid0_fifo_pend |
7 | MEM_AW0_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_aw0_fifo_pend |
6 | MEM_RX_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_rx_fifo_pend |
5 | MEM_RDAT_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_rdat_fifo_pend |
4 | MEM_BDAT1_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_bdat1_fifo_pend |
3 | MEM_BDAT0_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_bdat0_fifo_pend |
2 | MEM_WDAT1_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_wdat1_fifo_pend |
1 | MEM_WDAT0_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_wdat0_fifo_pend |
0 | MEM_ADR_FIFO_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for mem_adr_fifo_pend |
MCU_FSS0_HPB0_ECC_DED_ENABLE_CLR_REG0 is shown in Figure 12-2068 and described in Table 12-4115.
Return to Summary Table.
DED Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 01C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MEM_ARID_FIFO_ENABLE_CLR | MEM_AR_FIFO_ENABLE_CLR | MEM_AWID1_FIFO_ENABLE_CLR | MEM_WID1_FIFO_ENABLE_CLR | MEM_AW1_FIFO_ENABLE_CLR | MEM_AWID0_FIFO_ENABLE_CLR | MEM_WID0_FIFO_ENABLE_CLR |
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_AW0_FIFO_ENABLE_CLR | MEM_RX_FIFO_ENABLE_CLR | MEM_RDAT_FIFO_ENABLE_CLR | MEM_BDAT1_FIFO_ENABLE_CLR | MEM_BDAT0_FIFO_ENABLE_CLR | MEM_WDAT1_FIFO_ENABLE_CLR | MEM_WDAT0_FIFO_ENABLE_CLR | MEM_ADR_FIFO_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | Reserved |
14 | MEM_ARID_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_arid_fifo_pend |
13 | MEM_AR_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_ar_fifo_pend |
12 | MEM_AWID1_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_awid1_fifo_pend |
11 | MEM_WID1_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_wid1_fifo_pend |
10 | MEM_AW1_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_aw1_fifo_pend |
9 | MEM_AWID0_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_awid0_fifo_pend |
8 | MEM_WID0_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_wid0_fifo_pend |
7 | MEM_AW0_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_aw0_fifo_pend |
6 | MEM_RX_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_rx_fifo_pend |
5 | MEM_RDAT_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_rdat_fifo_pend |
4 | MEM_BDAT1_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_bdat1_fifo_pend |
3 | MEM_BDAT0_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_bdat0_fifo_pend |
2 | MEM_WDAT1_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_wdat1_fifo_pend |
1 | MEM_WDAT0_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_wdat0_fifo_pend |
0 | MEM_ADR_FIFO_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for mem_adr_fifo_pend |
MCU_FSS0_HPB0_ECC_AGGR_ENABLE_SET is shown in Figure 12-2069 and described in Table 12-4117.
Return to Summary Table.
Aggregator Interrupt Enable Set Register
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 0200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | Interrupt enable set for ECC interface timeout errors |
0 | PARITY | R/W1S | 0h | Interrupt enable set for parity errors |
MCU_FSS0_HPB0_ECC_AGGR_ENABLE_CLR is shown in Figure 12-2070 and described in Table 12-4119.
Return to Summary Table.
Aggregator Interrupt Enable Clear Register
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 0204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | Interrupt enable clear for ECC interface timeout errors |
0 | PARITY | R/W1C | 0h | Interrupt enable clear for parity errors |
MCU_FSS0_HPB0_ECC_AGGR_STATUS_SET is shown in Figure 12-2071 and described in Table 12-4121.
Return to Summary Table.
Aggregator Interrupt Status Set Register
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 0208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R = Read Only; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | Interrupt status set for ECC interface timeout errors |
1-0 | PARITY | R/Wincr | 0h | Interrupt status set for parity errors |
MCU_FSS0_HPB0_ECC_AGGR_STATUS_CLR is shown in Figure 12-2072 and described in Table 12-4123.
Return to Summary Table.
Aggregator Interrupt Status Clear Register
Instance | Physical Address |
---|---|
MCU_FSS0_HPB_ECC_AGGR | 4706 020Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R = Read Only; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | Interrupt status clear for ECC interface timeout errors |
1-0 | PARITY | R/Wdecr | 0h | Interrupt status clear for parity errors |