SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 6-233 lists the memory-mapped registers for the R5FSS_CPU1_ECC_AGGR_CFG_REGS. All register offset addresses not listed in Table 6-233 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0000h |
R5FSS0_ECC_AGGR | 05B1 0000h |
Offset | Acronym | Register Name | MCU_R5FSS0_ECC_AGGR Physical Address |
---|---|---|---|
0h | R5FSS_CPU1_REV | Revision register | 400C 0000h |
8h | R5FSS_CPU1_VECTOR | ECC vector register | 400C 0008h |
Ch | R5FSS_CPU1_STAT | Misc status register | 400C 000Ch |
3Ch | R5FSS_CPU1_SEC_EOI_REG | SEC EOI register | 400C 003Ch |
40h | R5FSS_CPU1_SEC_STATUS_REG0 | SEC interrupt status register 0 | 400C 0040h |
44h | R5FSS_CPU1_SEC_STATUS_REG1 | SEC interrupt status register 1 | 400C 0044h |
80h | R5FSS_CPU1_SEC_ENABLE_SET_REG0 | SEC interrupt enable set register 0 | 400C 0080h |
84h | R5FSS_CPU1_SEC_ENABLE_SET_REG1 | SEC interrupt enable set register 1 | 400C 0084h |
C0h | R5FSS_CPU1_SEC_ENABLE_CLR_REG0 | SEC interrupt enable clear register 0 | 400C 00C0h |
C4h | R5FSS_CPU1_SEC_ENABLE_CLR_REG1 | SEC interrupt enable clear register 1 | 400C 00C4h |
13Ch | R5FSS_CPU1_DED_EOI_REG | DED EOI register | 400C 013Ch |
140h | R5FSS_CPU1_DED_STATUS_REG0 | DED interrupt status register 0 | 400C 0140h |
144h | R5FSS_CPU1_DED_STATUS_REG1 | DED interrupt status register 1 | 400C 0144h |
180h | R5FSS_CPU1_DED_ENABLE_SET_REG0 | DED interrupt enable set register 0 | 400C 0180h |
184h | R5FSS_CPU1_DED_ENABLE_SET_REG1 | DED interrupt enable set register 1 | 400C 0184h |
1C0h | R5FSS_CPU1_DED_ENABLE_CLR_REG0 | DED interrupt enable clear register 0 | 400C 01C0h |
1C4h | R5FSS_CPU1_DED_ENABLE_CLR_REG1 | DED interrupt enable clear register 1 | 400C 01C4h |
200h | R5FSS_CPU1_AGGR_ENABLE_SET | AGGR interrupt enable set register | 400C 0200h |
204h | R5FSS_CPU1_AGGR_ENABLE_CLR | AGGR interrupt enable clear register | 400C 0204h |
208h | R5FSS_CPU1_AGGR_STATUS_SET | AGGR interrupt status set register | 400C 0208h |
20Ch | R5FSS_CPU1_AGGR_STATUS_CLR | AGGR interrupt status clear register | 400C 020Ch |
Offset | Acronym | Register Name | R5FSS0_ECC_AGGR Physical Address |
---|---|---|---|
0h | R5FSS_CPU1_REV | Revision register | 05B1 0000h |
8h | R5FSS_CPU1_VECTOR | ECC vector register | 05B1 0008h |
Ch | R5FSS_CPU1_STAT | Misc status register | 05B1 000Ch |
3Ch | R5FSS_CPU1_SEC_EOI_REG | SEC EOI register | 05B1 003Ch |
40h | R5FSS_CPU1_SEC_STATUS_REG0 | SEC interrupt status register 0 | 05B1 0040h |
44h | R5FSS_CPU1_SEC_STATUS_REG1 | SEC interrupt status register 1 | 05B1 0044h |
80h | R5FSS_CPU1_SEC_ENABLE_SET_REG0 | SEC interrupt enable set register 0 | 05B1 0080h |
84h | R5FSS_CPU1_SEC_ENABLE_SET_REG1 | SEC interrupt enable set register 1 | 05B1 0084h |
C0h | R5FSS_CPU1_SEC_ENABLE_CLR_REG0 | SEC interrupt enable clear register 0 | 05B1 00C0h |
C4h | R5FSS_CPU1_SEC_ENABLE_CLR_REG1 | SEC interrupt enable clear register 1 | 05B1 00C4h |
13Ch | R5FSS_CPU1_DED_EOI_REG | DED EOI register | 05B1 013Ch |
140h | R5FSS_CPU1_DED_STATUS_REG0 | DED interrupt status register 0 | 05B1 0140h |
144h | R5FSS_CPU1_DED_STATUS_REG1 | DED interrupt status register 1 | 05B1 0144h |
180h | R5FSS_CPU1_DED_ENABLE_SET_REG0 | DED interrupt enable set register 0 | 05B1 0180h |
184h | R5FSS_CPU1_DED_ENABLE_SET_REG1 | DED interrupt enable set register 1 | 05B1 0184h |
1C0h | R5FSS_CPU1_DED_ENABLE_CLR_REG0 | DED interrupt enable clear register 0 | 05B1 01C0h |
1C4h | R5FSS_CPU1_DED_ENABLE_CLR_REG1 | DED interrupt enable clear register 1 | 05B1 01C4h |
200h | R5FSS_CPU1_AGGR_ENABLE_SET | AGGR interrupt enable set register | 05B1 0200h |
204h | R5FSS_CPU1_AGGR_ENABLE_CLR | AGGR interrupt enable clear register | 05B1 0204h |
208h | R5FSS_CPU1_AGGR_STATUS_SET | AGGR interrupt status set register | 05B1 0208h |
20Ch | R5FSS_CPU1_AGGR_STATUS_CLR | AGGR interrupt status clear register | 05B1 020Ch |
R5FSS_CPU1_REV is shown in Figure 6-99 and described in Table 6-236.
Return to Summary Table.
Revision register.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0000h |
R5FSS0_ECC_AGGR | 05B1 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66A0E200h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66A0E200h | TI internal data. Identifies revision of peripheral. |
R5FSS_CPU1_VECTOR is shown in Figure 6-100 and described in Table 6-238.
Return to Summary Table.
ECC vector register.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0008h |
R5FSS0_ECC_AGGR | 05B1 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved. |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address. |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS. |
14-11 | RESERVED | R | 0h | Reserved. |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status. |
R5FSS_CPU1_STAT is shown in Figure 6-101 and described in Table 6-240.
Return to Summary Table.
Misc status register.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 000Ch |
R5FSS0_ECC_AGGR | 05B1 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-23h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-0 | NUM_RAMS | R | 23h | Indicates the number of RAMS serviced by the ECC aggregator |
R5FSS_CPU1_SEC_EOI_REG is shown in Figure 6-102 and described in Table 6-242.
Return to Summary Table.
SEC EOI register.
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 003Ch |
R5FSS0_ECC_AGGR | 05B1 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI value |
R5FSS_CPU1_SEC_STATUS_REG0 is shown in Figure 6-103 and described in Table 6-244.
Return to Summary Table.
SEC interrupt status register 0.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0040h |
R5FSS0_ECC_AGGR | 05B1 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND | CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND | CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND | CPU1_VBUSM2AXI_EDC_PEND | CPU1_KS_VIM_RAMECC_PEND | B1TCM1_BANK1_PEND | B1TCM1_BANK0_PEND | B0TCM1_BANK1_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
B0TCM1_BANK0_PEND | ATCM1_BANK1_PEND | ATCM1_BANK0_PEND | CPU1_DDATA_RAM7_PEND | CPU1_DDATA_RAM6_PEND | CPU1_DDATA_RAM5_PEND | CPU1_DDATA_RAM4_PEND | CPU1_DDATA_RAM3_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU1_DDATA_RAM2_PEND | CPU1_DDATA_RAM1_PEND | CPU1_DDATA_RAM0_PEND | CPU1_DDIRTY_RAM_PEND | CPU1_DTAG_RAM3_PEND | CPU1_DTAG_RAM2_PEND | CPU1_DTAG_RAM1_PEND | CPU1_DTAG_RAM0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_IDATA_BANK3_PEND | CPU1_IDATA_BANK2_PEND | CPU1_IDATA_BANK1_PEND | CPU1_IDATA_BANK0_PEND | CPU1_ITAG_RAM3_PEND | CPU1_ITAG_RAM2_PEND | CPU1_ITAG_RAM1_PEND | CPU1_ITAG_RAM0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_axi2vbusm_periph_mst_write_edc_pend |
30 | CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_axi2vbusm_mem_mst_read_edc_pend |
29 | CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_axi2vbusm_mem_mst_write_edc_pend |
28 | CPU1_VBUSM2AXI_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_vbusm2axi_edc_pend |
27 | CPU1_KS_VIM_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ks_vim_ramecc_pend |
26 | B1TCM1_BANK1_PEND | R/W1S | 0h | Interrupt pending status for b1tcm1_bank1_pend |
25 | B1TCM1_BANK0_PEND | R/W1S | 0h | Interrupt pending status for b1tcm1_bank0_pend |
24 | B0TCM1_BANK1_PEND | R/W1S | 0h | Interrupt pending status for b0tcm1_bank1_pend |
23 | B0TCM1_BANK0_PEND | R/W1S | 0h | Interrupt pending status for b0tcm1_bank0_pend |
22 | ATCM1_BANK1_PEND | R/W1S | 0h | Interrupt pending status for atcm1_bank1_pend |
21 | ATCM1_BANK0_PEND | R/W1S | 0h | Interrupt pending status for atcm1_bank0_pend |
20 | CPU1_DDATA_RAM7_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram7_pend |
19 | CPU1_DDATA_RAM6_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram6_pend |
18 | CPU1_DDATA_RAM5_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram5_pend |
17 | CPU1_DDATA_RAM4_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram4_pend |
16 | CPU1_DDATA_RAM3_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram3_pend |
15 | CPU1_DDATA_RAM2_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram2_pend |
14 | CPU1_DDATA_RAM1_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram1_pend |
13 | CPU1_DDATA_RAM0_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram0_pend |
12 | CPU1_DDIRTY_RAM_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddirty_ram_pend |
11 | CPU1_DTAG_RAM3_PEND | R/W1S | 0h | Interrupt pending status for cpu1_dtag_ram3_pend |
10 | CPU1_DTAG_RAM2_PEND | R/W1S | 0h | Interrupt pending status for cpu1_dtag_ram2_pend |
9 | CPU1_DTAG_RAM1_PEND | R/W1S | 0h | Interrupt pending status for cpu1_dtag_ram1_pend |
8 | CPU1_DTAG_RAM0_PEND | R/W1S | 0h | Interrupt pending status for cpu1_dtag_ram0_pend |
7 | CPU1_IDATA_BANK3_PEND | R/W1S | 0h | Interrupt pending status for cpu1_idata_bank3_pend |
6 | CPU1_IDATA_BANK2_PEND | R/W1S | 0h | Interrupt pending status for cpu1_idata_bank2_pend |
5 | CPU1_IDATA_BANK1_PEND | R/W1S | 0h | Interrupt pending status for cpu1_idata_bank1_pend |
4 | CPU1_IDATA_BANK0_PEND | R/W1S | 0h | Interrupt pending status for cpu1_idata_bank0_pend |
3 | CPU1_ITAG_RAM3_PEND | R/W1S | 0h | Interrupt pending status for cpu1_itag_ram3_pend |
2 | CPU1_ITAG_RAM2_PEND | R/W1S | 0h | Interrupt pending status for cpu1_itag_ram2_pend |
1 | CPU1_ITAG_RAM1_PEND | R/W1S | 0h | Interrupt pending status for cpu1_itag_ram1_pend |
0 | CPU1_ITAG_RAM0_PEND | R/W1S | 0h | Interrupt pending status for cpu1_itag_ram0_pend |
R5FSS_CPU1_SEC_STATUS_REG1 is shown in Figure 6-104 and described in Table 6-246.
Return to Summary Table.
SEC interrupt status register 1.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0044h |
R5FSS0_ECC_AGGR | 05B1 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU1_EDC_CTRL_PEND | CPU1_AHB2VBUSP_EDC_PEND | CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND | ||||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | CPU1_EDC_CTRL_PEND | R/W1S | 0h | Interrupt pending status for cpu1_edc_ctrl_pend |
1 | CPU1_AHB2VBUSP_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ahb2vbusp_edc_pend |
0 | CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_axi2vbusm_periph_mst_read_edc_pend |
R5FSS_CPU1_SEC_ENABLE_SET_REG0 is shown in Figure 6-105 and described in Table 6-248.
Return to Summary Table.
SEC interrupt enable set register 0.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0080h |
R5FSS0_ECC_AGGR | 05B1 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET | CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET | CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET | CPU1_VBUSM2AXI_EDC_ENABLE_SET | CPU1_KS_VIM_RAMECC_ENABLE_SET | B1TCM1_BANK1_ENABLE_SET | B1TCM1_BANK0_ENABLE_SET | B0TCM1_BANK1_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
B0TCM1_BANK0_ENABLE_SET | ATCM1_BANK1_ENABLE_SET | ATCM1_BANK0_ENABLE_SET | CPU1_DDATA_RAM7_ENABLE_SET | CPU1_DDATA_RAM6_ENABLE_SET | CPU1_DDATA_RAM5_ENABLE_SET | CPU1_DDATA_RAM4_ENABLE_SET | CPU1_DDATA_RAM3_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU1_DDATA_RAM2_ENABLE_SET | CPU1_DDATA_RAM1_ENABLE_SET | CPU1_DDATA_RAM0_ENABLE_SET | CPU1_DDIRTY_RAM_ENABLE_SET | CPU1_DTAG_RAM3_ENABLE_SET | CPU1_DTAG_RAM2_ENABLE_SET | CPU1_DTAG_RAM1_ENABLE_SET | CPU1_DTAG_RAM0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_IDATA_BANK3_ENABLE_SET | CPU1_IDATA_BANK2_ENABLE_SET | CPU1_IDATA_BANK1_ENABLE_SET | CPU1_IDATA_BANK0_ENABLE_SET | CPU1_ITAG_RAM3_ENABLE_SET | CPU1_ITAG_RAM2_ENABLE_SET | CPU1_ITAG_RAM1_ENABLE_SET | CPU1_ITAG_RAM0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_axi2vbusm_periph_mst_write_edc_pend |
30 | CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_axi2vbusm_mem_mst_read_edc_pend |
29 | CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_axi2vbusm_mem_mst_write_edc_pend |
28 | CPU1_VBUSM2AXI_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_vbusm2axi_edc_pend |
27 | CPU1_KS_VIM_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ks_vim_ramecc_pend |
26 | B1TCM1_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for b1tcm1_bank1_pend |
25 | B1TCM1_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for b1tcm1_bank0_pend |
24 | B0TCM1_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for b0tcm1_bank1_pend |
23 | B0TCM1_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for b0tcm1_bank0_pend |
22 | ATCM1_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for atcm1_bank1_pend |
21 | ATCM1_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for atcm1_bank0_pend |
20 | CPU1_DDATA_RAM7_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram7_pend |
19 | CPU1_DDATA_RAM6_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram6_pend |
18 | CPU1_DDATA_RAM5_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram5_pend |
17 | CPU1_DDATA_RAM4_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram4_pend |
16 | CPU1_DDATA_RAM3_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram3_pend |
15 | CPU1_DDATA_RAM2_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram2_pend |
14 | CPU1_DDATA_RAM1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram1_pend |
13 | CPU1_DDATA_RAM0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram0_pend |
12 | CPU1_DDIRTY_RAM_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddirty_ram_pend |
11 | CPU1_DTAG_RAM3_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_dtag_ram3_pend |
10 | CPU1_DTAG_RAM2_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_dtag_ram2_pend |
9 | CPU1_DTAG_RAM1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_dtag_ram1_pend |
8 | CPU1_DTAG_RAM0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_dtag_ram0_pend |
7 | CPU1_IDATA_BANK3_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_idata_bank3_pend |
6 | CPU1_IDATA_BANK2_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_idata_bank2_pend |
5 | CPU1_IDATA_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_idata_bank1_pend |
4 | CPU1_IDATA_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_idata_bank0_pend |
3 | CPU1_ITAG_RAM3_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_itag_ram3_pend |
2 | CPU1_ITAG_RAM2_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_itag_ram2_pend |
1 | CPU1_ITAG_RAM1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_itag_ram1_pend |
0 | CPU1_ITAG_RAM0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_itag_ram0_pend |
R5FSS_CPU1_SEC_ENABLE_SET_REG1 is shown in Figure 6-106 and described in Table 6-250.
Return to Summary Table.
SEC interrupt enable set register 1.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0084h |
R5FSS0_ECC_AGGR | 05B1 0084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU1_EDC_CTRL_ENABLE_SET | CPU1_AHB2VBUSP_EDC_ENABLE_SET | CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET | ||||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | 0h | Reserved |
2 | CPU1_EDC_CTRL_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_edc_ctrl_pend |
1 | CPU1_AHB2VBUSP_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ahb2vbusp_edc_pend |
0 | CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_axi2vbusm_periph_mst_read_edc_pend |
R5FSS_CPU1_SEC_ENABLE_CLR_REG0 is shown in Figure 6-107 and described in Table 6-252.
Return to Summary Table.
SC interrupt enable clear register 0.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 00C0h |
R5FSS0_ECC_AGGR | 05B1 00C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR | CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR | CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR | CPU1_VBUSM2AXI_EDC_ENABLE_CLR | CPU1_KS_VIM_RAMECC_ENABLE_CLR | B1TCM1_BANK1_ENABLE_CLR | B1TCM1_BANK0_ENABLE_CLR | B0TCM1_BANK1_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
B0TCM1_BANK0_ENABLE_CLR | ATCM1_BANK1_ENABLE_CLR | ATCM1_BANK0_ENABLE_CLR | CPU1_DDATA_RAM7_ENABLE_CLR | CPU1_DDATA_RAM6_ENABLE_CLR | CPU1_DDATA_RAM5_ENABLE_CLR | CPU1_DDATA_RAM4_ENABLE_CLR | CPU1_DDATA_RAM3_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU1_DDATA_RAM2_ENABLE_CLR | CPU1_DDATA_RAM1_ENABLE_CLR | CPU1_DDATA_RAM0_ENABLE_CLR | CPU1_DDIRTY_RAM_ENABLE_CLR | CPU1_DTAG_RAM3_ENABLE_CLR | CPU1_DTAG_RAM2_ENABLE_CLR | CPU1_DTAG_RAM1_ENABLE_CLR | CPU1_DTAG_RAM0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_IDATA_BANK3_ENABLE_CLR | CPU1_IDATA_BANK2_ENABLE_CLR | CPU1_IDATA_BANK1_ENABLE_CLR | CPU1_IDATA_BANK0_ENABLE_CLR | CPU1_ITAG_RAM3_ENABLE_CLR | CPU1_ITAG_RAM2_ENABLE_CLR | CPU1_ITAG_RAM1_ENABLE_CLR | CPU1_ITAG_RAM0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_axi2vbusm_periph_mst_write_edc_pend |
30 | CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_axi2vbusm_mem_mst_read_edc_pend |
29 | CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_axi2vbusm_mem_mst_write_edc_pend |
28 | CPU1_VBUSM2AXI_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_vbusm2axi_edc_pend |
27 | CPU1_KS_VIM_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ks_vim_ramecc_pend |
26 | B1TCM1_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for b1tcm1_bank1_pend |
25 | B1TCM1_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for b1tcm1_bank0_pend |
24 | B0TCM1_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for b0tcm1_bank1_pend |
23 | B0TCM1_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for b0tcm1_bank0_pend |
22 | ATCM1_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for atcm1_bank1_pend |
21 | ATCM1_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for atcm1_bank0_pend |
20 | CPU1_DDATA_RAM7_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram7_pend |
19 | CPU1_DDATA_RAM6_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram6_pend |
18 | CPU1_DDATA_RAM5_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram5_pend |
17 | CPU1_DDATA_RAM4_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram4_pend |
16 | CPU1_DDATA_RAM3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram3_pend |
15 | CPU1_DDATA_RAM2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram2_pend |
14 | CPU1_DDATA_RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram1_pend |
13 | CPU1_DDATA_RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram0_pend |
12 | CPU1_DDIRTY_RAM_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddirty_ram_pend |
11 | CPU1_DTAG_RAM3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_dtag_ram3_pend |
10 | CPU1_DTAG_RAM2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_dtag_ram2_pend |
9 | CPU1_DTAG_RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_dtag_ram1_pend |
8 | CPU1_DTAG_RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_dtag_ram0_pend |
7 | CPU1_IDATA_BANK3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_idata_bank3_pend |
6 | CPU1_IDATA_BANK2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_idata_bank2_pend |
5 | CPU1_IDATA_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_idata_bank1_pend |
4 | CPU1_IDATA_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_idata_bank0_pend |
3 | CPU1_ITAG_RAM3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_itag_ram3_pend |
2 | CPU1_ITAG_RAM2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_itag_ram2_pend |
1 | CPU1_ITAG_RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_itag_ram1_pend |
0 | CPU1_ITAG_RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_itag_ram0_pend |
R5FSS_CPU1_SEC_ENABLE_CLR_REG1 is shown in Figure 6-108 and described in Table 6-254.
Return to Summary Table.
SEC interrupt enable clear register 1.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 00C4h |
R5FSS0_ECC_AGGR | 05B1 00C4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU1_EDC_CTRL_ENABLE_CLR | CPU1_AHB2VBUSP_EDC_ENABLE_CLR | CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR | ||||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | CPU1_EDC_CTRL_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_edc_ctrl_pend |
1 | CPU1_AHB2VBUSP_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ahb2vbusp_edc_pend |
0 | CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_axi2vbusm_periph_mst_read_edc_pend |
R5FSS_CPU1_DED_EOI_REG is shown in Figure 6-109 and described in Table 6-256.
Return to Summary Table.
DED EOI register.
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 013Ch |
R5FSS0_ECC_AGGR | 05B1 013Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI value |
R5FSS_CPU1_DED_STATUS_REG0 is shown in Figure 6-110 and described in Table 6-258.
Return to Summary Table.
DED interrupt status register 0.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0140h |
R5FSS0_ECC_AGGR | 05B1 0140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND | CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND | CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND | CPU1_VBUSM2AXI_EDC_PEND | CPU1_KS_VIM_RAMECC_PEND | B1TCM1_BANK1_PEND | B1TCM1_BANK0_PEND | B0TCM1_BANK1_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
B0TCM1_BANK0_PEND | ATCM1_BANK1_PEND | ATCM1_BANK0_PEND | CPU1_DDATA_RAM7_PEND | CPU1_DDATA_RAM6_PEND | CPU1_DDATA_RAM5_PEND | CPU1_DDATA_RAM4_PEND | CPU1_DDATA_RAM3_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU1_DDATA_RAM2_PEND | CPU1_DDATA_RAM1_PEND | CPU1_DDATA_RAM0_PEND | CPU1_DDIRTY_RAM_PEND | CPU1_DTAG_RAM3_PEND | CPU1_DTAG_RAM2_PEND | CPU1_DTAG_RAM1_PEND | CPU1_DTAG_RAM0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_IDATA_BANK3_PEND | CPU1_IDATA_BANK2_PEND | CPU1_IDATA_BANK1_PEND | CPU1_IDATA_BANK0_PEND | CPU1_ITAG_RAM3_PEND | CPU1_ITAG_RAM2_PEND | CPU1_ITAG_RAM1_PEND | CPU1_ITAG_RAM0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_axi2vbusm_periph_mst_write_edc_pend |
30 | CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_axi2vbusm_mem_mst_read_edc_pend |
29 | CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_axi2vbusm_mem_mst_write_edc_pend |
28 | CPU1_VBUSM2AXI_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_vbusm2axi_edc_pend |
27 | CPU1_KS_VIM_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ks_vim_ramecc_pend |
26 | B1TCM1_BANK1_PEND | R/W1S | 0h | Interrupt pending status for b1tcm1_bank1_pend |
25 | B1TCM1_BANK0_PEND | R/W1S | 0h | Interrupt pending status for b1tcm1_bank0_pend |
24 | B0TCM1_BANK1_PEND | R/W1S | 0h | Interrupt pending status for b0tcm1_bank1_pend |
23 | B0TCM1_BANK0_PEND | R/W1S | 0h | Interrupt pending status for b0tcm1_bank0_pend |
22 | ATCM1_BANK1_PEND | R/W1S | 0h | Interrupt pending status for atcm1_bank1_pend |
21 | ATCM1_BANK0_PEND | R/W1S | 0h | Interrupt pending status for atcm1_bank0_pend |
20 | CPU1_DDATA_RAM7_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram7_pend |
19 | CPU1_DDATA_RAM6_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram6_pend |
18 | CPU1_DDATA_RAM5_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram5_pend |
17 | CPU1_DDATA_RAM4_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram4_pend |
16 | CPU1_DDATA_RAM3_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram3_pend |
15 | CPU1_DDATA_RAM2_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram2_pend |
14 | CPU1_DDATA_RAM1_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram1_pend |
13 | CPU1_DDATA_RAM0_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddata_ram0_pend |
12 | CPU1_DDIRTY_RAM_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ddirty_ram_pend |
11 | CPU1_DTAG_RAM3_PEND | R/W1S | 0h | Interrupt pending status for cpu1_dtag_ram3_pend |
10 | CPU1_DTAG_RAM2_PEND | R/W1S | 0h | Interrupt pending status for cpu1_dtag_ram2_pend |
9 | CPU1_DTAG_RAM1_PEND | R/W1S | 0h | Interrupt pending status for cpu1_dtag_ram1_pend |
8 | CPU1_DTAG_RAM0_PEND | R/W1S | 0h | Interrupt pending status for cpu1_dtag_ram0_pend |
7 | CPU1_IDATA_BANK3_PEND | R/W1S | 0h | Interrupt pending status for cpu1_idata_bank3_pend |
6 | CPU1_IDATA_BANK2_PEND | R/W1S | 0h | Interrupt pending status for cpu1_idata_bank2_pend |
5 | CPU1_IDATA_BANK1_PEND | R/W1S | 0h | Interrupt pending status for cpu1_idata_bank1_pend |
4 | CPU1_IDATA_BANK0_PEND | R/W1S | 0h | Interrupt pending status for cpu1_idata_bank0_pend |
3 | CPU1_ITAG_RAM3_PEND | R/W1S | 0h | Interrupt pending status for cpu1_itag_ram3_pend |
2 | CPU1_ITAG_RAM2_PEND | R/W1S | 0h | Interrupt pending status for cpu1_itag_ram2_pend |
1 | CPU1_ITAG_RAM1_PEND | R/W1S | 0h | Interrupt pending status for cpu1_itag_ram1_pend |
0 | CPU1_ITAG_RAM0_PEND | R/W1S | 0h | Interrupt pending status for cpu1_itag_ram0_pend |
R5FSS_CPU1_DED_STATUS_REG1 is shown in Figure 6-111 and described in Table 6-260.
Return to Summary Table.
DED interrupt status register 1.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0144h |
R5FSS0_ECC_AGGR | 05B1 0144h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU1_EDC_CTRL_PEND | CPU1_AHB2VBUSP_EDC_PEND | CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND | ||||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||
LEGEND: R = read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | CPU1_EDC_CTRL_PEND | R/W1S | 0h | Interrupt pending status for cpu1_edc_ctrl_pend |
1 | CPU1_AHB2VBUSP_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_ahb2vbusp_edc_pend |
0 | CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu1_axi2vbusm_periph_mst_read_edc_pend |
R5FSS_CPU1_DED_ENABLE_SET_REG0 is shown in Figure 6-112 and described in Table 6-262.
Return to Summary Table.
DED interrupt enable set register 0.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0180h |
R5FSS0_ECC_AGGR | 05B1 0180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET | CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET | CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET | CPU1_VBUSM2AXI_EDC_ENABLE_SET | CPU1_KS_VIM_RAMECC_ENABLE_SET | B1TCM1_BANK1_ENABLE_SET | B1TCM1_BANK0_ENABLE_SET | B0TCM1_BANK1_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
B0TCM1_BANK0_ENABLE_SET | ATCM1_BANK1_ENABLE_SET | ATCM1_BANK0_ENABLE_SET | CPU1_DDATA_RAM7_ENABLE_SET | CPU1_DDATA_RAM6_ENABLE_SET | CPU1_DDATA_RAM5_ENABLE_SET | CPU1_DDATA_RAM4_ENABLE_SET | CPU1_DDATA_RAM3_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU1_DDATA_RAM2_ENABLE_SET | CPU1_DDATA_RAM1_ENABLE_SET | CPU1_DDATA_RAM0_ENABLE_SET | CPU1_DDIRTY_RAM_ENABLE_SET | CPU1_DTAG_RAM3_ENABLE_SET | CPU1_DTAG_RAM2_ENABLE_SET | CPU1_DTAG_RAM1_ENABLE_SET | CPU1_DTAG_RAM0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_IDATA_BANK3_ENABLE_SET | CPU1_IDATA_BANK2_ENABLE_SET | CPU1_IDATA_BANK1_ENABLE_SET | CPU1_IDATA_BANK0_ENABLE_SET | CPU1_ITAG_RAM3_ENABLE_SET | CPU1_ITAG_RAM2_ENABLE_SET | CPU1_ITAG_RAM1_ENABLE_SET | CPU1_ITAG_RAM0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_axi2vbusm_periph_mst_write_edc_pend |
30 | CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_axi2vbusm_mem_mst_read_edc_pend |
29 | CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_axi2vbusm_mem_mst_write_edc_pend |
28 | CPU1_VBUSM2AXI_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_vbusm2axi_edc_pend |
27 | CPU1_KS_VIM_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ks_vim_ramecc_pend |
26 | B1TCM1_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for b1tcm1_bank1_pend |
25 | B1TCM1_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for b1tcm1_bank0_pend |
24 | B0TCM1_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for b0tcm1_bank1_pend |
23 | B0TCM1_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for b0tcm1_bank0_pend |
22 | ATCM1_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for atcm1_bank1_pend |
21 | ATCM1_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for atcm1_bank0_pend |
20 | CPU1_DDATA_RAM7_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram7_pend |
19 | CPU1_DDATA_RAM6_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram6_pend |
18 | CPU1_DDATA_RAM5_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram5_pend |
17 | CPU1_DDATA_RAM4_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram4_pend |
16 | CPU1_DDATA_RAM3_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram3_pend |
15 | CPU1_DDATA_RAM2_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram2_pend |
14 | CPU1_DDATA_RAM1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram1_pend |
13 | CPU1_DDATA_RAM0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddata_ram0_pend |
12 | CPU1_DDIRTY_RAM_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ddirty_ram_pend |
11 | CPU1_DTAG_RAM3_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_dtag_ram3_pend |
10 | CPU1_DTAG_RAM2_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_dtag_ram2_pend |
9 | CPU1_DTAG_RAM1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_dtag_ram1_pend |
8 | CPU1_DTAG_RAM0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_dtag_ram0_pend |
7 | CPU1_IDATA_BANK3_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_idata_bank3_pend |
6 | CPU1_IDATA_BANK2_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_idata_bank2_pend |
5 | CPU1_IDATA_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_idata_bank1_pend |
4 | CPU1_IDATA_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_idata_bank0_pend |
3 | CPU1_ITAG_RAM3_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_itag_ram3_pend |
2 | CPU1_ITAG_RAM2_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_itag_ram2_pend |
1 | CPU1_ITAG_RAM1_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_itag_ram1_pend |
0 | CPU1_ITAG_RAM0_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_itag_ram0_pend |
R5FSS_CPU1_DED_ENABLE_SET_REG1 is shown in Figure 6-113 and described in Table 6-264.
Return to Summary Table.
DED interrupt enable set register 1.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0184h |
R5FSS0_ECC_AGGR | 05B1 0184h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU1_EDC_CTRL_ENABLE_SET | CPU1_AHB2VBUSP_EDC_ENABLE_SET | CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET | ||||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | CPU1_EDC_CTRL_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_edc_ctrl_pend |
1 | CPU1_AHB2VBUSP_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_ahb2vbusp_edc_pend |
0 | CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for cpu1_axi2vbusm_periph_mst_read_edc_pend |
R5FSS_CPU1_DED_ENABLE_CLR_REG0 is shown in Figure 6-114 and described in Table 6-266.
Return to Summary Table.
DED interrupt enable clear register 0.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 01C0h |
R5FSS0_ECC_AGGR | 05B1 01C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR | CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR | CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR | CPU1_VBUSM2AXI_EDC_ENABLE_CLR | CPU1_KS_VIM_RAMECC_ENABLE_CLR | B1TCM1_BANK1_ENABLE_CLR | B1TCM1_BANK0_ENABLE_CLR | B0TCM1_BANK1_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
B0TCM1_BANK0_ENABLE_CLR | ATCM1_BANK1_ENABLE_CLR | ATCM1_BANK0_ENABLE_CLR | CPU1_DDATA_RAM7_ENABLE_CLR | CPU1_DDATA_RAM6_ENABLE_CLR | CPU1_DDATA_RAM5_ENABLE_CLR | CPU1_DDATA_RAM4_ENABLE_CLR | CPU1_DDATA_RAM3_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU1_DDATA_RAM2_ENABLE_CLR | CPU1_DDATA_RAM1_ENABLE_CLR | CPU1_DDATA_RAM0_ENABLE_CLR | CPU1_DDIRTY_RAM_ENABLE_CLR | CPU1_DTAG_RAM3_ENABLE_CLR | CPU1_DTAG_RAM2_ENABLE_CLR | CPU1_DTAG_RAM1_ENABLE_CLR | CPU1_DTAG_RAM0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU1_IDATA_BANK3_ENABLE_CLR | CPU1_IDATA_BANK2_ENABLE_CLR | CPU1_IDATA_BANK1_ENABLE_CLR | CPU1_IDATA_BANK0_ENABLE_CLR | CPU1_ITAG_RAM3_ENABLE_CLR | CPU1_ITAG_RAM2_ENABLE_CLR | CPU1_ITAG_RAM1_ENABLE_CLR | CPU1_ITAG_RAM0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_axi2vbusm_periph_mst_write_edc_pend |
30 | CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_axi2vbusm_mem_mst_read_edc_pend |
29 | CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_axi2vbusm_mem_mst_write_edc_pend |
28 | CPU1_VBUSM2AXI_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_vbusm2axi_edc_pend |
27 | CPU1_KS_VIM_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ks_vim_ramecc_pend |
26 | B1TCM1_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for b1tcm1_bank1_pend |
25 | B1TCM1_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for b1tcm1_bank0_pend |
24 | B0TCM1_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for b0tcm1_bank1_pend |
23 | B0TCM1_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for b0tcm1_bank0_pend |
22 | ATCM1_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for atcm1_bank1_pend |
21 | ATCM1_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for atcm1_bank0_pend |
20 | CPU1_DDATA_RAM7_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram7_pend |
19 | CPU1_DDATA_RAM6_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram6_pend |
18 | CPU1_DDATA_RAM5_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram5_pend |
17 | CPU1_DDATA_RAM4_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram4_pend |
16 | CPU1_DDATA_RAM3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram3_pend |
15 | CPU1_DDATA_RAM2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram2_pend |
14 | CPU1_DDATA_RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram1_pend |
13 | CPU1_DDATA_RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddata_ram0_pend |
12 | CPU1_DDIRTY_RAM_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ddirty_ram_pend |
11 | CPU1_DTAG_RAM3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_dtag_ram3_pend |
10 | CPU1_DTAG_RAM2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_dtag_ram2_pend |
9 | CPU1_DTAG_RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_dtag_ram1_pend |
8 | CPU1_DTAG_RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_dtag_ram0_pend |
7 | CPU1_IDATA_BANK3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_idata_bank3_pend |
6 | CPU1_IDATA_BANK2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_idata_bank2_pend |
5 | CPU1_IDATA_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_idata_bank1_pend |
4 | CPU1_IDATA_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_idata_bank0_pend |
3 | CPU1_ITAG_RAM3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_itag_ram3_pend |
2 | CPU1_ITAG_RAM2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_itag_ram2_pend |
1 | CPU1_ITAG_RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_itag_ram1_pend |
0 | CPU1_ITAG_RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_itag_ram0_pend |
R5FSS_CPU1_DED_ENABLE_CLR_REG1 is shown in Figure 6-115 and described in Table 6-268.
Return to Summary Table.
DED interrupt enable clear register 1.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 01C4h |
R5FSS0_ECC_AGGR | 05B1 01C4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU1_EDC_CTRL_ENABLE_CLR | CPU1_AHB2VBUSP_EDC_ENABLE_CLR | CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR | ||||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | CPU1_EDC_CTRL_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_edc_ctrl_pend |
1 | CPU1_AHB2VBUSP_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_ahb2vbusp_edc_pend |
0 | CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for cpu1_axi2vbusm_periph_mst_read_edc_pend |
R5FSS_CPU1_AGGR_ENABLE_SET is shown in Figure 6-116 and described in Table 6-270.
Return to Summary Table.
AGGR interrupt enable set register.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0200h |
R5FSS0_ECC_AGGR | 05B1 0200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | Interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | Interrupt enable set for parity errors |
R5FSS_CPU1_AGGR_ENABLE_CLR is shown in Figure 6-117 and described in Table 6-272.
Return to Summary Table.
AGGR interrupt enable clear register.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0204h |
R5FSS0_ECC_AGGR | 05B1 0204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | Interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | Interrupt enable clear for parity errors |
R5FSS_CPU1_AGGR_STATUS_SET is shown in Figure 6-118 and described in Table 6-274.
Return to Summary Table.
AGGR interrupt status set register.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 0208h |
R5FSS0_ECC_AGGR | 05B1 0208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/W | 0h | interrupt status set for svbus timeout errors |
1-0 | PARITY | R/W | 0h | interrupt status set for parity errors |
R5FSS_CPU1_AGGR_STATUS_CLR is shown in Figure 6-119 and described in Table 6-276.
Return to Summary Table.
AGGR interrupt status clear register.
Instance | Physical Address |
---|---|
MCU_R5FSS0_ECC_AGGR | 400C 020Ch |
R5FSS0_ECC_AGGR | 05B1 020Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/W | 0h | Interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/W | 0h | Interrupt status clear for parity errors |