The following sequence has to be performed in order to gate the MSMC0 clock:
- All A72SS connected to MSMC0 shall be in clkstop (or) powerdown state:
- Ensure that all Direct-TR initiated by the respective core is complete (by polling TR complete register).
- A72SS powerdown sequencing are described in the respective sections in Arm® Cortex®-A72 MPCore Processor Technical Reference Manual, available at http://infocenter.arm.com/help/index.jsp.
- This ensures that MSMC_*_CPU_PWR_SCR_DISABLE_ACK is asserted for all CorePacs (and EN_ACK if connected to an Arm CorePac are IDLE).
- Note that L3 cache may have dirty lines at this point and needs to be written back to DDRSS0 RAM.
- DRU has to be taken into idle state:
- System software ensures that DRU does not initiate any new requests.
- UDMA-P initiated TR need to be completed.
- System de-asserts the PSIL link slave port of NAVSS0 to DRU.
- System ensures that VBUSP_CFG, VBUSP_DBG, and VBUSP_DMSC slave ports are disconnected in CBASS0.
- System software guarantees that SoC0/SoC1 ports do not initiate any transactions to DDRSS0 or MSMC0 SRAM.
- System software to disable MSMC0 scrubber.
- System software to change L3 cache size to 0 by writing to MSMC0 CACHE_CTRL register:
- Note: This operation has to done by secure software running in WKUP_DMSC0 only. User code shall not be allowed to change L3 cache size.
- Results in L3 cache flush to DDRSS0.
- Software to poll MSMC0 CACHE_CTRL register to ensure that L3 cache size change is complete.
- PSC0 disconnects DDRSS0 slave interfaces of MSMC0 and MSMC0 core asserts MSMC_*_EMIF_PWR_SCR_DISABLE_ACK.
- PSC0 ensures SoC0 slave port from NAVSS0 to MSMC0 is disconnected at NAVSS0. Note that this will result in WKUP_DMSC0 not being able to access MSMC0 control registers.
- PSC0 disconnects SoC0/SoC1 slave interfaces of MSMC0 and MSMC0 core asserts MSMC_*_SoC*_PWR_SCR_DISABLE_ACK.
- System asserts MSMC_CLKSTOP_REQ.
- MSMC_WRAP asserts MSMC_CLKSTOP_ACK. This factors in idle of all the MSMC0_WRAP components as well:
- MSMC_CORE_IDLE, DRU_IDLE
- VBUSP_DBG, VBUSP_CFG, VBUSP_DMSC interfaces idle
- DRU_PSIL_LINK (output of MSMC) is ‘0’ – denotes disconnected.
- System can gate the clocks to MSMC_WRAP.