SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-2187 lists the memory-mapped registers for the CPSW0_RAM. All register offset addresses not listed in Table 12-2187 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
CPSW0_NUSS_RAM | 0C00 0000h |
Offset | Acronym | Register Name | CPSW0_NUSS_RAM Physical Address |
---|---|---|---|
00032000h + formula | CPSW_FETCH_LOC_y | RAM Location Register | 0C03 2000h + formula |
CPSW_FETCH_LOC_y is shown in Figure 12-1129 and described in Table 12-2189.
Return to Summary Table.
These are the RAM locations for one Ethernet port.
Offset = 00032000h + (y * 4h); where y = 0h to 3FFh
Instance | Physical Address |
---|---|
CPSW0_NUSS_RAM | 0C03 2000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOC | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R/W | X | |
21-0 | LOC | R/W | 0h | RAM Location. |