SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-4344 lists the memory-mapped registers for the MMCSD0 Subsystem. All register offset addresses not listed in Table 12-4344 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MMCSD0_SS_CFG | 04F8 8000h |
Offset | Acronym | Register Name | MMCSD0_SS_CFG Physical Address |
---|---|---|---|
0h | MMCSD0_SS_SS_ID_REV_REG | Subsystem ID and Revision Register | 04F8 8000h |
10h | MMCSD0_SS_CTL_CFG_1_REG | Controller Config 1 Register | 04F8 8010h |
14h | MMCSD0_SS_CTL_CFG_2_REG | Controller Config 2 Register | 04F8 8014h |
18h | MMCSD0_SS_CTL_CFG_3_REG | Controller Config 3 Register | 04F8 8018h |
1Ch | MMCSD0_SS_CTL_CFG_4_REG | Controller Config 4 Register | 04F8 801Ch |
20h | MMCSD0_SS_CTL_CFG_5_REG | Controller Config 5 Register | 04F8 8020h |
24h | MMCSD0_SS_CTL_CFG_6_REG | Controller Config 6 Register | 04F8 8024h |
28h | MMCSD0_SS_CTL_CFG_7_REG | Controller Config 7 Register | 04F8 8028h |
2Ch | MMCSD0_SS_CTL_CFG_8_REG | Controller Config 8 Register | 04F8 802Ch |
30h | MMCSD0_SS_CTL_CFG_9_REG | Controller Config 9 Register | 04F8 8030h |
34h | MMCSD0_SS_CTL_CFG_10_REG | Controller Config 10 Register | 04F8 8034h |
38h | MMCSD0_SS_CTL_CFG_11_REG | Controller Config 11 Register | 04F8 8038h |
3Ch | MMCSD0_SS_CTL_CFG_12_REG | Controller Config 12 Register | 04F8 803Ch |
40h | MMCSD0_SS_CTL_CFG_13_REG | Controller Config 13 Register | 04F8 8040h |
44h | MMCSD0_SS_CTL_CFG_14_REG | Controller Config 14 Register | 04F8 8044h |
60h | MMCSD0_SS_CTL_STAT_1_REG | Controller Status 1 Register | 04F8 8060h |
64h | MMCSD0_SS_CTL_STAT_2_REG | Controller Status 2 Register | 04F8 8064h |
68h | MMCSD0_SS_CTL_STAT_3_REG | Controller Status 3 Register | 04F8 8068h |
6Ch | MMCSD0_SS_CTL_STAT_4_REG | Controller Status 4 Register | 04F8 806Ch |
70h | MMCSD0_SS_CTL_STAT_5_REG | Controller Status 5 Register | 04F8 8070h |
74h | MMCSD0_SS_CTL_STAT_6_REG | Controller Status 6 Register | 04F8 8074h |
100h | MMCSD0_SS_PHY_CTRL_1_REG | PHY Control 1 Register | 04F8 8100h |
104h | MMCSD0_SS_PHY_CTRL_2_REG | PHY Control 2 Register | 04F8 8104h |
108h | MMCSD0_SS_PHY_CTRL_3_REG | PHY Control 3 Register | 04F8 8108h |
10Ch | MMCSD0_SS_PHY_CTRL_4_REG | PHY Control 4 Register | 04F8 810Ch |
110h | MMCSD0_SS_PHY_CTRL_5_REG | PHY Control 5 Register | 04F8 8110h |
114h | MMCSD0_SS_PHY_CTRL_6_REG | PHY Control 6 Register | 04F8 8114h |
130h | MMCSD0_SS_PHY_STAT_1_REG | PHY Status 1 Register | 04F8 8130h |
134h | MMCSD0_SS_PHY_STAT_2_REG | PHY Status 2 Register | 04F8 8134h |
MMCSD0_SS_SS_ID_REV_REG is shown in Figure 12-2256 and described in Table 12-4346.
Return to Summary Table.
The Subsystem ID and Revision Register contains the module ID, major, and minor revisions for the subsystem.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MOD_ID | |||||||||||||||
R-6841h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL_VER | MAJ_REV | CUSTOM | MIN_REV | ||||||||||||
R-9h | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MOD_ID | R | 6841h | Module ID |
15-11 | RTL_VER | R | 9h | RTL Version |
10-8 | MAJ_REV | R | 2h | Major Revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | MIN_REV | R | 0h | Minor Revision |
MMCSD0_SS_CTL_CFG_1_REG is shown in Figure 12-2257 and described in Table 12-4348.
Return to Summary Table.
The Controller Config 1 Register contains various fields to control the configuration ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | TUNINGCOUNT | ||||||
R-0h | R/W-20h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ASYNCWKUPENA | RESERVED | |||||
R-0h | R/W-1h | R-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CQFMUL | RESERVED | CQFVAL | |||||
R/W-3h | R-0h | R/W-C8h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CQFVAL | |||||||
R/W-C8h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R | 0h | Reserved |
29-24 | TUNINGCOUNT | R/W | 20h | Configures the number of Taps (Phases) of the RX clock that is
supported. |
23-21 | RESERVED | R | 0h | Reserved |
20 | ASYNCWKUPENA | R/W | 1h | Determines the Wakeup Signal Generation Mode. |
19-16 | RESERVED | R | 0h | Reserved |
15-12 | CQFMUL | R/W | 3h | FMUL for the CQ Internal Timer Clock Frequency |
11-10 | RESERVED | R | 0h | Reserved |
9-0 | CQFVAL | R/W | C8h | FVAL for the CQ Internal Timer Clock Frequency |
MMCSD0_SS_CTL_CFG_2_REG is shown in Figure 12-2258 and described in Table 12-4350.
Return to Summary Table.
The Controller Config 2 Register contains various fields to control the configuration ports on the Host Controller. This register sets the LSB fields in the MMCSD0_CAPABILITIES register inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SLOTTYPE | ASYNCHINTRSUPPORT | RESERVED | SUPPORT1P8VOLT | SUPPORT3P0VOLT | SUPPORT3P3VOLT | ||
R/W-0h | R/W-1h | R-0h | R/W-1h | R/W-0h | R/W-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SUSPRESSUPPORT | SDMASUPPORT | HIGHSPEEDSUPPORT | RESERVED | ADMA2SUPPORT | SUPPORT8BIT | MAXBLKLENGTH | |
R/W-1h | R/W-1h | R/W-1h | R-0h | R/W-1h | R/W-1h | R/W-0h | |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BASECLKFREQ | |||||||
R/W-C8h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIMEOUTCLKUNIT | RESERVED | TIMEOUTCLKFREQ | |||||
R/W-0h | R-0h | R/W-1h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SLOTTYPE | R/W | 0h | Slot Type Should
be set based on the final product usage. |
29 | ASYNCHINTRSUPPORT | R/W | 1h | Asynchronous Interrupt Support Suggested Value is 1h (The Core supports monitoring of Asynchronous Interrupt). |
28-27 | RESERVED | R | 0h | Reserved |
26 | SUPPORT1P8VOLT | R/W | 1h | 1.8 V Support Suggested Value is 1h (The 1.8 Volt Switching is supported by
Core). |
25 | SUPPORT3P0VOLT | R/W | 0h | 3.0 V Support Should be set based on whether 3.0 V is supported on the SD Interface. |
24 | SUPPORT3P3VOLT | R/W | 0h | 3.3 V Support Suggested Value is 1h as the 3.3 V is the default voltage on the SD Interface. |
23 | SUSPRESSUPPORT | R/W | 1h | Suspend/Resume Support Suggested Value
is 1h (The Suspend/Resume is supported by Core). |
22 | SDMASUPPORT | R/W | 1h | SDMA Support Suggested Value is 1h (The SDMA is supported by Core). |
21 | HIGHSPEEDSUPPORT | R/W | 1h | High Speed Support Suggested Value is 1h (The High Speed mode is supported by Core). |
20 | RESERVED | R | 0h | Reserved |
19 | ADMA2SUPPORT | R/W | 1h | ADMA2 Support Suggested Value
is 1h (The ADMA2 is supported by Core). |
18 | SUPPORT8BIT | R/W | 1h | 8-bit Support for Embedded Device Suggested Value
is 1h (The Core supports 8-bit Interface). |
17-16 | MAXBLKLENGTH | R/W | 0h | Max Block Length Maximum Block
Length supported by the Core/Device. |
15-8 | BASECLKFREQ | R/W | C8h | Base Clock Frequency for SD Clock This is the frequency of the FCLK. |
7 | TIMEOUTCLKUNIT | R/W | 0h | Timeout Clock Unit Suggested Value is 0h (KHz). |
6 | RESERVED | R | 0h | Reserved |
5-0 | TIMEOUTCLKFREQ | R/W | 1h | Timeout Clock Frequency Suggested Value
is 1 KHz. |
MMCSD0_SS_CTL_CFG_3_REG is shown in Figure 12-2259 and described in Table 12-4352.
Return to Summary Table.
The Controller Config 3 Register contains various fields to control the configuration ports on the Host Controller. This register sets the MSB fields in the MMCSD0_CAPABILITIES register inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
HS400SUPPORT | RESERVED | SUPPORT1P8VDD2 | ADMA3SUPPORT | RESERVED | |||
R/W-1h | R-0h | R/W-1h | R/W-1h | R-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLOCKMULTIPLIER | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RETUNINGMODES | TUNINGFORSDR50 | RESERVED | RETUNINGTIMERCNT | ||||
R/W-0h | R/W-0h | R-0h | R/W-4h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TYPE4SUPPORT | DDRIVERSUPPORT | CDRIVERSUPPORT | ADRIVERSUPPORT | RESERVED | DDR50SUPPORT | SDR104SUPPORT | SDR50SUPPORT |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-1h | R/W-1h | R/W-1h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | HS400SUPPORT | R/W | 1h | HS400 Support Suggested Value
is 1h (The Core supports HS400 Mode). |
30-29 | RESERVED | R | 0h | Reserved |
28 | SUPPORT1P8VDD2 | R/W | 1h | 1.8 V VDD2 Support |
27 | ADMA3SUPPORT | R/W | 1h | ADMA3 Support |
26-24 | RESERVED | R | 0h | Reserved |
23-16 | CLOCKMULTIPLIER | R/W | 0h | Clock Multiplier This field
indicates clock multiplier value of programmable clock
generator. |
15-14 | RETUNINGMODES | R/W | 0h | Re-Tuning Modes Should be set to 2h as the Core supports only the Software Timer based Re-Tuning. |
13 | TUNINGFORSDR50 | R/W | 0h | Use Tuning for SDR50 This bit should
be set if the application wants Tuning be used for SDR50
Modes. |
12 | RESERVED | R | 0h | Reserved |
11-8 | RETUNINGTIMERCNT | R/W | 4h | Timer Count for Re-Tuning This is the Timer
Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. |
7 | TYPE4SUPPORT | R/W | 0h | Driver Type 4 Support This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not. |
6 | DDRIVERSUPPORT | R/W | 0h | Driver Type D Support This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not. |
5 | CDRIVERSUPPORT | R/W | 0h | Driver Type C Support This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not. |
4 | ADRIVERSUPPORT | R/W | 0h | Driver Type A Support This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not. |
3 | RESERVED | R | 0h | Reserved |
2 | DDR50SUPPORT | R/W | 1h | DDR50 Support Suggested Value
is 1h (The Core supports DDR50 mode of operation). |
1 | SDR104SUPPORT | R/W | 1h | SDR104 Support. |
0 | SDR50SUPPORT | R/W | 1h | SDR50 Support. |
MMCSD0_SS_CTL_CFG_4_REG is shown in Figure 12-2260 and described in Table 12-4354.
Return to Summary Table.
The Controller Config 4 Register contains various fields to control the configuration ports on the Host Controller. This register sets the LSB fields in the MMCSD0_MAX_CURRENT_CAP register inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 801Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | MAXCURRENT1P8V | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAXCURRENT3P0V | MAXCURRENT3P3V | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-16 | MAXCURRENT1P8V | R/W | 0h | Maximum Current For 1.8 V |
15-8 | MAXCURRENT3P0V | R/W | 0h | Maximum Current For 3.0 V |
7-0 | MAXCURRENT3P3V | R/W | 0h | Maximum Current For 3.3 V |
MMCSD0_SS_CTL_CFG_5_REG is shown in Figure 12-2261 and described in Table 12-4356.
Return to Summary Table.
The Controller Config 5 Register contains various fields to control the configuration ports on the Host Controller. This register sets the MSB fields in the MMCSD0_MAX_CURRENT_CAP register inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MAXCURRENTVDD2 | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | MAXCURRENTVDD2 | R/W | 0h | Maximum Current For 1.8 V (VDD2) |
MMCSD0_SS_CTL_CFG_6_REG is shown in Figure 12-2262 and described in Table 12-4358.
Return to Summary Table.
The Controller Config 6 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE0 to MMCSD0_PRESET_VALUE10) for Initialization inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INITPRESETVAL | ||||||||||||||||||||||||||||||
R-0h | R/W-100h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | INITPRESETVAL | R/W | 100h | Preset Value For Initialization |
MMCSD0_SS_CTL_CFG_7_REG is shown in Figure 12-2263 and described in Table 12-4360.
Return to Summary Table.
The Controller Config 7 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE0 to MMCSD0_PRESET_VALUE10) for Default Speed inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DSPDPRESETVAL | ||||||||||||||||||||||||||||||
R-0h | R/W-4h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | DSPDPRESETVAL | R/W | 4h | Preset Value For Default Speed |
MMCSD0_SS_CTL_CFG_8_REG is shown in Figure 12-2264 and described in Table 12-4362.
Return to Summary Table.
The Controller Config 8 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE0 to MMCSD0_PRESET_VALUE10) for High Speed inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 802Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSPDPRESETVAL | ||||||||||||||||||||||||||||||
R-0h | R/W-2h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | HSPDPRESETVAL | R/W | 2h | Preset Value For High Speed |
MMCSD0_SS_CTL_CFG_9_REG is shown in Figure 12-2265 and described in Table 12-4364.
Return to Summary Table.
The Controller Config 9 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE0 to MMCSD0_PRESET_VALUE10) for SDR12 inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SDR12PRESETVAL | ||||||||||||||
R-0h | R/W-4h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | SDR12PRESETVAL | R/W | 4h | Preset Value For SDR12 |
MMCSD0_SS_CTL_CFG_10_REG is shown in Figure 12-2266 and described in Table 12-4366.
Return to Summary Table.
The Controller Config 10 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE0 to MMCSD0_PRESET_VALUE10) for SDR25 inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SDR25PRESETVAL | ||||||||||||||
R-0h | R/W-2h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | SDR25PRESETVAL | R/W | 2h | Preset Value For SDR25 |
MMCSD0_SS_CTL_CFG_11_REG is shown in Figure 12-2267 and described in Table 12-4368.
Return to Summary Table.
The Controller Config 11 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE0 to MMCSD0_PRESET_VALUE10) for SDR50 inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SDR50PRESETVAL | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | SDR50PRESETVAL | R/W | 1h | Preset Value For SDR50 |
MMCSD0_SS_CTL_CFG_12_REG is shown in Figure 12-2268 and described in Table 12-4370.
Return to Summary Table.
The Controller Config 12 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE0 to MMCSD0_PRESET_VALUE10) for SDR104 inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 803Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SDR104PRESETVAL | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | SDR104PRESETVAL | R/W | 0h | Preset Value For SDR104 |
MMCSD0_SS_CTL_CFG_13_REG is shown in Figure 12-2269 and described in Table 12-4372.
Return to Summary Table.
The Controller Config 13 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE0 to MMCSD0_PRESET_VALUE10) for DDR50 inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DDR50PRESETVAL | ||||||||||||||
R-0h | R/W-2h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | DDR50PRESETVAL | R/W | 2h | Preset Value For DDR50 |
MMCSD0_SS_CTL_CFG_14_REG is shown in Figure 12-2270 and described in Table 12-4374.
Return to Summary Table.
The Controller Config 14 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE0 to MMCSD0_PRESET_VALUE10) for HS400 inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HS400PRESETVAL | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | HS400PRESETVAL | R/W | 1h | Preset Value For HS400 |
MMCSD0_SS_CTL_STAT_1_REG is shown in Figure 12-2271 and described in Table 12-4376.
Return to Summary Table.
The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SDHC_CMDIDLE | RESERVED | ||||||
R-1h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMADEBUGBUS | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMADEBUGBUS | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SDHC_CMDIDLE | R | 1h | Idle signal to enable software to gate off the clocks |
30-16 | RESERVED | R | 0h | Reserved |
15-0 | DMADEBUGBUS | R | 0h | DMA_CTRL Debug Bus |
MMCSD0_SS_CTL_STAT_2_REG is shown in Figure 12-2272 and described in Table 12-4378.
Return to Summary Table.
The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMDDEBUGBUS | ||||||||||||||||||||||||||||||
R-0h | R-10h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | CMDDEBUGBUS | R | 10h | CMD_CTRL Debug Bus |
MMCSD0_SS_CTL_STAT_3_REG is shown in Figure 12-2273 and described in Table 12-4380.
Return to Summary Table.
The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8068h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXDDEBUGBUS | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | TXDDEBUGBUS | R | 0h | TXD_CTRL Debug Bus |
MMCSD0_SS_CTL_STAT_4_REG is shown in Figure 12-2274 and described in Table 12-4382.
Return to Summary Table.
The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 806Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXDDEBUGBUS0 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | RXDDEBUGBUS0 | R | 0h | RXD_CTRL Debug Bus (SD CLK) |
MMCSD0_SS_CTL_STAT_5_REG is shown in Figure 12-2275 and described in Table 12-4384.
Return to Summary Table.
The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXDDEBUGBUS1 | ||||||||||||||||||||||||||||||
R-0h | R-8h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | RXDDEBUGBUS1 | R | 8h | RXD_CTRL Debug Bus (RX CLK) |
MMCSD0_SS_CTL_STAT_6_REG is shown in Figure 12-2276 and described in Table 12-4386.
Return to Summary Table.
The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TUNDEBUGBUS | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | TUNDEBUGBUS | R | 0h | TUN_CTRL Debug Bus |
MMCSD0_SS_PHY_CTRL_1_REG is shown in Figure 12-2277 and described in Table 12-4388.
Return to Summary Table.
The PHY Control 1 Register contains various fields to control the ports on the Host Controller PHY.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DR_TY | RESERVED | RETRIM | EN_RTRIM | |||
R-0h | R/W-0h | R-0h | R/W-0h | R/W-1h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLL_TRM_ICP | RESERVED | ENDLL | PDB | ||||
R/W-0h | R-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R | 0h | Reserved |
22-20 | DR_TY | R/W | 0h | Drive Source/Sink Impedance Programming 0h: 50 Ohms |
19-18 | RESERVED | R | 0h | Reserved |
17 | RETRIM | R/W | 0h | Start CALIO Calibration Cycle At positive edge initiates CALIO calibration cycle. |
16 | EN_RTRIM | R/W | 1h | CALIO Enable Enables CALIO, If enabled CALIO will start calibration cycle at phyctrl_pdb positive edge. |
15-8 | RESERVED | R | 0h | Reserved |
7-4 | DLL_TRM_ICP | R/W | 0h | Analog DLL's Charge Pump Current Trim Programs the analog DLL loop gain. |
3-2 | RESERVED | R | 0h | Reserved |
1 | ENDLL | R/W | 0h | Enable DLL Enables the analog DLL circuits. |
0 | PDB | R/W | 0h | CALIO S/M Power Down Bar SoC asserts after power up sequence is completed. |
MMCSD0_SS_PHY_CTRL_2_REG is shown in Figure 12-2278 and described in Table 12-4390.
Return to Summary Table.
The PHY Control 2 Register contains various fields to control the ports on the Host Controller PHY.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8104h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | OD_RELEASE_STRB | OD_RELEASE_CMD | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
OD_RELEASE_DAT | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ODEN_STRB | ODEN_CMD | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ODEN_DAT | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R | 0h | Reserved |
29 | OD_RELEASE_STRB | R/W | 0h | Disable an internal 4.7 K pull up resistor on STRB line in open drain mode |
28 | OD_RELEASE_CMD | R/W | 0h | Disable an internal 4.7 K pull up resistor on CMD line in open drain mode |
27-24 | RESERVED | R | 0h | Reserved |
23-16 | OD_RELEASE_DAT | R/W | 0h | Disable an internal 4.7 K pull up resistor on data lines in open drain mode |
15-14 | RESERVED | R | 0h | Reserved |
13 | ODEN_STRB | R/W | 0h | Open Drain Enable On STRB Lline |
12 | ODEN_CMD | R/W | 0h | Open Drain Enable On CMD Line |
11-8 | RESERVED | R | 0h | Reserved |
7-0 | ODEN_DAT | R/W | 0h | Open Drain Enable On DAT Lines |
MMCSD0_SS_PHY_CTRL_3_REG is shown in Figure 12-2279 and described in Table 12-4392.
Return to Summary Table.
The PHY Control 3 Register contains various fields to control the ports on the Host Controller PHY.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8108h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PU_STRB | PU_CMD | RESERVED | ||||
R-0h | R/W-0h | R/W-1h | R-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PU_DAT | |||||||
R/W-FFh | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | REN_STRB | REN_CMD | RESERVED | ||||
R-0h | R/W-0h | R/W-1h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REN_DAT | |||||||
R/W-FFh | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R | 0h | Reserved |
29 | PU_STRB | R/W | 0h | Enable Pull Up On STRB Line If ren_strb is high week pull up is enabled on STRB line. |
28 | PU_CMD | R/W | 1h | Enable Pull Up On CMD Line If ren_cmd is high week pull up is enabled on CMD line. |
27-24 | RESERVED | R | 0h | Reserved |
23-16 | PU_DAT | R/W | FFh | Enable Pull Up On DAT Lines If ren_dat is high week pull up is enabled on DATA lines. |
15-14 | RESERVED | R | 0h | Reserved |
13 | REN_STRB | R/W | 1h | Enable Pull Up/Down On The STRB Line If pu_strb is high a week pull up is enabled on STRB line, if low week pull down is enabled on STRB line. |
12 | REN_CMD | R/W | 1h | Enable Pull Up/Down On The CMD Line If pu_cmd is high a week pull up is enabled on CMD line, if low week pull down is enabled on CMD line. |
11-8 | RESERVED | R | 0h | Reserved |
7-0 | REN_DAT | R/W | FFh | Enable Pull Up/Down On The DAT Lines If pu_dat is high a week pull up is enabled on DATA lines, if low week pull down is enabled on DATA lines. |
MMCSD0_SS_PHY_CTRL_4_REG is shown in Figure 12-2280 and described in Table 12-4394.
Return to Summary Table.
The PHY Control 4 Register contains various fields to control the ports on the Host Controller PHY.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 810Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
STRBSEL | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | OTAPDLYENA | RESERVED | |||||
R-0h | R/W-0h | R-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OTAPDLYSEL | RESERVED | ITAPCHGWIN | ITAPDLYENA | ||||
R/W-0h | R-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ITAPDLYSEL | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | STRBSEL | R/W | 0h | Select the Four Taps for each of STRB_90 and STRB_180 Outputs.
|
23-21 | RESERVED | R | 0h | Reserved |
20 | OTAPDLYENA | R/W | 0h | Output Tap Delay Enable Enables manual control of the TX clock tap delay, for clocking the final stage flops for maintaining Hold requirements on EMMC Interface. |
19-16 | RESERVED | R | 0h | Reserved |
15-12 | OTAPDLYSEL | R/W | 0h | Output Tap Delay Select Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface. |
11-10 | RESERVED | R | 0h | Reserved |
9 | ITAPCHGWIN | R/W | 0h | Input Tap Change Window It gets asserted
by the controller while changing the itapdlysel. |
8 | ITAPDLYENA | R/W | 0h | Input Tap Delay Enable This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes. |
7-5 | RESERVED | R | 0h | Reserved |
4-0 | ITAPDLYSEL | R/W | 0h | Input Tap Delay Select Manual control of the RX clock Tap Delay in the non HS200/HS400 modes. |
MMCSD0_SS_PHY_CTRL_5_REG is shown in Figure 12-2281 and described in Table 12-4396.
Return to Summary Table.
The PHY Control 5 Register contains various fields to control the ports on the Host Controller PHY.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8110h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | SELDLYTXCLK | SELDLYRXCLK | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FRQSEL | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLKBUFSEL | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | 0h | Reserved |
17 | SELDLYTXCLK | R/W | 0h | Select the Delay chain based txclk. |
16 | SELDLYRXCLK | R/W | 0h | Select the Delay chain based rxclk. |
15-11 | RESERVED | R | 0h | Reserved |
10-8 | FRQSEL | R/W | 0h | Select the frequency range of DLL operation: |
7-3 | RESERVED | R | 0h | Reserved |
2-0 | CLKBUFSEL | R/W | 0h | Clock Delay Buffer Select. |
MMCSD0_SS_PHY_CTRL_6_REG is shown in Figure 12-2282 and described in Table 12-4398.
Return to Summary Table.
The PHY Control 6 Register contains various fields to control the ports on the Host Controller PHY.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8114h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
BISTENABLE | BISTSTART | RESERVED | BISTMODE | ||||
R/W-0h | R/W-0h | R-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TESTCTRL | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | BISTENABLE | R/W | 0h | Internal BIST Operation Enable Enables the embedded BIST. |
30 | BISTSTART | R/W | 0h | Internal BIST Start Starts the embedded BIST operation. |
29-28 | RESERVED | R | 0h | Reserved |
27-24 | BISTMODE | R/W | 0h | Internal BIST Mode Select Select the embedded BIST mode of operation. |
23-8 | RESERVED | R | 0h | Reserved |
7-0 | TESTCTRL | R/W | 0h | PHY
Test Control: |
MMCSD0_SS_PHY_STAT_1_REG is shown in Figure 12-2283 and described in Table 12-4400.
Return to Summary Table.
The PHY Status 1 Register contains various fields to reflect the status of the Host Controller PHY ports.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8130h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTRIM | BISTDONE | EXR_NINST | CALDONE | DLLRDY | |||
R-Eh | R-0h | R-0h | R-0h | R-0h | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-4 | RTRIM | R | Eh | CALIO Calibration Result Holds the content of CALIO Impedance Calibration Result. |
3 | BISTDONE | R | 0h | Internal BIST Completed Test Cycle Indicates that the embedded BIST has completed the test cycle. |
2 | EXR_NINST | R | 0h | External Resistor On CALIO Absent Indicates trim cycle started and external resistor is absent. |
1 | CALDONE | R | 0h | STATUS, indicate that CALIO Calibration is completed successfully. |
0 | DLLRDY | R | 0h | DLL Ready Indicates that DLL loop is locked. |
MMCSD0_SS_PHY_STAT_2_REG is shown in Figure 12-2284 and described in Table 12-4402.
Return to Summary Table.
The PHY Status 2 Register contains various fields to reflect the status of the Host Controller PHY ports.
Instance | Physical Address |
---|---|
MMCSD0_SS_CFG | 04F8 8134h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BISTSTATUS | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BISTSTATUS | R | 0h | Internal BIST Data Compare Results BIST cycle data comparison results. |