SPRUIU1C User guide | 德州仪器 TI.com.cn

Table 12-3458 lists the PCIE_CORE_RP registers. All register offset addresses not listed in Table 12-3458 should be considered as reserved locations and the register contents should not be modified.

RC mode PCIE core registers. The Root Port (RP) register set is accessible only when the core is strapped in the Root Port mode. These registers are accessible only from the local management bus.

Table 12-2917 PCIE_CORE_RP Instances

Instance	Base Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0000h

Table 12-2918 PCIE_CORE_RP Registers

Offset	Acronym	PCIE1_CORE_DBN_CFG_PCIE_CORE Physical Address
0h	PCIE_CORE_RP_I_VENDOR_ID_DEVICE_ID	0D80 0000h
4h	PCIE_CORE_RP_I_COMMAND_STATUS	0D80 0004h
8h	PCIE_CORE_RP_I_REVISION_ID_CLASS_CODE	0D80 0008h
Ch	PCIE_CORE_RP_I_BIST_HEADER_LATENCY_CACHE_LINE	0D80 000Ch
10h	PCIE_CORE_RP_I_RC_BAR_0	0D80 0010h
14h	PCIE_CORE_RP_I_RC_BAR_1	0D80 0014h
18h	PCIE_CORE_RP_I_PCIE_BUS_NUMBERS	0D80 0018h
1Ch	PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT	0D80 001Ch
20h	PCIE_CORE_RP_I_PCIE_MEM_BASE_LIMIT	0D80 0020h
24h	PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_LIMIT	0D80 0024h
28h	PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_UPPER	0D80 0028h
2Ch	PCIE_CORE_RP_I_PCIE_PREFETCH_LIMIT_UPPER	0D80 002Ch
30h	PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT_UPPER	0D80 0030h
34h	PCIE_CORE_RP_I_CAPABILITIES_POINTER	0D80 0034h
38h	PCIE_CORE_RP_RSVD_0E	0D80 0038h
3Ch	PCIE_CORE_RP_I_INTRPT_LINE_INTRPT_PIN	0D80 003Ch
80h	PCIE_CORE_RP_I_PWR_MGMT_CAP	0D80 0080h
84h	PCIE_CORE_RP_I_PWR_MGMT_CTRL_STAT_REP	0D80 0084h
90h	PCIE_CORE_RP_I_MSI_CTRL_REG	0D80 0090h
94h	PCIE_CORE_RP_I_MSI_MSG_LOW_ADDR	0D80 0094h
98h	PCIE_CORE_RP_I_MSI_MSG_HI_ADDR	0D80 0098h
9Ch	PCIE_CORE_RP_I_MSI_MSG_DATA	0D80 009Ch
A0h	PCIE_CORE_RP_I_MSI_MASK	0D80 00A0h
A4h	PCIE_CORE_RP_I_MSI_PENDING_BITS	0D80 00A4h
B0h	PCIE_CORE_RP_I_MSIX_CTRL	0D80 00B0h
B4h	PCIE_CORE_RP_I_MSIX_TBL_OFFSET	0D80 00B4h
B8h	PCIE_CORE_RP_I_MSIX_PENDING_INTRPT	0D80 00B8h
C0h	PCIE_CORE_RP_I_PCIE_CAP_LIST	0D80 00C0h
C4h	PCIE_CORE_RP_I_PCIE_CAP	0D80 00C4h
C8h	PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS	0D80 00C8h
CCh	PCIE_CORE_RP_I_LINK_CAP	0D80 00CCh
D0h	PCIE_CORE_RP_I_LINK_CTRL_STATUS	0D80 00D0h
D4h	PCIE_CORE_RP_I_SLOT_CAPABILITY	0D80 00D4h
D8h	PCIE_CORE_RP_I_SLOT_CTRL_STATUS	0D80 00D8h
DCh	PCIE_CORE_RP_I_ROOT_CTRL_CAP	0D80 00DCh
E0h	PCIE_CORE_RP_I_ROOT_STATUS	0D80 00E0h
E4h	PCIE_CORE_RP_I_PCIE_CAP_2	0D80 00E4h
E8h	PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS_2	0D80 00E8h
ECh	PCIE_CORE_RP_I_LINK_CAP_2	0D80 00ECh
F0h	PCIE_CORE_RP_I_LINK_CTRL_STATUS_2	0D80 00F0h
100h	PCIE_CORE_RP_I_AER_ENHNCD_CAP	0D80 0100h
104h	PCIE_CORE_RP_I_UNCORR_ERR_STATUS	0D80 0104h
108h	PCIE_CORE_RP_I_UNCORR_ERR_MASK	0D80 0108h
10Ch	PCIE_CORE_RP_I_UNCORR_ERR_SEVERITY	0D80 010Ch
110h	PCIE_CORE_RP_I_CORR_ERR_STATUS	0D80 0110h
114h	PCIE_CORE_RP_I_CORR_ERR_MASK	0D80 0114h
118h	PCIE_CORE_RP_I_ADV_ERR_CAP_CTL	0D80 0118h
11Ch	PCIE_CORE_RP_I_HDR_LOG_0	0D80 011Ch
120h	PCIE_CORE_RP_I_HDR_LOG_1	0D80 0120h
124h	PCIE_CORE_RP_I_HDR_LOG_2	0D80 0124h
128h	PCIE_CORE_RP_I_HDR_LOG_3	0D80 0128h
12Ch	PCIE_CORE_RP_I_ROOT_ERR_CMD	0D80 012Ch
130h	PCIE_CORE_RP_I_ROOT_ERR_STAT	0D80 0130h
134h	PCIE_CORE_RP_I_ERR_SRC_ID	0D80 0134h
138h	PCIE_CORE_RP_I_TLP_PRE_LOG_0	0D80 0138h
150h	PCIE_CORE_RP_I_DEV_SER_NUM_CAP_HDR	0D80 0150h
154h	PCIE_CORE_RP_I_DEV_SER_NUM_0	0D80 0154h
158h	PCIE_CORE_RP_I_DEV_SER_NUM_1	0D80 0158h
300h	PCIE_CORE_RP_I_SEC_PCIE_CAP_HDR_REG	0D80 0300h
304h	PCIE_CORE_RP_I_LINK_CONTROL3	0D80 0304h
308h	PCIE_CORE_RP_I_LANE_ERROR_STATUS	0D80 0308h
30Ch	PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_0	0D80 030Ch
310h	PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_1	0D80 0310h
4C0h	PCIE_CORE_RP_I_VC_ENH_CAP_HEADER_REG	0D80 04C0h
4C4h	PCIE_CORE_RP_I_PORT_VC_CAP_REG_1	0D80 04C4h
4C8h	PCIE_CORE_RP_I_PORT_VC_CAP_REG_2	0D80 04C8h
4CCh	PCIE_CORE_RP_I_PORT_VC_CTRL_STS_REG	0D80 04CCh
4D0h	PCIE_CORE_RP_I_VC_RES_CAP_REG_0	0D80 04D0h
4D4h	PCIE_CORE_RP_I_VC_RES_CTRL_REG_0	0D80 04D4h
4D8h	PCIE_CORE_RP_I_VC_RES_STS_REG_0	0D80 04D8h
4DCh	PCIE_CORE_RP_I_VC_RES_CAP_REG_1	0D80 04DCh
4E0h	PCIE_CORE_RP_I_VC_RES_CTRL_REG_1	0D80 04E0h
4E4h	PCIE_CORE_RP_I_VC_RES_STS_REG_1	0D80 04E4h
4E8h	PCIE_CORE_RP_I_VC_RES_CAP_REG_2	0D80 04E8h
4ECh	PCIE_CORE_RP_I_VC_RES_CTRL_REG_2	0D80 04ECh
4F0h	PCIE_CORE_RP_I_VC_RES_STS_REG_2	0D80 04F0h
4F4h	PCIE_CORE_RP_I_VC_RES_CAP_REG_3	0D80 04F4h
4F8h	PCIE_CORE_RP_I_VC_RES_CTRL_REG_3	0D80 04F8h
4FCh	PCIE_CORE_RP_I_VC_RES_STS_REG_3	0D80 04FCh
900h	PCIE_CORE_RP_I_L1_PM_EXT_CAP_HDR	0D80 0900h
904h	PCIE_CORE_RP_I_L1_PM_CAP	0D80 0904h
908h	PCIE_CORE_RP_I_L1_PM_CTRL_1	0D80 0908h
90Ch	PCIE_CORE_RP_I_L1_PM_CTRL_2	0D80 090Ch
910h	PCIE_CORE_RP_I_DL_FEATURE_EXTENDED_CAPABILITY_HEADER_REG	0D80 0910h
914h	PCIE_CORE_RP_I_DL_FEATURE_CAPABILITIES_REG	0D80 0914h
918h	PCIE_CORE_RP_I_DL_FEATURE_STATUS_REG	0D80 0918h
920h	PCIE_CORE_RP_I_MARGINING_EXTENDED_CAPABILITY_HEADER_REG	0D80 0920h
924h	PCIE_CORE_RP_I_MARGINING_PORT_CAPABILITIES_STATUS_REG	0D80 0924h
928h	PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG0	0D80 0928h
92Ch	PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG1	0D80 092Ch
930h	PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG2	0D80 0930h
934h	PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG3	0D80 0934h
9C0h	PCIE_CORE_RP_I_PL_16GTS_EXTENDED_CAPABILITY_HEADER_REG	0D80 09C0h
9C4h	PCIE_CORE_RP_I_PL_16GTS_CAPABILITIES_REG	0D80 09C4h
9C8h	PCIE_CORE_RP_I_PL_16GTS_CONTROL_REG	0D80 09C8h
9CCh	PCIE_CORE_RP_I_PL_16GTS_STATUS_REG	0D80 09CCh
9D0h	PCIE_CORE_RP_I_PL_16GTS_LOCAL_DATA_PARITY_MISMATCH_STATUS_REG	0D80 09D0h
9D4h	PCIE_CORE_RP_I_PL_16GTS_FIRST_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG	0D80 09D4h
9D8h	PCIE_CORE_RP_I_PL_16GTS_SECOND_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG	0D80 09D8h
9DCh	PCIE_CORE_RP_I_PL_16GTS_RESERVED_REG	0D80 09DCh
9E0h	PCIE_CORE_RP_I_PL_16GTS_LANE_EQUALIZATION_CONTROL_REG0	0D80 09E0h
A20h	PCIE_CORE_RP_I_PTM_EXTENDED_CAPABILITY_HEADER_REG	0D80 0A20h
A24h	PCIE_CORE_RP_I_PTM_CAPABILITIES_REG	0D80 0A24h
A28h	PCIE_CORE_RP_I_PTM_CONTROL_REG	0D80 0A28h

3.5.3.1 PCIE_CORE_RP_I_VENDOR_ID_DEVICE_ID Register (Offset = 0h) [reset = 010017CDh]

PCIE_CORE_RP_I_VENDOR_ID_DEVICE_ID is shown in Figure 12-1489 and described in Table 12-2920.

Return to the Summary Table.

16-bit Vendor ID register and 16-bit Device ID register.

Table 12-2919 PCIE_CORE_RP_I_VENDOR_ID_DEVICE_ID Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0000h

Figure 12-1489 PCIE_CORE_RP_I_VENDOR_ID_DEVICE_ID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DID																VID
R-100h																R-17CDh

LEGEND: R = Read Only; -n = value after reset

Table 12-2920 PCIE_CORE_RP_I_VENDOR_ID_DEVICE_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	DID	R	100h	Device ID assigned by the manufacturer of the device. On power-up, the Controller sets it to the value defined in the RTL file reg_defaults.h. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
15-0	VID	R	17CDh	This is the Vendor ID assigned by PCI SIG to the manufacturer of the device. The Vendor ID is set in the Vendor ID Register within the local management register block.

3.5.3.2 PCIE_CORE_RP_I_COMMAND_STATUS Register (Offset = 4h) [reset = 00100000h]

PCIE_CORE_RP_I_COMMAND_STATUS is shown in Figure 12-1490 and described in Table 12-2922.

Return to the Summary Table.

16-bit Command Register and 16-bit Status Register.

Table 12-2921 PCIE_CORE_RP_I_COMMAND_STATUS Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0004h

Figure 12-1490 PCIE_CORE_RP_I_COMMAND_STATUS Register

31	30	29	28	27	26	25	24
DPE	SSE	RMA	RTA	STA	R6		MDPE
R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R-0h		R/W1C-0h

23	22	21	20	19	18	17	16
R5			CL	IS	R4
R-0h			R-1h	R-0h	R-0h

15	14	13	12	11	10	9	8
R3					IMD	R2	SE
R-0h					R/W-0h	R-0h	R/W-0h

7	6	5	4	3	2	1	0
R1	PERE	R0			BE	MSE	ISE
R-0h	R/W-0h	R-0h			R/W-0h	R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-2922 PCIE_CORE_RP_I_COMMAND_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DPE	R/W1C	0h	This bit is set when the Controller has received a poisoned TLP. The Parity Error Response enable bit [bit 6] has no effect on the setting of this bit. This field can also be cleared from the local management bus APB by writing a 1 into this bit position. This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
30	SSE	R/W1C	0h	The Controller sets this bit [i]On receiving an error message from the link, if SERR-Enable in PCI Command Register is 1 and SERR-Enable in the Bridge Control Register is also 1. [ii]On any internal Fatal/Non-Fatal error detected, if SERR-Enable in PCI Command Register is 1. This field can also be cleared from the local management APB bus by writing a 1 into this bit position. This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
29	RMA	R/W1C	0h	This bit is set when the Controller has received a completion from the link with the Unsupported Request status. This field can also be cleared from the local management APB bus by writing a 1 into this bit position This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
28	RTA	R/W1C	0h	This bit is set when the Controller has received a completion from the link with the Completer Abort status. This field can also be cleared from the local management APB bus by writing a 1 into this bit position. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
27	STA	R/W1C	0h	This bit is set when the Controller has sent a completion to the link with the Completer Abort status. This field can also be cleared from the local management APB bus by writing a 1 into this bit position. This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
26-25	R6	R	0h	Reserved
24	MDPE	R/W1C	0h	When the Parity Error Response enable bit is 1, the Controller sets this bit when it detects the following error conditions: [i] The Controller receives a poisoned request from the link. [ii] The Controller has sent a Poisoned Completion downstream to the link This bit remains 0 when the Parity Error Response enable bit is 0. This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
23-21	R5	R	0h	Reserved
20	CL	R	1h	Indicates the presence of PCI Extended Capabilities registers. This bit is hardwired to 1.
19	IS	R	0h	This bit is valid only when the Controller is configured to support legacy interrupts. Indicates that the Controller has a pending interrupt, that is, the Controller has sent an Assert_INTx message but has not transmitted a corresponding Deassert_INTx message.
18-16	R4	R	0h	Reserved
15-11	R3	R	0h	Reserved
10	IMD	R/W	0h	Enables or disables the transmission of INTx Assert and De-assert messages from the Controller. The setting of this bit has no effect on the operation of the Controller in the RC mode.
9	R2	R	0h	Reserved
8	SE	R/W	0h	Enables the reporting of fatal and non-fatal errors detected by the Controller to the Root Complex.
7	R1	R	0h	Reserved
6	PERE	R/W	0h	When this bit is 1, the Controller sets the Master Data Parity Error status bit when it detects the following error conditions: [i] The Controller receives a poisoned completion from the link in response to a request. [ii] The Controller sends out a poisoned write request on the link [this may be because an underflow occurred during the packet transfer at the host interface of the Controller.]. When this bit is 0, the Master Data Parity Error status bit is never set.
5-3	R0	R	0h	Reserved
2	BE	R/W	0h	For a Function with a Type 1 Configurations Space header[Controller in RP Mode], this bit controls forwarding of Memory or I/O Requests by a Port in the Upstream direction. Note: The Controller does not generate any response based on this bit. Client application logic must use this bit and respond to requests appropriately: - When this bit is '1', Client logic can process the Memory and IO Requests received from PCIe Link normally. - When this bit is '0', Client logic must handle Memory and IO Requests received from PCIe Link as Unsupported Requests.
1	MSE	R/W	0h	For a Function with a Type 1 Configuration Space header[Controller in RP Mode], this bit controls the response to Memory Space accesses received on its Primary Side. Note: The Controller does not generate any response based on this bit. - Client must check for this bit to be '1' before initiating any Memory requests on the pcie_master_AXI interface.
0	ISE	R/W	0h	For a Function with a Type 1 Configuration Space header [Controller in RP Mode] , this bit controls the response to I/O Space accesses received on its Primary Side. Note: The Controller does not generate any response based on this bit. - Client must check for this bit to be '1' before initiating any IO requests on the pcie_master_AXI interface.

3.5.3.3 PCIE_CORE_RP_I_REVISION_ID_CLASS_CODE Register (Offset = 8h) [reset = 0h]

PCIE_CORE_RP_I_REVISION_ID_CLASS_CODE is shown in Figure 12-1491 and described in Table 12-2924.

Return to the Summary Table.

This register contains the Revision ID and Class Code associated with the device
incorporating the PCIe Controller.

Table 12-2923 PCIE_CORE_RP_I_REVISION_ID_CLASS_CODE Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0008h

Figure 12-1491 PCIE_CORE_RP_I_REVISION_ID_CLASS_CODE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC								SCC								PIB								RID
R-0h								R-0h								R-0h								R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-2924 PCIE_CORE_RP_I_REVISION_ID_CLASS_CODE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	CC	R	0h	Identifies the function of the device. On power-up, the Controller sets it to the value defined in the RTL file reg_defaults.h. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
23-16	SCC	R	0h	Identifies a sub-category within the selected function. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
15-8	PIB	R	0h	Identifies the register set layout of the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
7-0	RID	R	0h	Assigned by the manufacturer of the device to identify the revision number of the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

3.5.3.4 PCIE_CORE_RP_I_BIST_HEADER_LATENCY_CACHE_LINE Register (Offset = Ch) [reset = 00010000h]

PCIE_CORE_RP_I_BIST_HEADER_LATENCY_CACHE_LINE is shown in Figure 12-1492 and described in Table 12-2926.

Return to the Summary Table.

This location contains the BIST, header-type, Latency Timer and Cache Line Size
Registers.

Table 12-2925 PCIE_CORE_RP_I_BIST_HEADER_LATENCY_CACHE_LINE Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 000Ch

Figure 12-1492 PCIE_CORE_RP_I_BIST_HEADER_LATENCY_CACHE_LINE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR								DT	HT
R-0h								R-0h	R-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LT								CLS
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-2926 PCIE_CORE_RP_I_BIST_HEADER_LATENCY_CACHE_LINE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	BR	R	0h	BIST control register. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
23	DT	R	0h	Identifies whether the device supports a single Function or multiple Functions. Hardwired to zero
22-16	HT	R	1h	Identifies format of header. This field is hardwired to 1.
15-8	LT	R	0h	This is an unused field and is hardwired to 0.
7-0	CLS	R/W	0h	Cache Line Size Register defined in PCI Specifications 3.0. This field can be read or written, both from the link and from the local management bus, but its value is not used.

3.5.3.5 PCIE_CORE_RP_I_RC_BAR_0 Register (Offset = 10h) [reset = 0h]

PCIE_CORE_RP_I_RC_BAR_0 is shown in Figure 12-1493 and described in Table 12-2928.

Return to the Summary Table.

This is the Base Address Register 0 in the Type-1 Config Space. It can be configured
as a 32-bit memory BAR, a 32-bit IO BAR, or can be paired with RC BAR 1 to form a 64-bit memory BAR.
The parameters of this BAR are configured in the local management register Root Complex BAR Configuration Register.

Table 12-2927 PCIE_CORE_RP_I_RC_BAR_0 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0010h

Figure 12-1493 PCIE_CORE_RP_I_RC_BAR_0 Register

31	30	29	28	27	26	25	24
BAMRW
R/W-0h

23	22	21	20	19	18	17	16
BAMRW		BAMR0
R/W-0h		R-0h

15	14	13	12	11	10	9	8
BAMR0
R-0h

7	6	5	4	3	2	1	0
BAMR0				P0	S0	R7	MSI0
R-0h				R-0h	R-0h	R-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-2928 PCIE_CORE_RP_I_RC_BAR_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-22	BAMRW	R/W	0h	This field defines the base address of the memory address range. The number of implemented bits in this field determines the BAR aperture configured in Root Complex BAR Configuration Register. All other bits are not writeable, and are read as 0's.
21-4	BAMR0	R	0h	This field defines the base address of the memory address range. The number of implemented bits in this field determines the BAR aperture configured in Root Complex BAR Configuration Register. All other bits are not writeable, and are read as 0's.
3	P0	R	0h	For memory BAR: This bit reads as 1 when BAR 0 is configured as a prefetchable BAR, and as 0 when configured as a non-prefetchable BAR. For IO BAR: This is bit 3 of the base address. The value read in this field is determined by the setting of Root Complex BAR Configuration Register.
2	S0	R	0h	For memory BAR:This bit reads as 0 when BAR 0 is configured as a 32-bit BAR, and as 1 when configured as a 64-bit BAR. For IO BAR: This is bit 3 of the base address. The value read in this field is determined by the setting of Root Complex BAR Configuration Register.
1	R7	R	0h	This bit is hardwired to 0 for both memory and I/O BARs.
0	MSI0	R	0h	Specifies whether this BAR defines a memory address range or an I/O address range [0 = memory, 1 = I/O]. The value read in this field is determined by the setting of Root Complex BAR Configuration Register.

3.5.3.6 PCIE_CORE_RP_I_RC_BAR_1 Register (Offset = 14h) [reset = 0h]

PCIE_CORE_RP_I_RC_BAR_1 is shown in Figure 12-1494 and described in Table 12-2930.

Return to the Summary Table.

This is the Base Address Register 1 in the Type-1 Config Space. It can be configured as a
32-bit memory BAR, a 32-bit IO BAR, or can be paired with RC BAR 0 to form a 64-bit memory BAR.
The parameters of this BAR are configured in the local management register Root Complex BAR Configuration Register.

Table 12-2929 PCIE_CORE_RP_I_RC_BAR_1 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0014h

Figure 12-1494 PCIE_CORE_RP_I_RC_BAR_1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R7
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-2930 PCIE_CORE_RP_I_RC_BAR_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	R7	R	0h	This field is reserved at power-on. This can be changed using BAR configuration regsiter in LM space.

3.5.3.7 PCIE_CORE_RP_I_PCIE_BUS_NUMBERS Register (Offset = 18h) [reset = 0h]

PCIE_CORE_RP_I_PCIE_BUS_NUMBERS is shown in Figure 12-1495 and described in Table 12-2932.

Return to the Summary Table.

This location contains the 8-bit fields: Primary Bus Number, Secondary Bus Number,Subordinate Bus Number, Secondary Latency
Timer.

Table 12-2931 PCIE_CORE_RP_I_PCIE_BUS_NUMBERS Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0018h

Figure 12-1495 PCIE_CORE_RP_I_PCIE_BUS_NUMBERS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SLTN								SUBN								SBN								PBN
R-0h								R/W-0h								R/W-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-2932 PCIE_CORE_RP_I_PCIE_BUS_NUMBERS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	SLTN	R	0h	This field is not implemented.
23-16	SUBN	R/W	0h	This field can be read and written from the local management bus, but its value is not used within the Controller.
15-8	SBN	R/W	0h	This field can be read and written from the local management bus, but its value is not used within the Controller.
7-0	PBN	R/W	0h	This field can be read and written from the local management bus, but its value is not used within the Controller.

3.5.3.8 PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT Register (Offset = 1Ch) [reset = 0h]

PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT is shown in Figure 12-1496 and described in Table 12-2934.

Return to the Summary Table.

This location contains the 8-bit IO Base Register, the 8-bit IO Limit Register and the 16-bit Secondary Status Registers.

Table 12-2933 PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 001Ch

Figure 12-1496 PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT Register

31	30	29	28	27	26	25	24
DPE	RSE	RMA	RTA	STA	R4		MPE
R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R-0h		R/W1C-0h

23	22	21	20	19	18	17	16
R3
R-0h

15	14	13	12	11	10	9	8
ILR				R2			IOBS2
R-0h				R-0h			R-0h

7	6	5	4	3	2	1	0
IBR				R1			IOBS1
R-0h				R-0h			R-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-2934 PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DPE	R/W1C	0h	The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
30	RSE	R/W1C	0h	The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
29	RMA	R/W1C	0h	The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
28	RTA	R/W1C	0h	The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
27	STA	R/W1C	0h	The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
26-25	R4	R	0h	Reserved
24	MPE	R/W1C	0h	The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. Note that this bit can be set only when the Parity Error Response Enable bit is set in the Bridge Control Register
23-16	R3	R	0h	Reserved
15-12	ILR	R	0h	This field can be read and written from the local management bus if IO BAR is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.
11-9	R2	R	0h	Reserved
8	IOBS2	R	0h	value set in Type1 cfg IO bar size[bit 20 of RC BAR CONFIG register].If type1 cfg IObar enable bit[bit 19 in RC BAR CONFIG register] is not set, then this field will be hard coded to 0.
7-4	IBR	R	0h	This field can be read and written from the local management bus if IO BAR is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.
3-1	R1	R	0h	Reserved
0	IOBS1	R	0h	value set in Type1 cfg IO bar size[bit 20 of RC BAR CONFIG register]. If type1 cfg IObar enable bit[bit 19 in RC BAR CONFIG register] is not set, then this field will be hard coded to 0.

3.5.3.9 PCIE_CORE_RP_I_PCIE_MEM_BASE_LIMIT Register (Offset = 20h) [reset = 0h]

PCIE_CORE_RP_I_PCIE_MEM_BASE_LIMIT is shown in Figure 12-1497 and described in Table 12-2936.

Return to the Summary Table.

This location contains the 16-bit Memory Base Register and the 16-bit Memory Limit Register

Table 12-2935 PCIE_CORE_RP_I_PCIE_MEM_BASE_LIMIT Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0020h

Figure 12-1497 PCIE_CORE_RP_I_PCIE_MEM_BASE_LIMIT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MLR												R2				MBR												R1
R/W-0h												R-0h				R/W-0h												R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-2936 PCIE_CORE_RP_I_PCIE_MEM_BASE_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	MLR	R/W	0h	This field can be read and written from the local management APB bus, but its value is not used within the Controller.
19-16	R2	R	0h	Reserved
15-4	MBR	R/W	0h	This field can be read and written from the local management APB bus, but its value is not used within the Controller.
3-0	R1	R	0h	Reserved

3.5.3.10 PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_LIMIT Register (Offset = 24h) [reset = 0h]

PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_LIMIT is shown in Figure 12-1498 and described in Table 12-2938.

Return to the Summary Table.

This location contains the Prefetchable Memory Base Register and the Prefetchable Memory Limit
Register. This register is enabled by programming the Root Complex BAR configuration register in
the Local Management space

Table 12-2937 PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_LIMIT Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0024h

Figure 12-1498 PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_LIMIT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PMLR																PMBR
R-0h																R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-2938 PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PMLR	R	0h	This field can be read and written from the local management APB bus if prefetchable memory is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.
15-0	PMBR	R	0h	This field can be read and written from the local management APB bus if prefetchable memory is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.

3.5.3.11 PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_UPPER Register (Offset = 28h) [reset = 0h]

PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_UPPER is shown in Figure 12-1499 and described in Table 12-2940.

Return to the Summary Table.

This location contains the upper 32 bits of the Prefetchable Base Register. This register is
enabled by programming the Root Complex BAR configuration register in the Local Management space.

Table 12-2939 PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_UPPER Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0028h

Figure 12-1499 PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_UPPER Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PBRU
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-2940 PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_UPPER Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PBRU	R	0h	This field can be read and written from the local management APB bus if 64bit prefetchable memory is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.

3.5.3.12 PCIE_CORE_RP_I_PCIE_PREFETCH_LIMIT_UPPER Register (Offset = 2Ch) [reset = 0h]

PCIE_CORE_RP_I_PCIE_PREFETCH_LIMIT_UPPER is shown in Figure 12-1500 and described in Table 12-2942.

Return to the Summary Table.

This location contains the upper 32 bits of the Prefetchable Limit Register. This register
is enabled by programming the Root Complex BAR configuration register in the Local Management space.

Table 12-2941 PCIE_CORE_RP_I_PCIE_PREFETCH_LIMIT_UPPER Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 002Ch

Figure 12-1500 PCIE_CORE_RP_I_PCIE_PREFETCH_LIMIT_UPPER Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PLRU
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-2942 PCIE_CORE_RP_I_PCIE_PREFETCH_LIMIT_UPPER Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PLRU	R	0h	This field can be read and written from the local management APB bus if 64bit prefetchable memory is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.

3.5.3.13 PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT_UPPER Register (Offset = 30h) [reset = 0h]

PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT_UPPER is shown in Figure 12-1501 and described in Table 12-2944.

Return to the Summary Table.

This location contains the upper 16 bits of the IO Base and IO Limit Registers

Table 12-2943 PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT_UPPER Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0030h

Figure 12-1501 PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT_UPPER Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ILR																IBRU
R-0h																R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-2944 PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT_UPPER Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ILR	R	0h	This field can be read and written from the local management bus if 32bit IO BAR is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.
15-0	IBRU	R	0h	This field can be read and written from the local management bus if 32bit IO BAR is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.

3.5.3.14 PCIE_CORE_RP_I_CAPABILITIES_POINTER Register (Offset = 34h) [reset = 80h]

PCIE_CORE_RP_I_CAPABILITIES_POINTER is shown in Figure 12-1502 and described in Table 12-2946.

Return to the Summary Table.

This location contains the pointer to the first PCI Capabilities Structure.

Table 12-2945 PCIE_CORE_RP_I_CAPABILITIES_POINTER Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0034h

Figure 12-1502 PCIE_CORE_RP_I_CAPABILITIES_POINTER Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R15																								CP
R-0h																								R-80h

LEGEND: R = Read Only; -n = value after reset

Table 12-2946 PCIE_CORE_RP_I_CAPABILITIES_POINTER Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	R15	R	0h	Reserved
7-0	CP	R	80h	Contains pointer to the first PCI Capability Structure. This field is set by default to the value defined in the RTL file reg_defaults.h. It can be re-written independently for every Function from the local management APB bus.

3.5.3.15 PCIE_CORE_RP_RSVD_0E Register (Offset = 38h) [reset = 0h]

PCIE_CORE_RP_RSVD_0E is shown in Figure 12-1503 and described in Table 12-2948.

Return to the Summary Table.

Reserved

Table 12-2947 PCIE_CORE_RP_RSVD_0E Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0038h

Figure 12-1503 PCIE_CORE_RP_RSVD_0E Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RSVD
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-2948 PCIE_CORE_RP_RSVD_0E Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RSVD	R	0h	Reserved

3.5.3.16 PCIE_CORE_RP_I_INTRPT_LINE_INTRPT_PIN Register (Offset = 3Ch) [reset = 1FFh]

PCIE_CORE_RP_I_INTRPT_LINE_INTRPT_PIN is shown in Figure 12-1504 and described in Table 12-2950.

Return to the Summary Table.

This location contains the Interrupt Line Register, the Interrupt Pin Register,
and the Bridge Control Register

Table 12-2949 PCIE_CORE_RP_I_INTRPT_LINE_INTRPT_PIN Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 003Ch

Figure 12-1504 PCIE_CORE_RP_I_INTRPT_LINE_INTRPT_PIN Register

31	30	29	28	27	26	25	24
R23
R-0h

23	22	21	20	19	18	17	16
R23	BCRSBR	R21	VGA16D	VGAE	ISAE	BCSE	PERE
R-0h	R/W-0h	R-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
R5					IPR
R-0h					R-1h

7	6	5	4	3	2	1	0
ILR
R/W-FFh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-2950 PCIE_CORE_RP_I_INTRPT_LINE_INTRPT_PIN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	R23	R	0h	Reserved
22	BCRSBR	R/W	0h	This field can be read and written from the local management APB bus. When set, it initiates a hot reset on the link.
21	R21	R	0h	Reserved
20	VGA16D	R/W	0h	This field can be read and written from the local management APB bus, but its value is not used within the Controller.
19	VGAE	R/W	0h	This field can be read and written from the local management APB bus, but its value is not used within the Controller.
18	ISAE	R/W	0h	This field can be read and written from the local management APB bus, but its value is not used within the Controller.
17	BCSE	R/W	0h	This field can be read and written from the local management APB bus, but its value is not used within the Controller.
16	PERE	R/W	0h	This field can be read and written from the local management APB bus. It is used only to enable the Master Data Parity Error bit in the Secondary Status Register.
15-11	R5	R	0h	Reserved
10-8	IPR	R	1h	Identifies the interrupt input [A, B, C, D] to which this Functions interrupt output is connected to [01 = INTA, 02 = INTB, 03 = INTC, 04 = INTD]. The assignment of interrupt inputs to Functions is fixed when the Controller is configured. This field can be re-written independently for each Function from the local management bus. Default values - PF 0: 01 [INTA], PF 1: 02 [INTB].
7-0	ILR	R/W	FFh	This field can be read and written from the local management bus, but its value is not used within the Controller.The given reset value is for PF0.

3.5.3.17 PCIE_CORE_RP_I_PWR_MGMT_CAP Register (Offset = 80h) [reset = 5A039001h]

PCIE_CORE_RP_I_PWR_MGMT_CAP is shown in Figure 12-1505 and described in Table 12-2952.

Return to the Summary Table.

This location contains the Power Management Capabilities Register, its Capability ID,
and a pointer to the next capability. In the RC mode, the settings of the fields of this
register have no effect on the operation of the Controller

Table 12-2951 PCIE_CORE_RP_I_PWR_MGMT_CAP Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0080h

Figure 12-1505 PCIE_CORE_RP_I_PWR_MGMT_CAP Register

31	30	29	28	27	26	25	24
PSDCS	PSDHS	PSD2S	PSD1S	PSD0S	D2S	D1S	MCRAPS
R-0h	R-1h	R-0h	R-1h	R-1h	R-0h	R-1h	R-0h

23	22	21	20	19	18	17	16
MCRAPS		DSI	R0	PC	VID
R-0h		R-0h	R-0h	R-0h	R-3h

15	14	13	12	11	10	9	8
CP
R-90h

7	6	5	4	3	2	1	0
CID
R-1h

LEGEND: R = Read Only; -n = value after reset

Table 12-2952 PCIE_CORE_RP_I_PWR_MGMT_CAP Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PSDCS	R	0h	Indicates whether the Function is capable of sending PME messages when in the D3cold state. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
30	PSDHS	R	1h	Indicates whether the Function is capable of sending PME messages when in the D3hot state. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
29	PSD2S	R	0h	Indicates whether the Function is capable of sending PME messages when in the D2 state. This bit is hardwired to 0 because D2 state is not supported.
28	PSD1S	R	1h	Indicates whether the Function is capable of sending PME messages when in the D1 state. This bit is set to 1 by default, but can be modified from the local management bus by writing into Function 0. All other Functions assume the value set in Function 0s Power Management Capabilities Register.
27	PSD0S	R	1h	Indicates whether the Function is capable of sending PME messages when in the D0 state. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
26	D2S	R	0h	Set if the Function supports the D2 power state. Currently hardwired to 0.
25	D1S	R	1h	Set if the Function supports the D1 power state. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
24-22	MCRAPS	R	0h	Specifies the maximum current drawn by the device from the aux power source in the D3cold state. This field is not implemented in devices not supporting PME notification when in the D3cold state, and is therefore hardwired to 0.
21	DSI	R	0h	This bit, when set, indicates that the device requires additional configuration steps beyond setting up its PCI configuration space, to bring it to the D0 active state from the D0 uninitialized state. This bit is hardwired to 0.
20	R0	R	0h	Reserved
19	PC	R	0h	Not applicable to PCI Express. This bit is hardwired to 0.
18-16	VID	R	3h	Indicates the version of the PCI Bus Power Management Specifications that the Function implements. This field is set by default to 011 [Version 1.2]. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
15-8	CP	R	90h	Contains pointer to the next PCI Capability Structure. The Controller sets it to the value defined in the RTL file reg_defaults.h. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
7-0	CID	R	1h	Identifies that the capability structure is for Power Management. This field is set by default to 01 hex. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

3.5.3.18 PCIE_CORE_RP_I_PWR_MGMT_CTRL_STAT_REP Register (Offset = 84h) [reset = 8h]

PCIE_CORE_RP_I_PWR_MGMT_CTRL_STAT_REP is shown in Figure 12-1506 and described in Table 12-2954.

Return to the Summary Table.

This location contains the Power Management Control/Status and Data Registers.

Table 12-2953 PCIE_CORE_RP_I_PWR_MGMT_CTRL_STAT_REP Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0084h

Figure 12-1506 PCIE_CORE_RP_I_PWR_MGMT_CTRL_STAT_REP Register

31	30	29	28	27	26	25	24
DR
R-0h

23	22	21	20	19	18	17	16
R1
R-0h

15	14	13	12	11	10	9	8
PMES	R2						PE
R/W1C-0h	R-0h						R/W-0h

7	6	5	4	3	2	1	0
R3				NSR	R4	PS
R-0h				R-1h	R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-2954 PCIE_CORE_RP_I_PWR_MGMT_CTRL_STAT_REP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	DR	R	0h	This optional register is not implemented in the PCIe Controller. This field is hardwired to 0.
23-16	R1	R	0h	Reserved
15	PMES	R/W1C	0h	This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write..
14-9	R2	R	0h	Reserved
8	PE	R/W	0h	This bit can be set or cleared from the local management APB bus, by writing a 1 or 0, respectively.
7-4	R3	R	0h	Reserved
3	NSR	R	1h	This bit is set to 1 by default. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
2	R4	R	0h	Reserved
1-0	PS	R/W	0h	This field can also be read or written from the local management APBbus.

3.5.3.19 PCIE_CORE_RP_I_MSI_CTRL_REG Register (Offset = 90h) [reset = 0180B005h]

PCIE_CORE_RP_I_MSI_CTRL_REG is shown in Figure 12-1507 and described in Table 12-2956.

Return to the Summary Table.

This register is used only when the Controller is configured to support Message Signaled
Interrupts (MSIs). In addition to the MSI control bits, this location also contains the
Capability ID for MSI and the pointer to the next PCI Capability Structure.

Table 12-2955 PCIE_CORE_RP_I_MSI_CTRL_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0090h

Figure 12-1507 PCIE_CORE_RP_I_MSI_CTRL_REG Register

31	30	29	28	27	26	25	24
R0							MC
R-0h							R-1h

23	22	21	20	19	18	17	16
BAC64	MME			MMC			ME
R-1h	R/W-0h			R-0h			R/W-0h

15	14	13	12	11	10	9	8
CP1
R-B0h

7	6	5	4	3	2	1	0
CID1
R-5h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-2956 PCIE_CORE_RP_I_MSI_CTRL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	R0	R	0h	Reserved
24	MC	R	1h	can be modified using localmanagement interface
23	BAC64	R	1h	Set to 1 to indicate that the device is capable of generating 64-bit addresses for MSI messages.Can be modified using local management interface
22-20	MME	R/W	0h	Encodes the number of distinct messages that the Controller is programmed to generate for this Function [000 = 1, 001 = 2, 010 = 4, 011 = 8, 100 = 16, 101 = 32]. This setting must be based on the number of interrupt inputs of the Controller that are actually used by this Function. This field can be written from the local management bus.
19-17	MMC	R	0h	Encodes the number of distinct messages that the Controller is capable of generating for this Function [000 = 1, 001 = 2, 010 = 4, 011 = 8, 100 = 16, 101 = 32]. Thus, this field defines the number of the interrupt vectors for this Function. The Controller allows up to 32 distinct messages, but the setting of this field must be based on the number of interrupt inputs of the Controller that are actually used by the client. For example, if the client logic uses 8 of the 32 distinct MSI interrupt inputs of the Controller for this Function, then the value of this field must be set to 011. This field can be written from the local management bus. Please see the define den_db_Fx_MSI_MULTIPLE_MSG_CAPABLE values [where x is the function number] for default values of each function in the reg_defaults.v files.
16	ME	R/W	0h	Set by the configuration program to enable the MSI feature. This field can also be written from the local management bus.
15-8	CP1	R	B0h	Pointer to the next PCI Capability Structure. This can be modified from the local management bus. This field can be written from the local management bus.
7-0	CID1	R	5h	Specifies that the capability structure is for MSI. Hardwired to 05 hex.

3.5.3.20 PCIE_CORE_RP_I_MSI_MSG_LOW_ADDR Register (Offset = 94h) [reset = 0h]

PCIE_CORE_RP_I_MSI_MSG_LOW_ADDR is shown in Figure 12-1508 and described in Table 12-2958.

Return to the Summary Table.

This register contains the first 32 bits of the address to be used in the MSI messages
generated by the Controller for this Function. This address is taken as a 32-bit address if the value
programmed in the MSI Message High Address Register is 0. Otherwise, this address is taken as
the least significant 32 bits of the 64-bit address sent in MSI messages.

Table 12-2957 PCIE_CORE_RP_I_MSI_MSG_LOW_ADDR Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0094h

Figure 12-1508 PCIE_CORE_RP_I_MSI_MSG_LOW_ADDR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MAL																														R1
R/W-0h																														R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-2958 PCIE_CORE_RP_I_MSI_MSG_LOW_ADDR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	MAL	R/W	0h	Lower bits of the address to be used in MSI messages. This field can also be written from the local management bus.
1-0	R1	R	0h	The two lower bits of the address are hardwired to 0 to align the address on a double-word boundary.

3.5.3.21 PCIE_CORE_RP_I_MSI_MSG_HI_ADDR Register (Offset = 98h) [reset = 0h]

PCIE_CORE_RP_I_MSI_MSG_HI_ADDR is shown in Figure 12-1509 and described in Table 12-2960.

Return to the Summary Table.

This register contains the most significant 32 bits of the 64-bit address sent by the
Controller in MSI messages. A value of all zeroes in this register is taken to mean that the Controller
should use 32-bit addresses in the messages.

Table 12-2959 PCIE_CORE_RP_I_MSI_MSG_HI_ADDR Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0098h

Figure 12-1509 PCIE_CORE_RP_I_MSI_MSG_HI_ADDR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MAH
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-2960 PCIE_CORE_RP_I_MSI_MSG_HI_ADDR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	MAH	R/W	0h	Contains bits 63:32 of the 64-bit address to be used in MSI Messages. A value of 0 specifies that 32-bit addresses are to be used in the messages. This field can also be written from the local management bus.

3.5.3.22 PCIE_CORE_RP_I_MSI_MSG_DATA Register (Offset = 9Ch) [reset = 0h]

PCIE_CORE_RP_I_MSI_MSG_DATA is shown in Figure 12-1510 and described in Table 12-2962.

Return to the Summary Table.

This register contains the write data to be used in the MSI messages to be generated for
the associated PCI Function. When the number of distinct messages programmed in the MSI Control
Register is 1, the 32-bit value from this register is used as the data value in the MSI packets
generated by the Controller for this Function. If the number of distinct messages is more than 1, the
least significant bits of the programmed value are replaced with the encoded interrupt vector
[31:0] of the specific message to generate the write data value for the message.

Table 12-2961 PCIE_CORE_RP_I_MSI_MSG_DATA Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 009Ch

Figure 12-1510 PCIE_CORE_RP_I_MSI_MSG_DATA Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R2																MD
R-0h																R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-2962 PCIE_CORE_RP_I_MSI_MSG_DATA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	R2	R	0h	Hardwired to 0
15-0	MD	R/W	0h	Message data to be used for this Function. This field can also be written from the local management bus.

3.5.3.23 PCIE_CORE_RP_I_MSI_MASK Register (Offset = A0h) [reset = X]

PCIE_CORE_RP_I_MSI_MASK is shown in Figure 12-1511 and described in Table 12-2964.

Return to the Summary Table.

This register contains the MSI mask bits, one for each of the interrupt levels.

Table 12-2963 PCIE_CORE_RP_I_MSI_MASK Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00A0h

Figure 12-1511 PCIE_CORE_RP_I_MSI_MASK Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															MM
R/W-X															R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-2964 PCIE_CORE_RP_I_MSI_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R/W	X
0	MM	R/W	0h	Mask bits for MSI interrupts. The Multiple Message Capable field of the MSI Control Register specifies the number of distinct interrupts for the Function, which determines the number of valid mask bits.

3.5.3.24 PCIE_CORE_RP_I_MSI_PENDING_BITS Register (Offset = A4h) [reset = X]

PCIE_CORE_RP_I_MSI_PENDING_BITS is shown in Figure 12-1512 and described in Table 12-2966.

Return to the Summary Table.

This register contains the MSI pending interrupt bits, one for each of the interrupt
levels.

Table 12-2965 PCIE_CORE_RP_I_MSI_PENDING_BITS Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00A4h

Figure 12-1512 PCIE_CORE_RP_I_MSI_PENDING_BITS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															MP
R-X															R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-2966 PCIE_CORE_RP_I_MSI_PENDING_BITS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	X
0	MP	R	0h	Pending bits for MSI interrupts. This field can be written from the APB interface to refelct the current pending status.

3.5.3.25 PCIE_CORE_RP_I_MSIX_CTRL Register (Offset = B0h) [reset = C011h]

PCIE_CORE_RP_I_MSIX_CTRL is shown in Figure 12-1513 and described in Table 12-2968.

Return to the Summary Table.

This register contains the MSI-X configuration bits, the Capability ID for MSI-X and the
pointer to the next PCI Capability Structure.

Table 12-2967 PCIE_CORE_RP_I_MSIX_CTRL Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00B0h

Figure 12-1513 PCIE_CORE_RP_I_MSIX_CTRL Register

31	30	29	28	27	26	25	24
MSIXE	FM	R0			MSIXTS
R/W-0h	R/W-0h	R-0h			R-0h

23	22	21	20	19	18	17	16
MSIXTS
R-0h

15	14	13	12	11	10	9	8
CP
R-C0h

7	6	5	4	3	2	1	0
CID
R-11h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-2968 PCIE_CORE_RP_I_MSIX_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	MSIXE	R/W	0h	Set by the configuration program to enable the MSI-X feature. This field can also be written from the local management bus.
30	FM	R/W	0h	This bit serves as a global mask to all the interrupt conditions associated with this Function. When this bit is set, the Controller will not send out MSI-X messages from this Function. This field can also be written from the local management bus.
29-27	R0	R	0h	Reserved
26-16	MSIXTS	R	0h	Specifies the size of the MSI-X Table, that is, the number of interrupt vectors defined for the Function. The programmed value is 1 minus the size of the table [that is, this field is set to 0 if the table size is 1.]. It can be re-written independently for each Function from the local management bus. Please see the define den_db_Fx_MSIX_TABLE_SIZE values [where x is the function number] for default values of each function in the reg_defaults.v files.
15-8	CP	R	C0h	Contains pointer to the next PCI Capability Structure. This is set to point to the PCI Express Capability Structure at 30 hex. This can be rewritten independently for each Function from the local management bus.
7-0	CID	R	11h	Identifies that the capability structure is for MSI-X. This field is set by default to 11 hex. It can be rewritten independently for each Function from the local management bus.

3.5.3.26 PCIE_CORE_RP_I_MSIX_TBL_OFFSET Register (Offset = B4h) [reset = 0h]

PCIE_CORE_RP_I_MSIX_TBL_OFFSET is shown in Figure 12-1514 and described in Table 12-2970.

Return to the Summary Table.

This register is used to specify the location of the MSI-X Table in memory. All the 32
bits of this register can be re-written independently for each Function from the local
management bus.

Table 12-2969 PCIE_CORE_RP_I_MSIX_TBL_OFFSET Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00B4h

Figure 12-1514 PCIE_CORE_RP_I_MSIX_TBL_OFFSET Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TO
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TO													BARI
R-0h													R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-2970 PCIE_CORE_RP_I_MSIX_TBL_OFFSET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	TO	R	0h	Offset of the memory address where the MSI-X Table is located, relative to the selected BAR. The three least significant bits of the address are omitted, as the addresses are QWORD aligned. Please see the define den_db_Fx_MSIX_TABLE_OFFSET values [where x is the function number] for default values of each function in the reg_defaults.v files.
2-0	BARI	R	0h	Identifies the BAR corresponding to the memory address range where the MSI-X Table is located [000 = BAR 0, 001 = BAR 1, ... , 101 = BAR 5]. Please see the define den_db_Fx_MSIX_TABLE_BIR values [where x is the function number] for default values of each function in the reg_defaults.v files.

3.5.3.27 PCIE_CORE_RP_I_MSIX_PENDING_INTRPT Register (Offset = B8h) [reset = 8h]

PCIE_CORE_RP_I_MSIX_PENDING_INTRPT is shown in Figure 12-1515 and described in Table 12-2972.

Return to the Summary Table.

This register is used to specify the location of the MSI-X Pending Bit Array (PBA). The
PBA is a structure in memory containing the pending interrupt bits. All the 32 bits of this
register can be rewritten independently for each Function from the local management bus.

Table 12-2971 PCIE_CORE_RP_I_MSIX_PENDING_INTRPT Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00B8h

Figure 12-1515 PCIE_CORE_RP_I_MSIX_PENDING_INTRPT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PBAO
R-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PBAO													BARI1
R-1h													R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-2972 PCIE_CORE_RP_I_MSIX_PENDING_INTRPT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	PBAO	R	1h	Offset of the memory address where the PBA is located, relative to the selected BAR. The three least significant bits of the address are omitted, as the addresses are QWORD aligned. Please see the define den_db_Fx_MSIX_PBA_OFFSET values [where x is the function number] for default values of each function in the reg_defaults.v files.
2-0	BARI1	R	0h	Identifies the BAR corresponding to the memory address range where the PBA Structure is located [000 = BAR 0, 001 = BAR 1, ... , 101 = BAR 5]. The value programmed must be the same as the BAR Indicator configured in the MSI-X Table Offset Register.Identifies the BAR corresponding to the memory address range where the PBA Structure is located [000 = BAR 0, 001 = BAR 1, ... , 101 = BAR 5]. The value programmed must be the same as the BAR Indicator configured in the MSI-X Table Offset Register. Please see the define den_db_Fx_MSIX_PBA_BIR values [where x is the function number] for default values of each function in the reg_defaults.v files.

3.5.3.28 PCIE_CORE_RP_I_PCIE_CAP_LIST Register (Offset = C0h) [reset = 01420010h]

PCIE_CORE_RP_I_PCIE_CAP_LIST is shown in Figure 12-1516 and described in Table 12-2974.

Return to the Summary Table.

This location identifies the PCI Express device type and its capabilities. It also
contains the Capability ID for the PCI Express Structure and the pointer to the next capability
structure.

Table 12-2973 PCIE_CORE_RP_I_PCIE_CAP_LIST Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00C0h

Figure 12-1516 PCIE_CORE_RP_I_PCIE_CAP_LIST Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
R0	TRS	IMN					SI	DT				PCV
R-0h	R-0h	R-0h					R-1h	R-4h				R-2h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NCP								CID
R-0h								R-10h

LEGEND: R = Read Only; -n = value after reset

Table 12-2974 PCIE_CORE_RP_I_PCIE_CAP_LIST Register Field Descriptions

Bit	Field	Type	Reset	Description
31	R0	R	0h	Reserved
30	TRS	R	0h	When set to 1, this bit indicates that the device supports routing of Trusted Configuration Requests. Not valid for Endpoints. Hardwired to 0.
29-25	IMN	R	0h	Identifies the MSI or MSI-X interrupt vector for the interrupt message generated corresponding to the status bits in the Slot Status Register, Root Status Register, or this capability structure. This field must be defined based on the chosen interrupt mode - MSI or MSI-X. This field is hardwired to 0.
24	SI	R	1h	When Set, this bit indicates that the Link associated with this Port is connected to a slot
23-20	DT	R	4h	Indicates the type of device implementing this Function. This field is hardwired to 4 in the RP mode.
19-16	PCV	R	2h	Identifies the version number of the capability structure. This field is set to 2 by default to indicate that the Controller is compatible to PCI Express Base Specification Revision 3.0. Can be modified using local management interface after asserting input signal MGMT_TYPE1_CONFIG_REG_ACCESS high.
15-8	NCP	R	0h	Points to the next PCI capability structure. Set to 0 because this is the last capability structure.
7-0	CID	R	10h	Specifies Capability ID assigned by PCI SIG for this structure. This field is hardwired to 10 hex.

3.5.3.29 PCIE_CORE_RP_I_PCIE_CAP Register (Offset = C4h) [reset = 8001h]

PCIE_CORE_RP_I_PCIE_CAP is shown in Figure 12-1517 and described in Table 12-2976.

Return to the Summary Table.

This register advertises the capabilities of the PCI Express device.

Table 12-2975 PCIE_CORE_RP_I_PCIE_CAP Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00C4h

Figure 12-1517 PCIE_CORE_RP_I_PCIE_CAP Register

31	30	29	28	27	26	25	24
R5			FLRC	CPLS		CSP
R-0h			R-0h	R-0h		R-0h

23	22	21	20	19	18	17	16
CSP						R4
R-0h						R-0h

15	14	13	12	11	10	9	8
RER	R3			AL1L			AL0L
R-1h	R-0h			R-0h			R-0h

7	6	5	4	3	2	1	0
AL0L		ETFS	PFS		MP
R-0h		R-0h	R-0h		R-1h

LEGEND: R = Read Only; -n = value after reset

Table 12-2976 PCIE_CORE_RP_I_PCIE_CAP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	R5	R	0h	Reserved
28	FLRC	R	0h	A value of 1b indicates the Function supports the optional Function Level Reset mechanism
27-26	CPLS	R	0h	Specifies the scale used by Slot Power Limit Value. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. .
25-18	CSP	R	0h	Specifies upper limit on power supplied by slot. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. .
17-16	R4	R	0h	Reserved
15	RER	R	1h	Enables role-based errer reporting. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
14-12	R3	R	0h	Reserved
11-9	AL1L	R	0h	Specifies acceptable latency that the Endpoint can tolerate while transitioning from L1 to L0. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
8-6	AL0L	R	0h	Specifies acceptable latency that the Endpoint can tolerate while transitioning from L0S to L0. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
5	ETFS	R	0h	hard coded to zero .
4-3	PFS	R	0h	This field is used to extend the tag field by combining unused Function bits with the tag bits. This field is hardwired to 00 to disable this feature.
2-0	MP	R	1h	Specifies maximum payload size supported by the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

3.5.3.30 PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS Register (Offset = C8h) [reset = 2810h]

PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS is shown in Figure 12-1518 and described in Table 12-2978.

Return to the Summary Table.

This register contains control and status bits associated with the device.

Table 12-2977 PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00C8h

Figure 12-1518 PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS Register

31	30	29	28	27	26	25	24
R8
R-0h

23	22	21	20	19	18	17	16
R8		TP	APD	URD	FED	NFED	CED
R-0h		R-0h	R-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h

15	14	13	12	11	10	9	8
R7	MRR			ENS	APPME	PFE	ETE
R-0h	R/W-2h			R/W-1h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
MP			ERO	EURR	EFER	ENFER	ECER
R/W-0h			R/W-1h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-2978 PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-22	R8	R	0h	N/A
21	TP	R	0h	Indicates if any of the Non-Posted requests issued by the RC are still pending.
20	APD	R	0h	Set when auxiliary power is detected by the device. This is an unused field.
19	URD	R/W1C	0h	Set to 1 by the Controller when it receives an unsupported request.
18	FED	R/W1C	0h	Set to 1 by the Controller when it detects a fatal error, regardless of whether the error is masked.
17	NFED	R/W1C	0h	Set to 1 by the Controller when it detects a non-fatal error, regardless of whether the error is masked.
16	CED	R/W1C	0h	Set to 1 by the Controller when it detects a correctable error, regardless of whether the error is masked.
15	R7	R	0h	Hardwired to 0.
14-12	MRR	R/W	2h	Specifies the maximum size allowed in read requests generated by the device.
11	ENS	R/W	1h	If this bit is Set, the Function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency.
10	APPME	R	0h	Hardwired to 0
9	PFE	R	0h	Hardwired to 0
8	ETE	R	0h	extended tag not enabled. Hence hard coded to zero .
7-5	MP	R/W	0h	Specifies the maximum TLP payload size configured. The device must be able to receive a TLP of this maximum size, and should not generate TLP's larger than this value. Software must set this field based on the maximum payload size in the Device Capabilities Register, and the capability of the other side.
4	ERO	R/W	1h	When set, this bit indicates that the device is allowed to set the Relaxed Ordering bit in the Attributes field of transactions initiated from it., when the transactions do not require Strong Ordering.
3	EURR	R/W	0h	This bit is used to gate the CORRECTABLE_ERROR_OUT, NON_FATAL_ERROR_OUT, FATAL_ERROR_OUT output in Root Port mode on receiving unsupported requests. Note: Alternately, the SERR Enable bit in the Command Register can also be set to enable assertion of FATAL_ERROR_OUT on receiving uncorrectable unsupported requests.
2	EFER	R/W	0h	This bit is used to gate the FATAL_ERROR_OUT output of the Controller in Root Port mode. When an Uncorrectable, Unmasked Error with Uncorrectable Error Severity set to 1 is detected Internally or when a ERR_FATAL message is received by the Controller, in Root Port mode, this bit gates the assertion of FATAL_ERROR_OUT output. Note: Alternately, the SERR Enable bit in the Command Register can also be set to enable assertion of FATAL_ERROR_OUT.
1	ENFER	R/W	0h	This bit is used to gate the NON_FATAL_ERROR_OUT output of the Controller in Root Port mode. When an Uncorrectable, Unmasked Error with Uncorrectable Error Severity set to 0 is detected Internally or when a ERR_NON_FATAL message is received by the Controller, in Root Port mode, this bit gates the assertion of NON_FATAL_ERROR_OUT output. Note: Alternately, the SERR Enable bit in the Command Register can also be set to enable assertion of NON_FATAL_ERROR_OUT.
0	ECER	R/W	0h	This bit is used to gate the CORRECTABLE_ERROR_OUT output of the Controller in Root Port mode. When a Correctable and Unmasked Error is detected Internally or when a ERR_CORR message is received by the Controller, in Root Port mode, this bit gates the assertion of CORRECTABLE_ERROR_OUT output.

3.5.3.31 PCIE_CORE_RP_I_LINK_CAP Register (Offset = CCh) [reset = 0061AC44h]

PCIE_CORE_RP_I_LINK_CAP is shown in Figure 12-1519 and described in Table 12-2980.

Return to the Summary Table.

This register advertises the link-specific capabilities of the device incorporating the
PCIe Controller.

Table 12-2979 PCIE_CORE_RP_I_LINK_CAP Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00CCh

Figure 12-1519 PCIE_CORE_RP_I_LINK_CAP Register

31	30	29	28	27	26	25	24
PN
R-0h

23	22	21	20	19	18	17	16
R9	ASPMOC	LBNC	DARC	SERC	CPM	L1EL
R-0h	R-1h	R-1h	R-0h	R-0h	R-0h	R-3h

15	14	13	12	11	10	9	8
L1EL	L0EL			ASPM		MLW
R-3h	R-2h			R-3h		R-4h

7	6	5	4	3	2	1	0
MLW				MLS
R-4h				R-4h

LEGEND: R = Read Only; -n = value after reset

Table 12-2980 PCIE_CORE_RP_I_LINK_CAP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	PN	R	0h	Specifies the port number assigned to the PCI Express link connected to this device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
23	R9	R	0h	Reserved
22	ASPMOC	R	1h	A 1 in this position indicates the device supports the ASPM Optionality feature. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
21	LBNC	R	1h	A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
20	DARC	R	0h	Set to 1 if the device is capable of reporting that the DL Control and Management State Machine has reached the DL_Active state. This bit is hardwired to 0, as this version of the Controller does not support the feature.
19	SERC	R	0h	Indicates the capability of the device to report a Surprise Down error condition. This bit is hardwired to 0, as this version of the Controller does not support the feature.
18	CPM	R	0h	Indicates that the device supports removal of reference clocks. Not supported in this version of the Controller. Hardwired to 0.
17-15	L1EL	R	3h	Specifies the exit latency from L1 state. This parameter is dependent on the Physical Layer implementation. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
14-12	L0EL	R	2h	Specifies the time required for the device to transition from L0S to L0. This parameter is dependent on the Physical Layer implementation. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
11-10	ASPM	R	3h	Indicates the level of ASPM support provided by the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
9-4	MLW	R	4h	Indicates the maximum number of lanes supported by the device. This field is hardwired based on the setting of the LANE_COUNT_IN strap input.
3-0	MLS	R	4h	Indicates the speeds supported by the link [2.5 GT/s , 5 GT/s , 8 GT/s , 16 GT/s per lane]. This field is hardwired to 0001 [2.5GT/s] when the strap input PCIE_GENERATION_SEL is set to 0, to 0010 [5 GT/s] when the strap is set to 1 , and to 0011 [8 GT/s] when the strap input is set to 10 , and to 0100 [16 GT/s] when the strap input is set to 11 .

3.5.3.32 PCIE_CORE_RP_I_LINK_CTRL_STATUS Register (Offset = D0h) [reset = 00410000h]

PCIE_CORE_RP_I_LINK_CTRL_STATUS is shown in Figure 12-1520 and described in Table 12-2982.

Return to the Summary Table.

This register contains control and status bits specific to the PCI Express link.

Table 12-2981 PCIE_CORE_RP_I_LINK_CTRL_STATUS Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00D0h

Figure 12-1520 PCIE_CORE_RP_I_LINK_CTRL_STATUS Register

31	30	29	28	27	26	25	24
LABS	LBMS	DA	SCC	LTS	R12	NLW
R/W1C-0h	R/W1C-0h	R-0h	R-0h	R-0h	R-0h	R-4h

23	22	21	20	19	18	17	16
NLW				NLS
R-4h				R-1h

15	14	13	12	11	10	9	8
R11				LABIE	LBMIE	HAWD	ECPM
R-0h				R/W-0h	R/W-0h	R/W-0h	R-0h

7	6	5	4	3	2	1	0
ES	CCC	RL	LD	RCB	R10	ASPMC
R/W-0h	R/W-0h	R-0h	R/W-0h	R-0h	R-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-2982 PCIE_CORE_RP_I_LINK_CTRL_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31	LABS	R/W1C	0h	This bit is Set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation. This triggers an interrupt to be generated through PHY_INTERRUPT_OUT if enabled. Hardwired to 0 if Link Bandwidth Notification Capability is 0.
30	LBMS	R/W1C	0h	This bit is Set by hardware to indicate that either link training has completed following write to retrain link bit, or when HW has changed link speed or width to attempt to correct unreliable link operation. This triggers an interrupt to be generated through PHY_INTERRUPT_OUT if enabled. Hardwired to 0 if Link Bandwidth Notification Capability is 0.
29	DA	R	0h	Indicates the status of the Data Link Layer. Set to 1 when the DL Control and Management State Machine has reached the DL_Active state. This bit is hardwired to 0 in this version of the Controller.
28	SCC	R	0h	Indicates that the device uses the reference clock provided by the connector. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
27	LTS	R	0h	This bit is set to 1 when the LTSSM is in the Recovery or Configuration states, or if a 1 has been written to the Retrain Link bit but the link training has not yet begun.
26	R12	R	0h	Reserved
25-20	NLW	R	4h	Set at the end of link training to the actual link width negotiated between the two sides.
19-16	NLS	R	1h	Negotiated link speed of the device. The only supported speed ids are 2.5 GT/s per lane [0001],5 GT/s per lane [0010] ,8 GT/s per lane [0011],16 GT/s per lane [0100].
15-12	R11	R	0h	Reserved
11	LABIE	R/W	0h	When Set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been Set. This enables an interrupt to be generated through PHY_INTERRUPT_OUT if triggered. Hardwired to 0 if Link Bandwidth Notification Capability is 0.
10	LBMIE	R/W	0h	When Set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been Set. This enables an interrupt to be generated through PHY_INTERRUPT_OUT if triggered. Hardwired to 0 if Link Bandwidth Notification Capability is 0.
9	HAWD	R/W	0h	When this bit is set, the local application must not request to change the operating width of the link, other than attempting to correct unreliable Link operation by reducing Link width.
8	ECPM	R	0h	This field is hardwired to 0 when the Controller is in the RC mode.
7	ES	R/W	0h	Set to 1 to extend the sequence of ordered sets transmitted while exiting from the L0S state.
6	CCC	R/W	0h	A value of 0 indicates that the reference clock of this device is asynchronous to that of the upstream device. A value of 1 indicates that the reference clock is common.
5	RL	R	0h	Setting this bit to 1 causes the LTSSM to initiate link training. This bit always reads as 0. This bit can be set by Host SW at any time independent of the LTSSM state. If the LTSSM is not in L0 state, the Controller will internally register the retrain command and initiate the link retrain immediately after the LTSSM reaches L0. For example, if the LTSSM is already in Recovery, the Controller will initiate Retrain Link after the LTSSM transitions back to L0 state.
4	LD	R/W	0h	Writing a 1 to this bit position causes the LTSSM to go to the Disable Link state. The LTSSM stays in the Disable Link state while this bit is set.
3	RCB	R	0h	Indicates the Read Completion Boundary of the Root Port [0 = 64 bytes, 1 = 128 bytes]. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
2	R10	R	0h	Reserved
1-0	ASPMC	R/W	0h	Controls the level of ASPM support on the PCI Express link associated with the function. The valid setting are 00: ASPM disabled 01: L0s entry enabled, L1 disabled 10: L1 entry enabled, L0s disabled 11: Both L0s and L1 enabled. Note that the ASPM Control bits can be enabled only if the corresponding ASPM Support [1:0] bit is 1 in the Link Capabilities Register.

3.5.3.33 PCIE_CORE_RP_I_SLOT_CAPABILITY Register (Offset = D4h) [reset = 0h]

PCIE_CORE_RP_I_SLOT_CAPABILITY is shown in Figure 12-1521 and described in Table 12-2984.

Return to the Summary Table.

The Slot Capabilities register identifies PCI Express slot specific capabilities.

Table 12-2983 PCIE_CORE_RP_I_SLOT_CAPABILITY Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00D4h

Figure 12-1521 PCIE_CORE_RP_I_SLOT_CAPABILITY Register

31	30	29	28	27	26	25	24
PSN
R-0h

23	22	21	20	19	18	17	16
PSN					NCCS	EIP	SPLS
R-0h					R-0h	R-0h	R-0h

15	14	13	12	11	10	9	8
SPLS	SPLV
R-0h	R-0h

7	6	5	4	3	2	1	0
SPLV	HPC	HPS	PIP	AIP	MRLSP	PCP	ABPRSNT
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-2984 PCIE_CORE_RP_I_SLOT_CAPABILITY Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	PSN	R	0h	This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis, regardless of the form factor associated with the slot. This field must be initialized to zero for Ports connected to devices that are either integrated on the system board or integrated within the same silicon as the Switch device or Root Port.
18	NCCS	R	0h	When Set, this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be Set if the hot-plug capable Port is able to accept writes to all fields of the Slot Control register without delay between successive writes.
17	EIP	R	0h	When Set, this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot.
16-15	SPLS	R	0h	Specifies the scale used for the Slot Power Limit Value . Range of Values: 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x This register must be implemented if the Slot Implemented bit is Set. Writes to this register also cause the Port to send the Set_Slot_Power_Limit Message. The default value prior to hardware/firmware initialization is 00b.
14-7	SPLV	R	0h	In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by the slot [see Section 6.9] or by other means to the adapter. Power limit [in Watts] is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field except when the Slot Power Limit Scale field equals 00b [1.0x] and Slot Power Limit Value exceeds EFh, the following alternative encodings are used: F0h = 250 W Slot Power Limit F1h = 275 W Slot Power Limit F2h = 300 W Slot Power Limit F3h to FFh = Reserved for Slot Power Limit values above 300 W This register must be implemented if the Slot Implemented bit is Set. Writes to this register also cause the Port to send the Set_Slot_Power_Limit Message. The default value prior to hardware/firmware initialization is 0000 0000b.
6	HPC	R	0h	When Set, this bit indicates that this slot is capable of supporting hot-plug operations.
5	HPS	R	0h	When Set, this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the operating system to allow for such removal without impacting continued software operation.
4	PIP	R	0h	When Set, this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot.
3	AIP	R	0h	When Set, this bit indicates that an Attention Indicator is electrically controlled by the chassis.
2	MRLSP	R	0h	When Set, this bit indicates that an MRL Sensor is implemented on the chassis for this slot.
1	PCP	R	0h	When Set, this bit indicates that a software programmable Power Controller is implemented for this slot/adapter [depending on form factor].
0	ABPRSNT	R	0h	When Set, this bit indicates that an Attention Button for this slot is electrically controlled by the chassis.

3.5.3.34 PCIE_CORE_RP_I_SLOT_CTRL_STATUS Register (Offset = D8h) [reset = 002007C0h]

PCIE_CORE_RP_I_SLOT_CTRL_STATUS is shown in Figure 12-1522 and described in Table 12-2986.

Return to the Summary Table.

This register contains control bits specific to PCI Express slot parameters and status
bits specific to the PCI Express Slot. All the read-write bits in this register can also be written
from the local management APB bus.

Table 12-2985 PCIE_CORE_RP_I_SLOT_CTRL_STATUS Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00D8h

Figure 12-1522 PCIE_CORE_RP_I_SLOT_CTRL_STATUS Register

31	30	29	28	27	26	25	24
RSCS2							DLLSC
R-0h							R/W1C-0h

23	22	21	20	19	18	17	16
EMIS	PDS	MRLSS	CMDCMPL	PDC	MRLSC	PFD	ABPRSD
R-0h	R-0h	R-1h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h

15	14	13	12	11	10	9	8
RSCS1			DLLSCE	EMIC	PCC	PIC
R-0h			R/W-0h	R-0h	R/W-1h	R/W-3h

7	6	5	4	3	2	1	0
AIC		HPIE	CCIE	PDCE	MSCE	PFDE	ABPE
R/W-3h		R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-2986 PCIE_CORE_RP_I_SLOT_CTRL_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RSCS2	R	0h	N/A
24	DLLSC	R/W1C	0h	This bit is Set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event, software must read the Data Link Layer Link Active bit of the Link Status register to determine if the Link is active before initiating configuration cycles to the hot plugged device.
23	EMIS	R	0h	If an Electromechanical Interlock is implemented, this bit indicates the status of the Electromechanical Interlock. Defined encodings are: 0b Electromechanical Interlock Disengaged 1b Electromechanical Interlock Engaged
22	PDS	R	0h	This bit indicates the presence of an adapter in the slot, reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism defined for the slot's corresponding form factor. Note that the in-band presence detect mechanism requires that power be applied to an adapter for its presence to be detected. Consequently, form factors that require a power controller for hot-plug must implement a physical pin presence detect mechanism. Defined encodings are: 0b Slot Empty 1b Card Present in slot.
21	MRLSS	R	1h	This bit reports the status of the MRL sensor if implemented. Defined encodings are: 0b MRL Closed 1b MRL Open
20	CMDCMPL	R/W1C	0h	If Command Completed notification is supported [if the No Command Completed Support bit in the Slot Capabilities register is 0b], this bit is Set when a hot-plug command has completed and the Hot-Plug Controller is ready to accept a subsequent command. The Command Completed status bit is Set as an indication to host software that the Hot- Plug Controller has processed the previous command and is ready to receive the next command it provides no guarantee that the action corresponding to the command is complete. If Command Completed notification is not supported, this bit must be hardwired to 0b.
19	PDC	R/W1C	0h	This bit is set when the value reported in the Presence Detect State bit is changed.
18	MRLSC	R/W1C	0h	If an MRL sensor is implemented, this bit is Set when a MRL Sensor state change is detected. If an MRL sensor is not implemented, this bit must not be Set.
17	PFD	R/W1C	0h	If a Power Controller that supports power fault detection is implemented, this bit is Set when the Power Controller detects a power fault at this slot. Note that, depending on hardware capability, it is possible that a power fault can be detected at any time, independent of the Power Controller Control setting or the occupancy of the slot. If power fault detection is not supported, this bit must not be Set.
16	ABPRSD	R/W1C	0h	If an Attention Button is implemented, this bit is Set when the attention button is pressed. If an Attention Button is not supported, this bit must not be Set.
15-13	RSCS1	R	0h	Reserved
12	DLLSCE	R/W	0h	If the Data Link Layer Link Active Reporting capability is 1b, this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active Reporting Capable bit is 0b, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b.
11	EMIC	R	0h	If an Electromechanical Interlock is implemented, a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit always returns a 0b.
10	PCC	R/W	1h	If a Power Controller is implemented, this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write, if required to, without waiting for the previous command to complete in which case the read value is undefined. The defined encodings are: 0b Power On 1b Power Off
9-8	PIC	R/W	3h	If a Power Indicator is implemented, writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write,Defined encodings are: 00b Reserved 01b On 10b Blink 11b Off
7-6	AIC	R/W	3h	If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write,Defined encodings are: 00b Reserved 01b On 10b Blink 11b Off
5	HPIE	R/W	0h	When Set, this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is Clear, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b.
4	CCIE	R/W	0h	If Command Completed notification is supported [if the No Command Completed Support bit in the Slot Capabilities register is 0b], when Set, this bit enables software notification when a hot-plug command is completed by the Hot-Plug Controller. If Command Completed notification is not supported, this bit must be hardwired to 0b. Default value of this bit is 0b.
3	PDCE	R/W	0h	When Set, this bit enables software notification on a presence detect changed event. If the Hot-Plug Capable bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b.
2	MSCE	R/W	0h	When Set, this bit enables software notification on a MRL sensor changed event If the MRL Sensor Present bit in the Slot Capabilities register is Clear, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b.
1	PFDE	R/W	0h	When Set, this bit enables software notification on a power fault event If a Power Controller that supports power fault detection is not implemented, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b.
0	ABPE	R/W	0h	When Set to 1b, this bit enables software notification on an attention button pressed event. If the Attention Button Present bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b.

3.5.3.35 PCIE_CORE_RP_I_ROOT_CTRL_CAP Register (Offset = DCh) [reset = 0h]

PCIE_CORE_RP_I_ROOT_CTRL_CAP is shown in Figure 12-1523 and described in Table 12-2988.

Return to the Summary Table.

This register controls and identifies PCI Express Root Complex specific parameters.

Table 12-2987 PCIE_CORE_RP_I_ROOT_CTRL_CAP Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00DCh

Figure 12-1523 PCIE_CORE_RP_I_ROOT_CTRL_CAP Register

31	30	29	28	27	26	25	24
R27
R-0h

23	22	21	20	19	18	17	16
R27
R-0h

15	14	13	12	11	10	9	8
R27
R-0h

7	6	5	4	3	2	1	0
R27			CRSSVE	PMEIE	SEFEE	SENFEE	SECEE
R-0h			R-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-2988 PCIE_CORE_RP_I_ROOT_CTRL_CAP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	R27	R	0h	Reserved
4	CRSSVE	R	0h	This capability is not implemented and this bit is hardwired to 0b.
3	PMEIE	R/W	0h	This field can be read and written from the local management APB bus, but its value is not used within the Controller.
2	SEFEE	R/W	0h	This field can be read and written from the local management APB bus, but its value is not used within the Controller.
1	SENFEE	R/W	0h	This field can be read and written from the local management APB bus, but its value is not used within the Controller.
0	SECEE	R/W	0h	This field can be read and written from the local management APB bus, but its value is not used within the Controller.

3.5.3.36 PCIE_CORE_RP_I_ROOT_STATUS Register (Offset = E0h) [reset = 0h]

PCIE_CORE_RP_I_ROOT_STATUS is shown in Figure 12-1524 and described in Table 12-2990.

Return to the Summary Table.

This register controls and identifies PCI Express Root Complex specific parameters.

Table 12-2989 PCIE_CORE_RP_I_ROOT_STATUS Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00E0h

Figure 12-1524 PCIE_CORE_RP_I_ROOT_STATUS Register

31	30	29	28	27	26	25	24
R18
R-0h

23	22	21	20	19	18	17	16
R18						PMEP	PMES
R-0h						R-0h	R/W1C-0h

15	14	13	12	11	10	9	8
PMERID
R-0h

7	6	5	4	3	2	1	0
PMERID
R-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-2990 PCIE_CORE_RP_I_ROOT_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	R18	R	0h	Reserved
17	PMEP	R	0h	This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
16	PMES	R/W1C	0h	This field is not set by the Controller but can be cleared by writing a 1 from the local management APB bus. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
15-0	PMERID	R	0h	This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

3.5.3.37 PCIE_CORE_RP_I_PCIE_CAP_2 Register (Offset = E4h) [reset = X]

PCIE_CORE_RP_I_PCIE_CAP_2 is shown in Figure 12-1525 and described in Table 12-2992.

Return to the Summary Table.

This register advertises the capabilities of the PCI Express device.

Table 12-2991 PCIE_CORE_RP_I_PCIE_CAP_2 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00E4h

Figure 12-1525 PCIE_CORE_RP_I_PCIE_CAP_2 Register

31	30	29	28	27	26	25	24
R16
R-0h

23	22	21	20	19	18	17	16
MEEP		EEPS	EXFS	OBFF		T10RS	T10CS
R-1h		R-1h	R-1h	R-1h		R-0h	R-1h

15	14	13	12	11	10	9	8
R15		RESERVED	TPHC	LMS	R14	ACS128	ACS64
R-0h		R-X	R-0h	R-1h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
ACS32	AOPRS	AFS	CTDS	CTR
R-0h	R-0h	R-1h	R-1h	R-2h

LEGEND: R = Read Only; -n = value after reset

Table 12-2992 PCIE_CORE_RP_I_PCIE_CAP_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	R16	R	0h	Reserved
23-22	MEEP	R	1h	Indicates the maximum number of End-End TLP Prefixes supported by the Function. The supported values are: 01b 1 End-End TLP Prefix 10b 2 End-End TLP Prefixes. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write
21	EEPS	R	1h	Indicates whether the Function supports End-End TLP Prefixes. A 1 in this field indicates that the Function supports receiving TLPs containing End-End TLP Prefixes. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write
20	EXFS	R	1h	Indicates that the Function supports the 3-bit definition of the Fmt field in the TLP header. This bit is hardwired to 1 for all Physical Functions.
19-18	OBFF	R	1h	A 1 in this bit position indicates that the Function supports the Optimized Buffer Flush/Fill [OBFF] capability using message signaling. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
17	T10RS	R	0h	If set function supports 1-bit requester capability otherwise, the function does not. This bit can be disabled using local management register.
16	T10CS	R	1h	If set function supports 1-bit completer capability otherwise, the function does not. This field can be modified using local management interface.
15-14	R15	R	0h	Reserved
13	RESERVED	R	X
12	TPHC	R	0h	Hardwired to 0.
11	LMS	R	1h	A value of 1b indicates support for the optional Latency Tolerance Reporting [LTR] mechanism. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
10	R14	R	0h	Reserved
9	ACS128	R	0h	Hardwired to 0.
8	ACS64	R	0h	Hardwired to 0.
7	ACS32	R	0h	Hardwired to 0.
6	AOPRS	R	0h	Applicable only to Switch Upstream Ports, Switch Downstream Ports, and Root Ports must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
5	AFS	R	1h	A 1 in this bit indicates that the device is able to forward TLPs with function number greater than 8. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
4	CTDS	R	1h	A 1 in this field indicates that the associated Function supports the capability to turn off its Completion timeout. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
3-0	CTR	R	2h	Specifies the Completion Timeout values supported by the device. This field is set by default to 0010 [10 ms - 250 ms], but can be modified from the local management APB bus. The actual timeout values are in two programmable local management registers, which allow the timeout settings of the two sub-ranges within Range B to be programmed independently. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

3.5.3.38 PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS_2 Register (Offset = E8h) [reset = 0h]

PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS_2 is shown in Figure 12-1526 and described in Table 12-2994.

Return to the Summary Table.

This register contains control and status bits associated with the device.

Table 12-2993 PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS_2 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00E8h

Figure 12-1526 PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS_2 Register

31	30	29	28	27	26	25	24
R20
R-0h

23	22	21	20	19	18	17	16
R20
R-0h

15	14	13	12	11	10	9	8
R20	OBFFE		T10RE	R19	LTRME	ICE	IRE
R-0h	R/W-0h		R-0h	R-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
R18	AORE	AFE	CTD	CTV
R-0h	R-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-2994 PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-15	R20	R	0h	N/A
14-13	OBFFE	R/W	0h	Enables the Optimized Buffer Flush/Fill [OBFF] capability in the device. Valid settings are 00 [disabled], 01 [Variation A], and 10 [Variation B].
12	T10RE	R	0h	10bit TAGs generation are not supported in this configuration.
11	R19	R	0h	Reserved
10	LTRME	R/W	0h	This must be set to 1 to enable the Latency Tolerance Reporting Mechanism. This bit is implemented only in PF 0. Its default value is 1, but can be modified from the local management bus. This bit is read-only in PF 1.
9	ICE	R/W	0h	When this bit is 1, the RC is allowed to set the ID-based Ordering [IDO] Attribute bit in the Completions it generates.
8	IRE	R/W	0h	When this bit is 1, the RC is allowed to set the ID-based Ordering [IDO] Attribute bit in the requests it generates.
7	R18	R	0h	Reserved
6	AORE	R	0h	This bit must be set to enable the generation of Atomic Op Requests. If the client logic attempts to send an Atomic Op when this bit is not set, logic in the Controller will nullify the TLP on its way to the link.
5	AFE	R/W	0h	A 1 in this filed indicates that the port treats fields 7:0 of the ID as function number while converting a Type 1 config packet to type 0 config packet.
4	CTD	R/W	0h	Setting this bit disables the Completion Timeout in the device.
3-0	CTV	R/W	0h	Specifies the Completion Timeout value for the device. Allowable values are 0101 [sub-range 1] and 0110 [sub-range 2]. The corresponding timeout values are stored in the local management register's Completion Timeout Interval Registers 0 and 1, respectively. Value of 0 selects completion timeout from Completion-Timeout-Interval-Registers-0 in local management register.

3.5.3.39 PCIE_CORE_RP_I_LINK_CAP_2 Register (Offset = ECh) [reset = X]

PCIE_CORE_RP_I_LINK_CAP_2 is shown in Figure 12-1527 and described in Table 12-2996.

Return to the Summary Table.

This register advertises the supported link speeds of the Controller.

Table 12-2995 PCIE_CORE_RP_I_LINK_CAP_2 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00ECh

Figure 12-1527 PCIE_CORE_RP_I_LINK_CAP_2 Register

31	30	29	28	27	26	25	24
R31	R25						TWRTPDS
R-0h	R-0h						R-1h

23	22	21	20	19	18	17	16
RTPDS	R3			LSORSSV
R-1h	R-0h			R-0h

15	14	13	12	11	10	9	8
R2			LSOGSSV				R1
R-0h			R-0h				R-0h

7	6	5	4	3	2	1	0
R1			SLSV				RESERVED
R-0h			R-Fh				R-X

LEGEND: R = Read Only; -n = value after reset

Table 12-2996 PCIE_CORE_RP_I_LINK_CAP_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	R31	R	0h	Indicates support for the optional Device Readiness Status [DRS] capability. This capability is currently not supported in the Controller.
30-25	R25	R	0h	Reserved
24	TWRTPDS	R	1h	When set to 1b, this bit indicates that the associated Port supports detection and reporting of two Retimers presence. This bit is valid for both Downstream Ports and Upstream Ports.
23	RTPDS	R	1h	When set to 1b, this bit indicates that the associated Port supports detection and reporting of Retimer presence. This bit is valid for both Downstream Ports and Upstream Ports.
22-20	R3	R	0h	Reserved
19-16	LSORSSV	R	0h	If this field is non-zero, it indicates that the Port, when operating at the indicated speed[s] supports SRIS and also supports receiving SKP OS at the rate defined for SRNS while running in SRIS.
15-13	R2	R	0h	Reserved
12-9	LSOGSSV	R	0h	If this field is non-zero, it indicates that the Port, when operating at the indicated speed[s] supports SRIS and also supports software control of the SKP Ordered Set transmission scheduling rate.
8-5	R1	R	0h	Reserved
4-1	SLSV	R	Fh	This field indicates the supported link speeds of the Controller. For each bit, a value of 1 indicates that the corresponding link speed is supported, while a value of 0 indicates that the corresponding speed is not supported. The bits corresponding to various link speeds are: Bit 1 = Link Speed 2.5 GT/s, Bit 2 = Link Speed 5 GT/s, Bit 3 = Link Speed 8 GT/s, Bit 4 = Link Speed 16 GT/s. This field is hardwired to 0001 [2.5 GT/s] when the PCIE_GENERATION_SEL strap pins of the Controller are set to 0, 0011 [2.5 and 5 GT/s] when the strap is set to 1, and 0111 [2.5, 5, and 8 GT/s] when the strap pin is set to 10, and 1111 [2.5, 5, 8 and 16 GT/s] when the strap pin is set to 11.
0	RESERVED	R	X

3.5.3.40 PCIE_CORE_RP_I_LINK_CTRL_STATUS_2 Register (Offset = F0h) [reset = 00010004h]

PCIE_CORE_RP_I_LINK_CTRL_STATUS_2 is shown in Figure 12-1528 and described in Table 12-2998.

Return to the Summary Table.

This register contains control and status bits specific to the PCI Express link.

Table 12-2997 PCIE_CORE_RP_I_LINK_CTRL_STATUS_2 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 00F0h

Figure 12-1528 PCIE_CORE_RP_I_LINK_CTRL_STATUS_2 Register

31	30	29	28	27	26	25	24
DMR	DCP			R21
R-0h	R-0h			R-0h

23	22	21	20	19	18	17	16
TWRTP	RTP	LE	EP3S	EP2S	EP1S	EQC	CDEL
R-0h	R-0h	R/W1C-0h	R-0h	R-0h	R-0h	R-0h	R-1h

15	14	13	12	11	10	9	8
CD				CS	EMC	TM
R/W-0h				R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
TM	SD	HASD	EC	TLS
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-4h

LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-2998 PCIE_CORE_RP_I_LINK_CTRL_STATUS_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DMR	R	0h	DRS is not supported by the Controller and hence this field is not implemented.
30-28	DCP	R	0h	DRS is not supported by the Controller and hence this field is not implemented.
27-24	R21	R	0h	Reserved
23	TWRTP	R	0h	When set to 1b, this bit indicates that two Retimers were present during the most recent Link negotiation.
22	RTP	R	0h	When set to 1b, this bit indicates that a Retimer was present during the most recent Link negotiation.
21	LE	R/W1C	0h	When the Controller [RP] receives an 8GTs equalization request from an Upstream Port the Controller internally sets this bit to 1. [that is, when RP is in the Recovery.RcvrCfg state and receives 8 consecutive TS2 Ordered Sets with the Request Equalization bit set to 1b] The LOCAL_INTERRUPT output is also asserted, if Link Equalization Request Interrupt Enable is enabled.
20	EP3S	R	0h	This bit, when set to 1, indicates that the Phase 3 of the Transmitter Equalization procedure has completed successfully. STICKY
19	EP2S	R	0h	This bit, when set to 1, indicates that the Phase 2 of the Transmitter Equalization procedure has completed successfully. STICKY
18	EP1S	R	0h	This bit, when set to 1, indicates that the Phase 1 of the Transmitter Equalization procedure has completed successfully. STICKY
17	EQC	R	0h	This bit, when set to 1, indicates that the Transmitter Equalization procedure has completed. STICKY
16	CDEL	R	1h	This status bit indicates the current operating de-emphasis level of the transmitter [0 = -6dB, 1 = -3.5dB].
15-12	CD	R/W	0h	This bit sets the de-emphasis level [for 5 GT/s operation] or the Transmitter Preset level [for 8 GT/s or 16 GT/s operation] when the LTSSM enters the Polling.Compliance state because of software setting the Enter Compliance bit in this register. It is used only when the link is running at 5 GT/s or 8 GT/s or 16 GT/s. At 5 GT/s, the only valid setting are 0 [-6 dB] and 1 [-3.5 dB]. STICKY
11	CS	R/W	0h	When this bit is set to 1, the device will transmit SKP ordered sets between compliance patterns. STICKY
10	EMC	R/W	0h	This field is intended for debug and compliance testing purposes only. If this bit is set to 1, the device will transmit the Modified Compliance Pattern when the LTSSM enters the Polling.Compliance substate. STICKY
9-7	TM	R/W	0h	This field is intended for debug and compliance testing purposes only. It controls the non-deemphasized voltage level at the transmitter outputs. Its encodings are: 000 = Normal operating range, 001 = 800 - 1200 mV for full swing and 400 - 700 mV for half swing, 010 - 111 = See PCI Express Base Specification 2.0. This field is reset to 0 when th LTSSM enters the Polling.Configuration substate during link training. STICKY.
6	SD	R/W	0h	This bit selects the de-emphasis level when the Controller is operating at 5 GT/s [0 = -6 dB, 1 = -3.5 dB].
5	HASD	R/W	0h	When this bit is set, the LTSSM is prevented from changing the operating speed of the link, other than reducing the speed to correct unreliable operation of the link. STICKY
4	EC	R/W	0h	This bit is used to force the Endpoint device to enter the Compliance mode. Software sets this bit to 1 and initiates a hot reset to force the device into the Compliance mode. The target speed for the Compliance mode is determined by the Target Link Speed field of this register. STICKY.
3-0	TLS	R/W	4h	This field sets the target speed when the software forces the link into Compliance mode by setting the Enter Compliance bit in this register [0001 = 2.5 GT/s, 0010 = 5 GT/s, 0100 = 8 GT/s, 1000 = 16 GT/s]. The default value of this field is 0001 [2.5 GT/s] when the PCIE_GENERATION_SEL [1:0] strap pins of the Controller are set to 0, 0010 [5 GT/s] when the strap is set to 1, and 0011 [8 GT/s] when the strap pin is set to 10 , and 0100 [16 GT/s] when the strap pin is set to 11. STICKY.

3.5.3.41 PCIE_CORE_RP_I_AER_ENHNCD_CAP Register (Offset = 100h) [reset = 15020001h]

PCIE_CORE_RP_I_AER_ENHNCD_CAP is shown in Figure 12-1529 and described in Table 12-3000.

Return to the Summary Table.

This is the first register in the PCI Express Advanced Error Reporting Capability
Structure. This register contains the PCI Express Extended Capability ID, the capability version
, and the pointer to the next capability structure.

Table 12-2999 PCIE_CORE_RP_I_AER_ENHNCD_CAP Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0100h

Figure 12-1529 PCIE_CORE_RP_I_AER_ENHNCD_CAP Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NCO												CV				PECID
R-150h												R-2h				R-1h

LEGEND: R = Read Only; -n = value after reset

Table 12-3000 PCIE_CORE_RP_I_AER_ENHNCD_CAP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	NCO	R	150h	Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16	CV	R	2h	Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 4'h2.
15-0	PECID	R	1h	This field is hardwired to the Capability ID assigned by PCI SIG to the PCI Express AER Extended Capability Structure [0001 hex].

3.5.3.42 PCIE_CORE_RP_I_UNCORR_ERR_STATUS Register (Offset = 104h) [reset = 0h]

PCIE_CORE_RP_I_UNCORR_ERR_STATUS is shown in Figure 12-1530 and described in Table 12-3002.

Return to the Summary Table.

This register provides the status of the various uncorrectable errors detected by the
PCI Express Controller. Software may clear any error bit by writing a 1 into the corresponding bit
position. The states of the bits in the Uncorrectable Error Mask Register have no effect on the
status bits of this register. In the case of certain errors detected by the Transaction Layer,
the associated TLP header is logged in the Header Log Registers.

Table 12-3001 PCIE_CORE_RP_I_UNCORR_ERR_STATUS Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0104h

Figure 12-1530 PCIE_CORE_RP_I_UNCORR_ERR_STATUS Register

31	30	29	28	27	26	25	24
R28
R-0h

23	22	21	20	19	18	17	16
R28	UIE	R27	URE	EE	MT	RO	UC
R-0h	R/W1C-0h	R-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h

15	14	13	12	11	10	9	8
CA	CT	FCPE	PT	R26
R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R-0h

7	6	5	4	3	2	1	0
R26		SDES	DLPE	R25			LTE
R-0h		R/W1C-0h	R/W1C-0h	R-0h			R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-3002 PCIE_CORE_RP_I_UNCORR_ERR_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	R28	R	0h	Reserved
22	UIE	R/W1C	0h	This bit is set when the Controller has detected an internal uncorrectable error [HAL parity error or an uncorrectable ECC error while reading from any of the RAMs]. This bit is also set in response to the client signaling an internal error through the input UNCORRECTABLE_ERROR_IN. This error is considered fatal by default.
21	R27	R	0h	Reserved
20	URE	R/W1C	0h	This bit is set when the Controller has received a request from the link that it does not support. This error is not Function-specific. This error is considered non-fatal by default, except for the special case outlined in PCI Express Base Specification 2.0. The header of the received request that caused the error is logged in the Header Log Registers.
19	EE	R/W1C	0h	This bit is set when the Controller has detected an ECRC error in a received TLP.
18	MT	R/W1C	0h	This bit is set when the Controller receives a malformed TLP from the link. This error is considered fatal by default. The header of the received TLP with error is logged in the Header Log Registers.
17	RO	R/W1C	0h	This bit is set when the Controller receives a TLP in violation of the receive credit currently available.
16	UC	R/W1C	0h	This bit is set when the Controller has received an unexpected Completion packet from the link.
15	CA	R/W1C	0h	This bit is set when the Controller has returned the Completer Abort [CA] status to a request received from the link. This error is considered non-fatal by default, except for the special cases outlined in PCI Express Base Specification 2.0. The header of the received request that caused the error is logged in the Header Log Registers.
14	CT	R/W1C	0h	This bit is set when the completion timer associated with an outstanding request times out. This error is considered non-fatal by default.
13	FCPE	R/W1C	0h	This bit is set when certain violations of the flow control protocol are detected by the Controller.
12	PT	R/W1C	0h	This bit is set when the Controller receives a poisoned TLP from the link. This error is considered non-fatal by default. The header of the received TLP with error is logged in the Header Log Registers.
11-6	R26	R	0h	Reserved
5	SDES	R/W1C	0h	This error status indicates Link up to Link down event. So Status bit is set upon LINK_DOWN_RESET_OUT event. This field is applicable to RC only and not for EP as per PCIE-spec.
4	DLPE	R/W1C	0h	This bit is set when the Controller receives an Ack or Nak DLLP whose sequence does not correspond to that of an unacknowledged TLP or that of the last acknowledged TLP [for details, refer to the PCI Express Base Specifications].
3-1	R25	R	0h	N/A
0	LTE	R/W1C	0h	This error indicates that link training is not successful and transition back to detect state. This Status bit is set on any LTSSM transition from Configuration to Detect or Recovery to Detect. This field is applicable to RC only and not for EP as per PCIE-spec.

3.5.3.43 PCIE_CORE_RP_I_UNCORR_ERR_MASK Register (Offset = 108h) [reset = 00400000h]

PCIE_CORE_RP_I_UNCORR_ERR_MASK is shown in Figure 12-1531 and described in Table 12-3004.

Return to the Summary Table.

The mask bits in this register control the reporting of uncorrectable errors. For each
error type in the Uncorrectable Error Status Register, there is a corresponding bit in this
register to mask its reporting. Setting the mask bit has the following effects: (1) The
occurrence of the error does not cause activation of the FATAL_ERROR_OUT or NON_FATAL_ERROR_OUT
output of the Controller, depending on the severity of the error. (2) The header of the TLP in which
the error was detected is not logged in the Header Log Registers. (3) The First Error Pointer in
the Advanced Error Capabilities and Control Register is not updated on the detection of the
error. The individual bits of the mask register are described below.

Table 12-3003 PCIE_CORE_RP_I_UNCORR_ERR_MASK Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0108h

Figure 12-1531 PCIE_CORE_RP_I_UNCORR_ERR_MASK Register

31	30	29	28	27	26	25	24
R32
R-0h

23	22	21	20	19	18	17	16
R32	UIEM	R31	UREM	EEM	MTM	ROM	UCM
R-0h	R/W-1h	R-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
CAM	CTM	FCPER	PTM	R30
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R-0h

7	6	5	4	3	2	1	0
R30		SDEM	DLPER	R29			LTEM
R-0h		R/W-0h	R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3004 PCIE_CORE_RP_I_UNCORR_ERR_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	R32	R	0h	Reserved
22	UIEM	R/W	1h	This bit is set to mask the reporting of internal errors. STICKY.
21	R31	R	0h	Reserved
20	UREM	R/W	0h	This bit is set to mask the reporting of unexpected requests received from the link. STICKY.
19	EEM	R/W	0h	This bit is set to mask the reporting of ECRC errors. STICKY.
18	MTM	R/W	0h	This bit is set to mask the reporting of malformed TLPs received from the link. STICKY.
17	ROM	R/W	0h	This bit is set to mask the reporting of violations of receive credit. STICKY.
16	UCM	R/W	0h	This bit is set to mask the reporting of unexpected Completions received by the Controller. STICKY.
15	CAM	R/W	0h	This bit is set to mask the reporting of the Controller sending a Completer Abort. STICKY.
14	CTM	R/W	0h	This bit is set to mask the reporting of Completion Timeouts. STICKY.
13	FCPER	R/W	0h	This bit is set to mask the reporting of Flow Control Protocol Errors. STICKY.
12	PTM	R/W	0h	This bit is set to mask the reporting of a Poisoned TLP. STICKY.
11-6	R30	R	0h	Reserved
5	SDESM	R/W	0h	This bit is set to mask the reporting of Surprise Down Error Status Mask. STICKY. This field is applicable to RC only and not for EP as per PCIE-spec.
4	DLPER	R/W	0h	This bit is set to mask the reporting of Data Link Protocol Errors. STICKY.
3-1	R29	R	0h	Reserved
0	LTEM	R/W	0h	This bit is set to mask the reporting of Link Training Error Mask. STICKY. This field is applicable to RC only and not for EP as per PCIE-spec.

3.5.3.44 PCIE_CORE_RP_I_UNCORR_ERR_SEVERITY Register (Offset = 10Ch) [reset = 00462030h]

PCIE_CORE_RP_I_UNCORR_ERR_SEVERITY is shown in Figure 12-1532 and described in Table 12-3006.

Return to the Summary Table.

The setting of this register determines whether an uncorrectable error is reported as a
fatal error or non-fatal, that is, whether the FATAL_ERROR_OUT or NON_FATAL_ERROR_OUT output of
the Controller is activated. If a severity bit of this register is 0,the corresponding error is
reported by the Controller by asserting NON_FATAL_ERROR_OUT. Otherwise, it is reported by asserting
FATAL_ERROR_OUT.

Table 12-3005 PCIE_CORE_RP_I_UNCORR_ERR_SEVERITY Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 010Ch

Figure 12-1532 PCIE_CORE_RP_I_UNCORR_ERR_SEVERITY Register

31	30	29	28	27	26	25	24
R37
R-0h

23	22	21	20	19	18	17	16
R37	UNCORR_INTRNL_ERR_SVRTY	R36	URES	EES	MTS	ROS	UCS
R-0h	R/W-1h	R-0h	R/W-0h	R/W-0h	R/W-1h	R/W-1h	R/W-0h

15	14	13	12	11	10	9	8
CAS	CTS	FCPES	PTS	R35
R/W-0h	R/W-0h	R/W-1h	R/W-0h	R-0h

7	6	5	4	3	2	1	0
R35		SDES	DLPES	R33			LTES
R-0h		R-1h	R/W-1h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3006 PCIE_CORE_RP_I_UNCORR_ERR_SEVERITY Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	R37	R	0h	N/A
22	UNCORR_INTRNL_ERR_SVRTY	R/W	1h	Severity of internal errors [0 = Non-Fatal, 1 = Fatal].
21	R36	R	0h	Reserved
20	URES	R/W	0h	Severity of unexpected requests received from the link [0 = Non-Fatal, 1 = Fatal]. STICKY.
19	EES	R/W	0h	Severity of ECRC errors [0 = Non-Fatal, 1 = Fatal]. STICKY.
18	MTS	R/W	1h	Severity of malformed TLPs received from the link [0 = Non-Fatal, 1 = Fatal]. STICKY.
17	ROS	R/W	1h	Severity of receive credit violations [0 = Non-Fatal, 1 = Fatal]. STICKY.
16	UCS	R/W	0h	Severity of unexpected Completions received by the Controller [0 = Non-Fatal, 1 = Fatal]. STICKY.
15	CAS	R/W	0h	Severity of sending a Completer Abort [0 = Non-Fatal, 1 = Fatal]. STICKY.
14	CTS	R/W	0h	Severity of Completion Timeouts [0 = Non-Fatal, 1 = Fatal]. STICKY.
13	FCPES	R/W	1h	Severity of a Flow Control Protocol Error [0 = Non-Fatal, 1 = Fatal]. STICKY.
12	PTS	R/W	0h	Severity of a Poisoned TLP error [0 = Non-Fatal, 1 = Fatal]. STICKY.
11-6	R35	R	0h	N/A
5	SDES	R/W	1h	surprise down error severity. [0 = Non-Fatal, 1 = Fatal]. STICKY. This field is applicable to RC only and not for EP as per PCIE-spec.
4	DLPES	R/W	1h	Severity of Data Link Protocol Errors [0 = Non-Fatal, 1 = Fatal]. STICKY.
3-1	R33	R	0h	Reserved
0	LTES	R/W	0h	Severity of Link Training Error [0 = Non-Fatal, 1 = Fatal]. STICKY. This field is applicable to RC only and not for EP as per PCIE-spec.

3.5.3.45 PCIE_CORE_RP_I_CORR_ERR_STATUS Register (Offset = 110h) [reset = 0h]

PCIE_CORE_RP_I_CORR_ERR_STATUS is shown in Figure 12-1533 and described in Table 12-3008.

Return to the Summary Table.

This register provides the status of the various correctable errors detected by the PCI
Express Controller. Software may clear any error bit by writing a 1 into the corresponding bit
position. The states of the bits in the Correctable Error Mask Register have no effect on the
status bits of this register. The setting of a correctable error status bit causes the Controller to
assert the CORRECTABLE_ERROR_OUT output if the error is not masked in the Correctable Error Mask
Register. Header logging of received TLPs does not apply to correctable errors.

Table 12-3007 PCIE_CORE_RP_I_CORR_ERR_STATUS Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0110h

Figure 12-1533 PCIE_CORE_RP_I_CORR_ERR_STATUS Register

31	30	29	28	27	26	25	24
R39
R-0h

23	22	21	20	19	18	17	16
R39
R-0h

15	14	13	12	11	10	9	8
HLOS	CIES	ANES	RTTS	R38			RNRS
R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R-0h			R/W1C-0h

7	6	5	4	3	2	1	0
BDS	BTS	R37					RES
R/W1C-0h	R/W1C-0h	R-0h					R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-3008 PCIE_CORE_RP_I_CORR_ERR_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	R39	R	0h	Reserved
15	HLOS	R/W1C	0h	This bit is set on a Header Log Register overflow, that is, when the header could not be logged in the Header Log Register because it is occupied by a previous header.
14	CIES	R/W1C	0h	This bit is set when the Controller has detected an internal correctable error condition [a correctable ECC error while reading from any of the RAMs]. This bit is also set in response to the client signaling an internal error through the input CORRECTABLE_ERROR_IN.
13	ANES	R/W1C	0h	This bit is set when an uncorrectable error occurs, which is determined to belong to one of the special cases described in the PCI Express Base Specification 2.0. This causes the Controller to assert the CORRECTABLE_ERROR_OUT output in place of NON_FATAL_ERROR_OUT.
12	RTTS	R/W1C	0h	This bit is set when the replay timer in the Data Link Layer of the Controller times out, causing the Controller to re-transmit a TLP.
11-9	R38	R	0h	Reserved
8	RNRS	R/W1C	0h	This bit is set when the replay count rolls over after three re-transmissions of a TLP at the Data Link Layer of the Controller.
7	BDS	R/W1C	0h	This bit is set when an LCRC error is detected in a received DLLP, and no errors were detected by the Physical Layer.
6	BTS	R/W1C	0h	This bit is set when an error is detected in a received TLP by the Data Link Layer of the Controller the conditions causing this error are [1] an LCRC error, [2] the packet terminates with EDB symbol, but its LCRC field does not equal the inverted value of the calculated CRC.
5-1	R37	R	0h	Reserved
0	RES	R/W1C	0h	This bit is set when an error is detected in the receive side of the Physical Layer of the Controller [e.g. an 8b10b decode error].

3.5.3.46 PCIE_CORE_RP_I_CORR_ERR_MASK Register (Offset = 114h) [reset = E000h]

PCIE_CORE_RP_I_CORR_ERR_MASK is shown in Figure 12-1534 and described in Table 12-3010.

Return to the Summary Table.

The mask bits in this register control the reporting of correctable errors. For each
error type in the Correctable Error Status Register, there is a corresponding bit in this
register to mask its reporting. When a mask bit is set the occurrence of the error is not
reported (by asserting the CORRECTABLE_ERROR_OUT output).

Table 12-3009 PCIE_CORE_RP_I_CORR_ERR_MASK Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0114h

Figure 12-1534 PCIE_CORE_RP_I_CORR_ERR_MASK Register

31	30	29	28	27	26	25	24
R42
R-0h

23	22	21	20	19	18	17	16
R42
R-0h

15	14	13	12	11	10	9	8
HLOM	CIEM	ANEM	RTTM	R41			RNRM
R/W-1h	R/W-1h	R/W-1h	R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
BDM	BTM	R40					REM
R/W-0h	R/W-0h	R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3010 PCIE_CORE_RP_I_CORR_ERR_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	R42	R	0h	Reserved
15	HLOM	R/W	1h	This bit, when set, masks the reporting of an error in response to a Header Log register overflow. STICKY.
14	CIEM	R/W	1h	This bit, when set, masks the reporting of an error in response to a corrected internal error condition. STICKY.
13	ANEM	R/W	1h	This bit, when set, masks the reporting of an error in response to an uncorrectable error occurence, which is determined to belong to one of the special cases in the PCI Express Base Specification 2.0. STICKY.
12	RTTM	R/W	0h	This bit, when set, masks the reporting of an error in response to a Replay Timer timeout event. STICKY.
11-9	R41	R	0h	Reserved
8	RNRM	R/W	0h	This bit, when set, masks the reporting of an error in response to a Replay Number Rollover event. STICKY.
7	BDM	R/W	0h	This bit, when set, masks the reporting of an error in response to a 'Bad DLLP' received. STICKY.
6	BTM	R/W	0h	This bit,when set, masks the reporting of an error in response to a 'Bad TLP' received. STICKY.
5-1	R40	R	0h	Reserved
0	REM	R/W	0h	This bit, when set, masks the reporting of Physical Layer errors. STICKY.

3.5.3.47 PCIE_CORE_RP_I_ADV_ERR_CAP_CTL Register (Offset = 118h) [reset = A0h]

PCIE_CORE_RP_I_ADV_ERR_CAP_CTL is shown in Figure 12-1535 and described in Table 12-3012.

Return to the Summary Table.

This register contains a pointer to the first error that is reported in the
Uncorrectable Error Status Register, and bits to enable ECRC generation and checking.

Table 12-3011 PCIE_CORE_RP_I_ADV_ERR_CAP_CTL Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0118h

Figure 12-1535 PCIE_CORE_RP_I_ADV_ERR_CAP_CTL Register

31	30	29	28	27	26	25	24
R43
R-0h

23	22	21	20	19	18	17	16
R43
R-0h

15	14	13	12	11	10	9	8
R43				TPLP	MHRE	MHRC	EEC
R-0h				R-0h	R-0h	R-0h	R/W-0h

7	6	5	4	3	2	1	0
ECC	EEG	EGC	FEP
R-1h	R/W-0h	R-1h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3012 PCIE_CORE_RP_I_ADV_ERR_CAP_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	R43	R	0h	Reserved
11	TPLP	R	0h	If Set and the First Error Pointer is valid, indicates that the TLP Prefix Log register contains valid information. If Clear or if First Error Pointer is invalid, the TLP Prefix Log register is undefined. Default value of this bit is 0. This bit is RsvdP if the End-End TLP Prefix Supported bit is CIf Set and the First Error Pointer is valid, indicates that the TLP Prefix Log register contains valid information. If Clear or if First Error Pointer is invalid, the TLP Prefix Log register is undefined.
10	MHRE	R	0h	Setting this bit enables the RC to log multiple error headers in its Header Log Registers. It is hardwired to 0.
9	MHRC	R	0h	This bit is set when the RC has the capability to log more than one error header in its Header Log Registers. It is hardwired to 0.
8	EEC	R/W	0h	Setting this bit enables ECRC checking on the receive side of the Controller. This bit is writable from the local management bus. STICKY.
7	ECC	R	1h	This read-only bit indicates to the software that the device is capable of checking ECRC in packets received from the link.
6	EEG	R/W	0h	Setting this bit enables the ECRC generation on the transmit side of the Controller. This bit is writable from the local management bus. STICKY.
5	EGC	R	1h	This read-only bit indicates to the software that the device is capable of generating ECRC in packets transmitted on the link.
4-0	FEP	R	0h	This is a 5-bit pointer to the bit position in the Uncorrectable Error Status Register corresponding to the error that was detected first. When there are multiple bits set in the Uncorrectable Error Status Register, this field informs the software which error was observed first. To prevent the field from being overwritten before the software is able to read it, this field is not updated while the status bit it points to in the Uncorrectable Error Status Register remains set. After the software clears this status bit, a subsequent error condition that sets any bit in the Uncorrectable Error Status Register will update the First Error Pointer. Any uncorrectable error type, including the special cases where the error is reported using an ERR_COR message, will set the First Error Pointer [assuming the software has reset the error pointed by it in the Uncorrectable Error Status Register]. STICKY.

3.5.3.48 PCIE_CORE_RP_I_HDR_LOG_0 Register (Offset = 11Ch) [reset = 0h]

PCIE_CORE_RP_I_HDR_LOG_0 is shown in Figure 12-1536 and described in Table 12-3014.

Return to the Summary Table.

This is the first of a set of four registers used to capture the header of a TLP
received by the Controller from the link upon detection of an uncorrectable error. When multiple bits
are set in the Uncorrectable Error Status Register, the captured header corresponds the the
error that was detected first, that is, the error pointed by the First Error Pointer. To prevent
the captured header from being over-written before software is able to read it, this register is
not updated while the status bit pointed to by the First Error Pointer in the Uncorrectable Error
Status Register remains set. After the software clears this status bit, a subsequent error
condition that sets any bit in the Uncorrectable Error Status Register will also cause the
Header Log Registers to be updated. The doublewords of the TLP header are stored in the Header
Log Registers with their bytes transposed. That is, the byte containing the Type/Format fields
of the header is stored at bit positions 31:24 of the Header Log Register 0.

Table 12-3013 PCIE_CORE_RP_I_HDR_LOG_0 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 011Ch

Figure 12-1536 PCIE_CORE_RP_I_HDR_LOG_0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HD0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3014 PCIE_CORE_RP_I_HDR_LOG_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	HD0	R	0h	First Dword of captured TLP header. STICKY.

3.5.3.49 PCIE_CORE_RP_I_HDR_LOG_1 Register (Offset = 120h) [reset = 0h]

PCIE_CORE_RP_I_HDR_LOG_1 is shown in Figure 12-1537 and described in Table 12-3016.

Return to the Summary Table.

This register contains the second Dword of the captured TLP header. The bytes are stored
in transposed order.

Table 12-3015 PCIE_CORE_RP_I_HDR_LOG_1 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0120h

Figure 12-1537 PCIE_CORE_RP_I_HDR_LOG_1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HD1
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3016 PCIE_CORE_RP_I_HDR_LOG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	HD1	R	0h	Second Dword of captured TLP header. STICKY.

3.5.3.50 PCIE_CORE_RP_I_HDR_LOG_2 Register (Offset = 124h) [reset = 0h]

PCIE_CORE_RP_I_HDR_LOG_2 is shown in Figure 12-1538 and described in Table 12-3018.

Return to the Summary Table.

This register contains the third Dword of the captured TLP header. The bytes are stored
in transposed order.

Table 12-3017 PCIE_CORE_RP_I_HDR_LOG_2 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0124h

Figure 12-1538 PCIE_CORE_RP_I_HDR_LOG_2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HD2
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3018 PCIE_CORE_RP_I_HDR_LOG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	HD2	R	0h	Third Dword of captured TLP header. STICKY.

3.5.3.51 PCIE_CORE_RP_I_HDR_LOG_3 Register (Offset = 128h) [reset = 0h]

PCIE_CORE_RP_I_HDR_LOG_3 is shown in Figure 12-1539 and described in Table 12-3020.

Return to the Summary Table.

If the captured TLP header is 4 Dwords long, this register contains its fourth Dword. If
the captured header is a 3-Dword header, this register is unused. The bytes of the Dword are
stored in this register in transposed order.

Table 12-3019 PCIE_CORE_RP_I_HDR_LOG_3 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0128h

Figure 12-1539 PCIE_CORE_RP_I_HDR_LOG_3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HD3
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3020 PCIE_CORE_RP_I_HDR_LOG_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	HD3	R	0h	Fourth Dword of captured TLP header. STICKY.

3.5.3.52 PCIE_CORE_RP_I_ROOT_ERR_CMD Register (Offset = 12Ch) [reset = 0h]

PCIE_CORE_RP_I_ROOT_ERR_CMD is shown in Figure 12-1540 and described in Table 12-3022.

Return to the Summary Table.

This register contains bits that control how the RC responds to errors reported by
remote devices.

Table 12-3021 PCIE_CORE_RP_I_ROOT_ERR_CMD Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 012Ch

Figure 12-1540 PCIE_CORE_RP_I_ROOT_ERR_CMD Register

31	30	29	28	27	26	25	24
R44
R-0h

23	22	21	20	19	18	17	16
R44
R-0h

15	14	13	12	11	10	9	8
R44
R-0h

7	6	5	4	3	2	1	0
R44					FERE	NFERE	CERE
R-0h					R/W-0h	R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3022 PCIE_CORE_RP_I_ROOT_ERR_CMD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	R44	R	0h	Reserved
2	FERE	R/W	0h	If this bit is set, the Controller will active its FATAL_ERROR_OUT output in response to an error message received from the link.
1	NFERE	R/W	0h	If this bit is set, the Controller will active its NON_FATAL_ERROR_OUT output in response to an error message received from the link.
0	CERE	R/W	0h	If this bit is set, the Controller will active its CORRECTABLE_ERROR_OUT output in response to an error message received from the link.

3.5.3.53 PCIE_CORE_RP_I_ROOT_ERR_STAT Register (Offset = 130h) [reset = 0h]

PCIE_CORE_RP_I_ROOT_ERR_STAT is shown in Figure 12-1541 and described in Table 12-3024.

Return to the Summary Table.

This register contains status information on error messages received from the link (that
is, errors reported by remote devices attached to this Root Complex).

Table 12-3023 PCIE_CORE_RP_I_ROOT_ERR_STAT Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0130h

Figure 12-1541 PCIE_CORE_RP_I_ROOT_ERR_STAT Register

31	30	29	28	27	26	25	24
R45
R-0h

23	22	21	20	19	18	17	16
R45
R-0h

15	14	13	12	11	10	9	8
R45
R-0h

7	6	5	4	3	2	1	0
R45	FEMR	NEMR	FUF	MEFNR	EFNR	MECR	ECR
R-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-3024 PCIE_CORE_RP_I_ROOT_ERR_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	R45	R	0h	Reserved
6	FEMR	R/W1C	0h	This bit, when set, indicates that the RC has received one or more Fatal error messages from the link. STICKY
5	NEMR	R/W1C	0h	This bit, when set, indicates that the RC has received one or more Non-Fatal error messages from the link. STICKY
4	FUF	R/W1C	0h	This bit, when set, indicates that the first Uncorrectable error message received was for a Fatal error. STICKY
3	MEFNR	R/W1C	0h	This bit is set when the RC receives either a Fatal or Non-Fatal error message from the link, and the ERR_FATAL/NONFATAL Received bit is already set. STICKY
2	EFNR	R/W1C	0h	This bit is set when the RC receives either a Fatal or Non-Fatal error message from the link. STICKY
1	MECR	R/W1C	0h	This bit is set when the RC receives a Correctable error message from the link, if the ERR_COR received bit is already set. STICKY
0	ECR	R/W1C	0h	This bit is set when the RC receives a Correctable error message from the link. STICKY

3.5.3.54 PCIE_CORE_RP_I_ERR_SRC_ID Register (Offset = 134h) [reset = 0h]

PCIE_CORE_RP_I_ERR_SRC_ID is shown in Figure 12-1542 and described in Table 12-3026.

Return to the Summary Table.

This register stores the Register IDs extracted from error messages received by the Root
Complex from the link.

Table 12-3025 PCIE_CORE_RP_I_ERR_SRC_ID Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0134h

Figure 12-1542 PCIE_CORE_RP_I_ERR_SRC_ID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EFNSI																ECSI
R-0h																R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3026 PCIE_CORE_RP_I_ERR_SRC_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	EFNSI	R	0h	This field captures and stores the Requester ID from an ERR_FATAL or ERROR_NONFATAL message received by the RC, if the ERR_FATAL or NONFATAL Received bit was not set at the time the message was received. STICKY
15-0	ECSI	R	0h	This field captures and stores the Requester ID from an ERR_COR message received by the RC, if the ERR_COR bit was not set at the time the message was received. STICKY

3.5.3.55 PCIE_CORE_RP_I_TLP_PRE_LOG_0 Register (Offset = 138h) [reset = 0h]

PCIE_CORE_RP_I_TLP_PRE_LOG_0 is shown in Figure 12-1543 and described in Table 12-3028.

Return to the Summary Table.

First TLP Prefix (if present) associated with the TLP whose header is in the Header Log Register.
The bytes are in transposed order.

Table 12-3027 PCIE_CORE_RP_I_TLP_PRE_LOG_0 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0138h

Figure 12-1543 PCIE_CORE_RP_I_TLP_PRE_LOG_0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HD1
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3028 PCIE_CORE_RP_I_TLP_PRE_LOG_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	HD1	R	0h	First TLP Prefix of captured TLP STICKY.

3.5.3.56 PCIE_CORE_RP_I_DEV_SER_NUM_CAP_HDR Register (Offset = 150h) [reset = 30010003h]

PCIE_CORE_RP_I_DEV_SER_NUM_CAP_HDR is shown in Figure 12-1544 and described in Table 12-3030.

Return to the Summary Table.

This register contains the PCI Express Extended Capability ID for Device Serial Number
Capability, the capability version, and the pointer to the next capability structure.

Table 12-3029 PCIE_CORE_RP_I_DEV_SER_NUM_CAP_HDR Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0150h

Figure 12-1544 PCIE_CORE_RP_I_DEV_SER_NUM_CAP_HDR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SNNCO												DSNCV
R-300h												R-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PECID
R-3h

LEGEND: R = Read Only; -n = value after reset

Table 12-3030 PCIE_CORE_RP_I_DEV_SER_NUM_CAP_HDR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	SNNCO	R	300h	Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16	DSNCV	R	1h	Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1, but can be modified from the local management bus by writing into Function 0 from the local management bus.
15-0	PECID	R	3h	This field is hardwired to the Capability ID assigned by PCI SIG to the PCI Express Device Serial Number Capability [0001 hex].

3.5.3.57 PCIE_CORE_RP_I_DEV_SER_NUM_0 Register (Offset = 154h) [reset = 0h]

PCIE_CORE_RP_I_DEV_SER_NUM_0 is shown in Figure 12-1545 and described in Table 12-3032.

Return to the Summary Table.

This read-only register stored the first 32 bits of the device's serial number.

Table 12-3031 PCIE_CORE_RP_I_DEV_SER_NUM_0 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0154h

Figure 12-1545 PCIE_CORE_RP_I_DEV_SER_NUM_0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DSND0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3032 PCIE_CORE_RP_I_DEV_SER_NUM_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DSND0	R	0h	This field contains the first 32 bits of the device's serial number. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

3.5.3.58 PCIE_CORE_RP_I_DEV_SER_NUM_1 Register (Offset = 158h) [reset = 0h]

PCIE_CORE_RP_I_DEV_SER_NUM_1 is shown in Figure 12-1546 and described in Table 12-3034.

Return to the Summary Table.

This read-only register stored the last 32 bits of the device's serial number.

Table 12-3033 PCIE_CORE_RP_I_DEV_SER_NUM_1 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0158h

Figure 12-1546 PCIE_CORE_RP_I_DEV_SER_NUM_1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DSND1
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3034 PCIE_CORE_RP_I_DEV_SER_NUM_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DSND1	R	0h	This field contains the last 32 bits of the device's serial number. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

3.5.3.59 PCIE_CORE_RP_I_SEC_PCIE_CAP_HDR_REG Register (Offset = 300h) [reset = 4C010019h]

PCIE_CORE_RP_I_SEC_PCIE_CAP_HDR_REG is shown in Figure 12-1547 and described in Table 12-3036.

Return to the Summary Table.

This register contains the PCI Express Extended Capability ID for the Secondary PCI
Express Extended Capability, its capability version, and the pointer to the next capability
structure. This register is implemented only in the configuration space of PF 0 or RC.

Table 12-3035 PCIE_CORE_RP_I_SEC_PCIE_CAP_HDR_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0300h

Figure 12-1547 PCIE_CORE_RP_I_SEC_PCIE_CAP_HDR_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NCO												CV				PECI
R-4C0h												R-1h				R-19h

LEGEND: R = Read Only; -n = value after reset

Table 12-3036 PCIE_CORE_RP_I_SEC_PCIE_CAP_HDR_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	NCO	R	4C0h	Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16	CV	R	1h	Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1 , but can be modified independently for each PF from [ the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write] .
15-0	PECI	R	19h	This field is hardwired to the Capability ID assigned by PCI SIG to the Secondary PCI Express Capability

3.5.3.60 PCIE_CORE_RP_I_LINK_CONTROL3 Register (Offset = 304h) [reset = 0h]

PCIE_CORE_RP_I_LINK_CONTROL3 is shown in Figure 12-1548 and described in Table 12-3038.

Return to the Summary Table.

This register is part of the Secondary PCI Express Extended Capability Structure.
It contains bits to control the link equalization procedure at 8 GT/s or 16 GT/s speed.

Table 12-3037 PCIE_CORE_RP_I_LINK_CONTROL3 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0304h

Figure 12-1548 PCIE_CORE_RP_I_LINK_CONTROL3 Register

31	30	29	28	27	26	25	24
R2
R-0h

23	22	21	20	19	18	17	16
R2
R-0h

15	14	13	12	11	10	9	8
R2			ELSOSGV				R1
R-0h			R/W-0h				R-0h

7	6	5	4	3	2	1	0
R1						LERIE	PE
R-0h						R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3038 PCIE_CORE_RP_I_LINK_CONTROL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	R2	R	0h	Reserved
12-9	ELSOSGV	R/W	0h	When the Link is in L0 and the bit in this field corresponding to the current Link speed is Set, SKP Ordered Sets are scheduled at the rate defined for SRNS, overriding the rate required based on the clock tolerance architecture.
8-2	R1	R	0h	Reserved
1	LERIE	R/W	0h	This bit enables the activation of the LOCAL_INTERRUPT_OUT output of the Controller when the Link Equalization Request bit in the Link Status 2 Register rr the Link Equalization Request 16.0 GT/s in the 16GTs Status Register is set.
0	PE	R/W	0h	The state of this bit determines whether the Controller performs link equalization when the link is retrained by the local software. If this bit is set to 1 when the local software sets the Link Retrain bit in the Link Control Register, and the target link speed is 8 GT/s or 16 GT/s, the LTSSM of the Controller will go through the link equalization states during the retraining.

3.5.3.61 PCIE_CORE_RP_I_LANE_ERROR_STATUS Register (Offset = 308h) [reset = 0h]

PCIE_CORE_RP_I_LANE_ERROR_STATUS is shown in Figure 12-1549 and described in Table 12-3040.

Return to the Summary Table.

This register contains one bit per lane indicating the physical-layer error status of
the corresponding lane. A 1 indicates that a physical-layer error was detected by the Controller in
the corresponding lane. The error can be cleared by writing a 1 into the bit position, either
through a Configuration Write transaction from the link or from the local management
APB bus.

Table 12-3039 PCIE_CORE_RP_I_LANE_ERROR_STATUS Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0308h

Figure 12-1549 PCIE_CORE_RP_I_LANE_ERROR_STATUS Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
R0
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R0												LES
R-0h												R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-3040 PCIE_CORE_RP_I_LANE_ERROR_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	R0	R	0h	N/A
3-0	LES	R/W1C	0h	Each of these bits indicates the error status for the corresponding lane. STICKY.

3.5.3.62 PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_0 Register (Offset = 30Ch) [reset = 7F7F7F7Fh]

PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_0 is shown in Figure 12-1550 and described in Table 12-3042.

Return to the Summary Table.

This register contains the 8.0GT/s Transmitter Preset and the Receiver Preset Hint values for
lanes 0 and 1, for use during the Link Equalization procedure.

Table 12-3041 PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_0 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 030Ch

Figure 12-1550 PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_0 Register

31	30	29	28	27	26	25	24
R3	UPRPH1			UPTP1
R-0h	R-7h			R-Fh

23	22	21	20	19	18	17	16
R2_1	DNRPH1			DNTP1
R-0h	R-7h			R-Fh

15	14	13	12	11	10	9	8
R1	UPRPH0			UPTP0
R-0h	R-7h			R-Fh

7	6	5	4	3	2	1	0
R0_1	DNRPH0			DNTP0
R-0h	R-7h			R-Fh

LEGEND: R = Read Only; -n = value after reset

Table 12-3042 PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	R3	R	0h	Reserved
30-28	UPRPH1	R	7h	8.0GT/s Value sent by the Controller as the Receiver Preset Hint for the remote receiver associated with Lane 1. The remote node may use this value to adapt its receiver at the start of the link equalization procedure.
27-24	UPTP1	R	Fh	8.0GT/s Value sent by the Controller as the Transmitter Preset for the remote transmitter associated with Lane 1. The remote node uses this value to set up its transmitter at the start of the link equalization procedure.
23	R2_1	R	0h	Reserved
22-20	DNRPH1	R	7h	8.0GT/s Receiver Preset Hint value to be used for the local receiver associated with Lane 1. The Controller uses this value to set up the receiver attached to Lane 1
19-16	DNTP1	R	Fh	8.0GT/s Transmitter Preset value to be used for the local transmitter associated with Lane 1. The Controller uses this value to set up the Lane 1 transmitter during link equalization.
15	R1	R	0h	Reserved
14-12	UPRPH0	R	7h	8.0GT/s Value sent by the Controller as the Receiver Preset Hint for the remote receiver associated with Lane 0. The remote node may use this value to adapt its receiver at the start of the link equalization procedure.
11-8	UPTP0	R	Fh	8.0GT/s Value sent by the Controller as the Transmitter Preset for the remote transmitter associated with Lane 0. The remote node uses this value to set up its transmitter at the start of the link equalization procedure.
7	R0_1	R	0h	Reserved
6-4	DNRPH0	R	7h	8.0GT/s Receiver Preset Hint value to be used for the local receiver associated with Lane 0. The Controller uses this value to set up the receiver attached to Lane 0
3-0	DNTP0	R	Fh	8.0GT/s Transmitter Preset value to be used for the local transmitter associated with Lane 0. The Controller uses this value to set up the Lane 0 transmitter during link equalization.

3.5.3.63 PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_1 Register (Offset = 310h) [reset = 7F7F7F7Fh]

PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_1 is shown in Figure 12-1551 and described in Table 12-3044.

Return to the Summary Table.

This register contains the 8.0GT/s Transmitter Preset and the Receiver Preset Hint values for
lanes 2 and 3, for use during the Link Equalization procedure.

Table 12-3043 PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_1 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0310h

Figure 12-1551 PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_1 Register

31	30	29	28	27	26	25	24
R3	UPRPH1			UPTP1
R-0h	R-7h			R-Fh

23	22	21	20	19	18	17	16
R2_1	DNRPH1			DNTP1
R-0h	R-7h			R-Fh

15	14	13	12	11	10	9	8
R1	UPRPH0			UPTP0
R-0h	R-7h			R-Fh

7	6	5	4	3	2	1	0
R0_1	DNRPH0			DNTP0
R-0h	R-7h			R-Fh

Table 12-3044 PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	R3	R	0h	Reserved
30-28	UPRPH1	R	7h	8.0GT/s Value sent by the Controller as the Receiver Preset Hint for the remote receiver associated with Lane 3. The remote node may use this value to adapt its receiver at the start of the link equalization procedure.
27-24	UPTP1	R	Fh	8.0GT/s Value sent by the Controller as the Transmitter Preset for the remote transmitter associated with Lane 3. The remote node uses this value to set up its transmitter at the start of the link equalization procedure.
23	R2_1	R	0h	Reserved
22-20	DNRPH1	R	7h	8.0GT/s Receiver Preset Hint value to be used for the local receiver associated with Lane 3. The Controller uses this value to set up the receiver attached to Lane 3
19-16	DNTP1	R	Fh	8.0GT/s Transmitter Preset value to be used for the local transmitter associated with Lane 3. The Controller uses this value to set up the Lane 3 transmitter during link equalization.
15	R1	R	0h	Reserved
14-12	UPRPH0	R	7h	8.0GT/s Value sent by the Controller as the Receiver Preset Hint for the remote receiver associated with Lane 2. The remote node may use this value to adapt its receiver at the start of the link equalization procedure.
11-8	UPTP0	R	Fh	8.0GT/s Value sent by the Controller as the Transmitter Preset for the remote transmitter associated with Lane 2. The remote node uses this value to set up its transmitter at the start of the link equalization procedure.
7	R0_1	R	0h	Reserved
6-4	DNRPH0	R	7h	8.0GT/s Receiver Preset Hint value to be used for the local receiver associated with Lane 2. The Controller uses this value to set up the receiver attached to Lane 2
3-0	DNTP0	R	Fh	8.0GT/s Transmitter Preset value to be used for the local transmitter associated with Lane 2. The Controller uses this value to set up the Lane 2 transmitter during link equalization.

3.5.3.64 PCIE_CORE_RP_I_VC_ENH_CAP_HEADER_REG Register (Offset = 4C0h) [reset = 5C010002h]

PCIE_CORE_RP_I_VC_ENH_CAP_HEADER_REG is shown in Figure 12-1552 and described in Table 12-3046.

Return to the Summary Table.

This is the first register in the Virtual Channel Capability Structure. The VC Capability is present only in
the configuration space of Physical Function 0. This register contains the PCI Express Extended
Capability ID, the capability version, and the pointer to the next capability structure.

Table 12-3045 PCIE_CORE_RP_I_VC_ENH_CAP_HEADER_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04C0h

Figure 12-1552 PCIE_CORE_RP_I_VC_ENH_CAP_HEADER_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NCO												CV				PECID
R-5C0h												R-1h				R-2h

LEGEND: R = Read Only; -n = value after reset

Table 12-3046 PCIE_CORE_RP_I_VC_ENH_CAP_HEADER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	NCO	R	5C0h	Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16	CV	R	1h	Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1, but can be modified independently for each PF from the local management bus.
15-0	PECID	R	2h	This field is hardwired to the Capability ID assigned by PCI SIG to the VC Capability.

3.5.3.65 PCIE_CORE_RP_I_PORT_VC_CAP_REG_1 Register (Offset = 4C4h) [reset = X]

PCIE_CORE_RP_I_PORT_VC_CAP_REG_1 is shown in Figure 12-1553 and described in Table 12-3048.

Return to the Summary Table.

This register has fields that describe the capabilities of the device with respect to the virtual channels.

Table 12-3047 PCIE_CORE_RP_I_PORT_VC_CAP_REG_1 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04C4h

Figure 12-1553 PCIE_CORE_RP_I_PORT_VC_CAP_REG_1 Register

31	30	29	28	27	26	25	24
R0
R-0h

23	22	21	20	19	18	17	16
R0
R-0h

15	14	13	12	11	10	9	8
R0
R-0h

7	6	5	4	3	2	1	0
R0				RESERVED	EVC
R-0h				R-X	R-3h

LEGEND: R = Read Only; -n = value after reset

Table 12-3048 PCIE_CORE_RP_I_PORT_VC_CAP_REG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	R0	R	0h	N/A
3	RESERVED	R	X
2-0	EVC	R	3h	N/A

3.5.3.66 PCIE_CORE_RP_I_PORT_VC_CAP_REG_2 Register (Offset = 4C8h) [reset = 0h]

PCIE_CORE_RP_I_PORT_VC_CAP_REG_2 is shown in Figure 12-1554 and described in Table 12-3050.

Return to the Summary Table.

This register has fields that describe the capabilities of the device with respect to the virtual channels.
This register is not implemented. A read from this location returns all zeroes.

Table 12-3049 PCIE_CORE_RP_I_PORT_VC_CAP_REG_2 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04C8h

Figure 12-1554 PCIE_CORE_RP_I_PORT_VC_CAP_REG_2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R1
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3050 PCIE_CORE_RP_I_PORT_VC_CAP_REG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	R1	R	0h	N/A

3.5.3.67 PCIE_CORE_RP_I_PORT_VC_CTRL_STS_REG Register (Offset = 4CCh) [reset = 0h]

PCIE_CORE_RP_I_PORT_VC_CTRL_STS_REG is shown in Figure 12-1555 and described in Table 12-3052.

Return to the Summary Table.

This location contains the 16-bit VC Control Register and the 16-bit VC Status Register. These registers
are not implemented. A read from this location returns all zeroes.

Table 12-3051 PCIE_CORE_RP_I_PORT_VC_CTRL_STS_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04CCh

Figure 12-1555 PCIE_CORE_RP_I_PORT_VC_CTRL_STS_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R2
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3052 PCIE_CORE_RP_I_PORT_VC_CTRL_STS_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	R2	R	0h	N/A

3.5.3.68 PCIE_CORE_RP_I_VC_RES_CAP_REG_0 Register (Offset = 4D0h) [reset = 0h]

PCIE_CORE_RP_I_VC_RES_CAP_REG_0 is shown in Figure 12-1556 and described in Table 12-3054.

Return to the Summary Table.

This register describes the capabilities associated with VC 0.

Table 12-3053 PCIE_CORE_RP_I_VC_RES_CAP_REG_0 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04D0h

Figure 12-1556 PCIE_CORE_RP_I_VC_RES_CAP_REG_0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
R3
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RST	R1
R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3054 PCIE_CORE_RP_I_VC_RES_CAP_REG_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	R3	R	0h	N/A
15	RST	R	0h	N/A
14-0	R1	R	0h	N/A

3.5.3.69 PCIE_CORE_RP_I_VC_RES_CTRL_REG_0 Register (Offset = 4D4h) [reset = X]

PCIE_CORE_RP_I_VC_RES_CTRL_REG_0 is shown in Figure 12-1557 and described in Table 12-3056.

Return to the Summary Table.

This register contains bits to configure VC 0.

Table 12-3055 PCIE_CORE_RP_I_VC_RES_CTRL_REG_0 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04D4h

Figure 12-1557 PCIE_CORE_RP_I_VC_RES_CTRL_REG_0 Register

31	30	29	28	27	26	25	24
VCEN	R6				VCI
R-1h	R-0h				R-0h

23	22	21	20	19	18	17	16
R5				PARS			LPAT
R-0h				R-0h			R-0h

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
TVM							TVM0
R/W-7Fh							R-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3056 PCIE_CORE_RP_I_VC_RES_CTRL_REG_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	VCEN	R	1h	Software uses this bit to enable the VC. For VC0 this bit is hardwired to 1.
30-27	R6	R	0h	N/A
26-24	VCI	R	0h	VC ID assigned to VC0. For the VC0, this field is read-only and it is hardwired to 00b. For non VC0 case, it is allowed to use any VC-ID. This VC-ID has to be unique across all VCs. This must not be same as VC0's ID[VC0 ID=0].
23-20	R5	R	0h	N/A
19-17	PARS	R	0h	Configures the VC to use a specific port arbitration scheme. This field is not implemented, and hardwired to 0.
16	LPAT	R	0h	Updates the port arbitration logic from the Port Arbitration Table for VC 0. This bit is not implemented, and hardwired to 0.
15-8	RESERVED	R/W	X
7-1	TVM	R/W	7Fh	Indicates the TCs that are mapped to this VC. When bit 0 of this field is set, it indicates that TC 0 is mapped to VC 0.By default, all TCs are mapped to VC 0.
0	TVM0	R	1h	Indicates the TC0 always mapped to VC0.

3.5.3.70 PCIE_CORE_RP_I_VC_RES_STS_REG_0 Register (Offset = 4D8h) [reset = X]

PCIE_CORE_RP_I_VC_RES_STS_REG_0 is shown in Figure 12-1558 and described in Table 12-3058.

Return to the Summary Table.

This register contains status bits associated with VC 0.

Table 12-3057 PCIE_CORE_RP_I_VC_RES_STS_REG_0 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04D8h

Figure 12-1558 PCIE_CORE_RP_I_VC_RES_STS_REG_0 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
RESERVED						VCNP	PATS
R-X						R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3058 PCIE_CORE_RP_I_VC_RES_STS_REG_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	X
1	VCNP	R	0h	This indicates whether the Virtual Channel negotiation is in pending state. The value of this bit is defined only when the link is in the DL_Active state and Virtual Channel is enabled. When this bit is set by hardware, it indicates that the VC resource has not completed the process of negotiation. This bit is cleared by hardware after the VC negotiation is complete.
0	PATS	R	0h	This is not implemented and hardwired to 0.

3.5.3.71 PCIE_CORE_RP_I_VC_RES_CAP_REG_1 Register (Offset = 4DCh) [reset = 0h]

PCIE_CORE_RP_I_VC_RES_CAP_REG_1 is shown in Figure 12-1559 and described in Table 12-3060.

Return to the Summary Table.

This register describes the capabilities associated with VC 1.

Table 12-3059 PCIE_CORE_RP_I_VC_RES_CAP_REG_1 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04DCh

Figure 12-1559 PCIE_CORE_RP_I_VC_RES_CAP_REG_1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
R3
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RST	R1
R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3060 PCIE_CORE_RP_I_VC_RES_CAP_REG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	R3	R	0h	N/A
15	RST	R	0h	N/A
14-0	R1	R	0h	N/A

3.5.3.72 PCIE_CORE_RP_I_VC_RES_CTRL_REG_1 Register (Offset = 4E0h) [reset = X]

PCIE_CORE_RP_I_VC_RES_CTRL_REG_1 is shown in Figure 12-1560 and described in Table 12-3062.

Return to the Summary Table.

This register contains bits to configure VC 1.

Table 12-3061 PCIE_CORE_RP_I_VC_RES_CTRL_REG_1 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04E0h

Figure 12-1560 PCIE_CORE_RP_I_VC_RES_CTRL_REG_1 Register

31	30	29	28	27	26	25	24
VCEN	R6				VCI
R/W-0h	R-0h				R/W-1h

23	22	21	20	19	18	17	16
R5				PARS			LPAT
R-0h				R-0h			R-0h

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
TVM							TVM0
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3062 PCIE_CORE_RP_I_VC_RES_CTRL_REG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	VCEN	R/W	0h	Software uses this bit to enable the VC. For VC0 this bit is hardwired to 1.
30-27	R6	R	0h	N/A
26-24	VCI	R/W	1h	VC ID assigned to VC1. For the VC0, this field is read-only and it is hardwired to 00b. For non VC0 case, it is allowed to use any VC-ID. This VC-ID has to be unique across all VCs. This must not be same as VC0's ID[VC0 ID=0].
23-20	R5	R	0h	N/A
19-17	PARS	R	0h	Configures the VC to use a specific port arbitration scheme. This field is not implemented, and hardwired to 0.
16	LPAT	R	0h	Updates the port arbitration logic from the Port Arbitration Table for VC 1. This bit is not implemented, and hardwired to 0.
15-8	RESERVED	R/W	X
7-1	TVM	R/W	0h	Indicates the TCs that are mapped to this VC. When bit 1 of this field is set, it indicates that TC 1 is mapped to VC 1.By default, all TCs are mapped to VC 0.
0	TVM0	R	0h	Indicates the TC0 always mapped to VC0.

3.5.3.73 PCIE_CORE_RP_I_VC_RES_STS_REG_1 Register (Offset = 4E4h) [reset = X]

PCIE_CORE_RP_I_VC_RES_STS_REG_1 is shown in Figure 12-1561 and described in Table 12-3064.

Return to the Summary Table.

This register contains status bits associated with VC 1.

Table 12-3063 PCIE_CORE_RP_I_VC_RES_STS_REG_1 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04E4h

Figure 12-1561 PCIE_CORE_RP_I_VC_RES_STS_REG_1 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
RESERVED						VCNP	PATS
R-X						R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3064 PCIE_CORE_RP_I_VC_RES_STS_REG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	X
1	VCNP	R	0h	This indicates whether the Virtual Channel negotiation is in pending state. The value of this bit is defined only when the link is in the DL_Active state and Virtual Channel is enabled. When this bit is set by hardware, it indicates that the VC resource has not completed the process of negotiation. This bit is cleared by hardware after the VC negotiation is complete.
0	PATS	R	0h	This is not implemented and hardwired to 0.

3.5.3.74 PCIE_CORE_RP_I_VC_RES_CAP_REG_2 Register (Offset = 4E8h) [reset = 0h]

PCIE_CORE_RP_I_VC_RES_CAP_REG_2 is shown in Figure 12-1562 and described in Table 12-3066.

Return to the Summary Table.

This register describes the capabilities associated with VC 2.

Table 12-3065 PCIE_CORE_RP_I_VC_RES_CAP_REG_2 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04E8h

Figure 12-1562 PCIE_CORE_RP_I_VC_RES_CAP_REG_2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
R3
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RST	R1
R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3066 PCIE_CORE_RP_I_VC_RES_CAP_REG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	R3	R	0h	N/A
15	RST	R	0h	N/A
14-0	R1	R	0h	N/A

3.5.3.75 PCIE_CORE_RP_I_VC_RES_CTRL_REG_2 Register (Offset = 4ECh) [reset = X]

PCIE_CORE_RP_I_VC_RES_CTRL_REG_2 is shown in Figure 12-1563 and described in Table 12-3068.

Return to the Summary Table.

This register contains bits to configure VC 2.

Table 12-3067 PCIE_CORE_RP_I_VC_RES_CTRL_REG_2 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04ECh

Figure 12-1563 PCIE_CORE_RP_I_VC_RES_CTRL_REG_2 Register

31	30	29	28	27	26	25	24
VCEN	R6				VCI
R/W-0h	R-0h				R/W-2h

23	22	21	20	19	18	17	16
R5				PARS			LPAT
R-0h				R-0h			R-0h

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
TVM							TVM0
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3068 PCIE_CORE_RP_I_VC_RES_CTRL_REG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	VCEN	R/W	0h	Software uses this bit to enable the VC. For VC0 this bit is hardwired to 1.
30-27	R6	R	0h	N/A
26-24	VCI	R/W	2h	VC ID assigned to VC2. For the VC0, this field is read-only and it is hardwired to 00b. For non VC0 case, it is allowed to use any VC-ID. This VC-ID has to be unique across all VCs. This must not be same as VC0's ID[VC0 ID=0].
23-20	R5	R	0h	N/A
19-17	PARS	R	0h	Configures the VC to use a specific port arbitration scheme. This field is not implemented, and hardwired to 0.
16	LPAT	R	0h	Updates the port arbitration logic from the Port Arbitration Table for VC 2. This bit is not implemented, and hardwired to 0.
15-8	RESERVED	R/W	X
7-1	TVM	R/W	0h	Indicates the TCs that are mapped to this VC. When bit 2 of this field is set, it indicates that TC 2 is mapped to VC 2.By default, all TCs are mapped to VC 0.
0	TVM0	R	0h	Indicates the TC0 always mapped to VC0.

3.5.3.76 PCIE_CORE_RP_I_VC_RES_STS_REG_2 Register (Offset = 4F0h) [reset = X]

PCIE_CORE_RP_I_VC_RES_STS_REG_2 is shown in Figure 12-1564 and described in Table 12-3070.

Return to the Summary Table.

This register contains status bits associated with VC 2.

Table 12-3069 PCIE_CORE_RP_I_VC_RES_STS_REG_2 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04F0h

Figure 12-1564 PCIE_CORE_RP_I_VC_RES_STS_REG_2 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
RESERVED						VCNP	PATS
R-X						R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3070 PCIE_CORE_RP_I_VC_RES_STS_REG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	X
1	VCNP	R	0h	This indicates whether the Virtual Channel negotiation is in pending state. The value of this bit is defined only when the link is in the DL_Active state and Virtual Channel is enabled. When this bit is set by hardware, it indicates that the VC resource has not completed the process of negotiation. This bit is cleared by hardware after the VC negotiation is complete.
0	PATS	R	0h	This is not implemented and hardwired to 0.

3.5.3.77 PCIE_CORE_RP_I_VC_RES_CAP_REG_3 Register (Offset = 4F4h) [reset = 0h]

PCIE_CORE_RP_I_VC_RES_CAP_REG_3 is shown in Figure 12-1565 and described in Table 12-3072.

Return to the Summary Table.

This register describes the capabilities associated with VC 3.

Table 12-3071 PCIE_CORE_RP_I_VC_RES_CAP_REG_3 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04F4h

Figure 12-1565 PCIE_CORE_RP_I_VC_RES_CAP_REG_3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
R3
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RST	R1
R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3072 PCIE_CORE_RP_I_VC_RES_CAP_REG_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	R3	R	0h	N/A
15	RST	R	0h	N/A
14-0	R1	R	0h	N/A

3.5.3.78 PCIE_CORE_RP_I_VC_RES_CTRL_REG_3 Register (Offset = 4F8h) [reset = X]

PCIE_CORE_RP_I_VC_RES_CTRL_REG_3 is shown in Figure 12-1566 and described in Table 12-3074.

Return to the Summary Table.

This register contains bits to configure VC 3.

Table 12-3073 PCIE_CORE_RP_I_VC_RES_CTRL_REG_3 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04F8h

Figure 12-1566 PCIE_CORE_RP_I_VC_RES_CTRL_REG_3 Register

31	30	29	28	27	26	25	24
VCEN	R6				VCI
R/W-0h	R-0h				R/W-3h

23	22	21	20	19	18	17	16
R5				PARS			LPAT
R-0h				R-0h			R-0h

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
TVM							TVM0
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3074 PCIE_CORE_RP_I_VC_RES_CTRL_REG_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	VCEN	R/W	0h	Software uses this bit to enable the VC. For VC0 this bit is hardwired to 1.
30-27	R6	R	0h	N/A
26-24	VCI	R/W	3h	VC ID assigned to VC3. For the VC0, this field is read-only and it is hardwired to 00b. For non VC0 case, it is allowed to use any VC-ID. This VC-ID has to be unique across all VCs. This must not be same as VC0's ID[VC0 ID=0].
23-20	R5	R	0h	N/A
19-17	PARS	R	0h	Configures the VC to use a specific port arbitration scheme. This field is not implemented, and hardwired to 0.
16	LPAT	R	0h	Updates the port arbitration logic from the Port Arbitration Table for VC 3. This bit is not implemented, and hardwired to 0.
15-8	RESERVED	R/W	X
7-1	TVM	R/W	0h	Indicates the TCs that are mapped to this VC. When bit 3 of this field is set, it indicates that TC 3 is mapped to VC 3.By default, all TCs are mapped to VC 0.
0	TVM0	R	0h	Indicates the TC0 always mapped to VC0.

3.5.3.79 PCIE_CORE_RP_I_VC_RES_STS_REG_3 Register (Offset = 4FCh) [reset = X]

PCIE_CORE_RP_I_VC_RES_STS_REG_3 is shown in Figure 12-1567 and described in Table 12-3076.

Return to the Summary Table.

This register contains status bits associated with VC 3.

Table 12-3075 PCIE_CORE_RP_I_VC_RES_STS_REG_3 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 04FCh

Figure 12-1567 PCIE_CORE_RP_I_VC_RES_STS_REG_3 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
RESERVED						VCNP	PATS
R-X						R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3076 PCIE_CORE_RP_I_VC_RES_STS_REG_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	X
1	VCNP	R	0h	This indicates whether the Virtual Channel negotiation is in pending state. The value of this bit is defined only when the link is in the DL_Active state and Virtual Channel is enabled. When this bit is set by hardware, it indicates that the VC resource has not completed the process of negotiation. This bit is cleared by hardware after the VC negotiation is complete.
0	PATS	R	0h	This is not implemented and hardwired to 0.

3.5.3.80 PCIE_CORE_RP_I_L1_PM_EXT_CAP_HDR Register (Offset = 900h) [reset = 9101001Eh]

PCIE_CORE_RP_I_L1_PM_EXT_CAP_HDR is shown in Figure 12-1568 and described in Table 12-3078.

Return to the Summary Table.

L1 PM Substates Extended Capability Header Register.

Table 12-3077 PCIE_CORE_RP_I_L1_PM_EXT_CAP_HDR Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0900h

Figure 12-1568 PCIE_CORE_RP_I_L1_PM_EXT_CAP_HDR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NCO												CV				PECID
R-910h												R-1h				R-1Eh

LEGEND: R = Read Only; -n = value after reset

Table 12-3078 PCIE_CORE_RP_I_L1_PM_EXT_CAP_HDR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	NCO	R	910h	Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19-16	CV	R	1h	Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1, but can be modified from the local management bus.
15-0	PECID	R	1Eh	This field is hardwired to the Capability ID assigned by PCI SIG to the L1 PM Substates Extended Capability Structure [001E hex].

3.5.3.81 PCIE_CORE_RP_I_L1_PM_CAP Register (Offset = 904h) [reset = X]

PCIE_CORE_RP_I_L1_PM_CAP is shown in Figure 12-1569 and described in Table 12-3080.

Return to the Summary Table.

This register advertises the L1 PM Substates Capabilities.

Table 12-3079 PCIE_CORE_RP_I_L1_PM_CAP Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0904h

Figure 12-1569 PCIE_CORE_RP_I_L1_PM_CAP Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
R0					RESERVED	L1PRTPVRONSCALE
R-Dh					R-X	R-0h

15	14	13	12	11	10	9	8
L1PRTCMMDRESTRTIME
R-FFh

7	6	5	4	3	2	1	0
RESERVED			L1PMSUPP	L1ASPML11SUPP	L1ASPML12SUPP	L1PML11SUPP	L1PML12SUPP
R-X			R-1h	R-1h	R-1h	R-1h	R-1h

LEGEND: R = Read Only; -n = value after reset

Table 12-3080 PCIE_CORE_RP_I_L1_PM_CAP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X
23-19	R0	R	Dh	Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time [in us] that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface. The value of Port T_POWER_ON is calculated by multiplying the value in this field by the scale value in the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register. T Power On is the minimum amount of time that each component must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface. This is to ensure no device is ever actively driving into an unpowered component.
18	RESERVED	R	X
17-16	L1PRTPVRONSCALE	R	0h	Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of Values 00b = 2us 01b = 10us 10b = 100us 11b = Reserved Default value is 00.
15-8	L1PRTCMMDRESTRTIME	R	FFh	Time [in us] required for this Port to re-establish common mode during exit from PM or ASPM L1.2 substate.
7-5	RESERVED	R	X
4	L1PMSUPP	R	1h	When Set this bit indicates that this Port supports L1 PM Substates.
3	L1ASPML11SUPP	R	1h	When Set this bit indicates that ASPM L1.1 is supported.
2	L1ASPML12SUPP	R	1h	When Set this bit indicates that ASPM L1.2 is supported.
1	L1PML11SUPP	R	1h	When Set this bit indicates that PCI-PM L1.1 is supported.
0	L1PML12SUPP	R	1h	When Set this bit indicates that PCI-PM L1.2 is supported.

3.5.3.82 PCIE_CORE_RP_I_L1_PM_CTRL_1 Register (Offset = 908h) [reset = X]

PCIE_CORE_RP_I_L1_PM_CTRL_1 is shown in Figure 12-1570 and described in Table 12-3082.

Return to the Summary Table.

L1 PM Substates Control 1 Register

Table 12-3081 PCIE_CORE_RP_I_L1_PM_CTRL_1 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0908h

Figure 12-1570 PCIE_CORE_RP_I_L1_PM_CTRL_1 Register

31	30	29	28	27	26	25	24
L1THRSHLDSC			RESERVED			L1THRSHLDVAL
R/W-0h			R/W-X			R/W-0h

23	22	21	20	19	18	17	16
L1THRSHLDVAL
R/W-0h

15	14	13	12	11	10	9	8
L1CMMDRESTRTIME
R/W-0h

7	6	5	4	3	2	1	0
RESERVED				L1ASPML11EN	L1ASPML12EN	L1PML11EN	L1PML12EN
R/W-X				R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3082 PCIE_CORE_RP_I_L1_PM_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	L1THRSHLDSC	R/W	0h	This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value. 000 - Value times 1 ns 001 - Value times 32 ns 010 - Value times 1024 ns 011 - Value times 32,768 ns 100 - Value times 1,048,576 ns 101 - Value times 33,554,422ns 110- 111 - Not permitted
28-26	RESERVED	R/W	X
25-16	L1THRSHLDVAL	R/W	0h	Along with the LTR_L1.2_THRESHOLD_Scale, this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 [if enabled] or L1.2 [if enabled].
15-8	L1CMMDRESTRTIME	R/W	0h	Sets value of TCOMMONMODE [in us], which must be used by the Downstream Port for timing the re-establishment of common mode. This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear. This field is reserved since both PCI-PM L1.2 and ASPM L1.2 are Not Supported in this configuration of the Controller.
7-4	RESERVED	R/W	X
3	L1ASPML11EN	R/W	0h	When Set this bit enables ASPM L1.1.
2	L1ASPML12EN	R/W	0h	When Set this bit enables ASPM L1.2.
1	L1PML11EN	R/W	0h	When Set this bit enables PCI-PM L1.1.
0	L1PML12EN	R/W	0h	When Set this bit enables PCI-PM L1.2.

3.5.3.83 PCIE_CORE_RP_I_L1_PM_CTRL_2 Register (Offset = 90Ch) [reset = X]

PCIE_CORE_RP_I_L1_PM_CTRL_2 is shown in Figure 12-1571 and described in Table 12-3084.

Return to the Summary Table.

L1 PM Substates Control 2 Register

Table 12-3083 PCIE_CORE_RP_I_L1_PM_CTRL_2 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 090Ch

Figure 12-1571 PCIE_CORE_RP_I_L1_PM_CTRL_2 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
L1PWRONVAL					RESERVED	L1PWRONSC
R/W-5h					R/W-X	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 12-3084 PCIE_CORE_RP_I_L1_PM_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R/W	X
7-3	L1PWRONVAL	R/W	5h	Along with the T_POWER_ON Scale sets the minimum amount of time [in us] that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface. T_POWER_ON is calculated by multiplying the value in this field by the value in the T_POWER_ON Scale field.
2	RESERVED	R/W	X
1-0	L1PWRONSC	R/W	0h	Specifies the scale used for T_POWER_ON Value. Range of Values 00b = 2us 01b = 10us 10b = 100us 11b = Reserved

3.5.3.84 PCIE_CORE_RP_I_DL_FEATURE_EXTENDED_CAPABILITY_HEADER_REG Register (Offset = 910h) [reset = 92010025h]

PCIE_CORE_RP_I_DL_FEATURE_EXTENDED_CAPABILITY_HEADER_REG is shown in Figure 12-1572 and described in Table 12-3086.

Return to the Summary Table.

Data Link Feature Extended Capability Structure is used to configure the DL Feature mechanism.

Table 12-3085 PCIE_CORE_RP_I_DL_FEATURE_EXTENDED_CAPABILITY_HEADER_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0910h

Figure 12-1572 PCIE_CORE_RP_I_DL_FEATURE_EXTENDED_CAPABILITY_HEADER_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DLFNXCAP												DLFCAPVER
R-920h												R-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DLFCAPID
R-25h

LEGEND: R = Read Only; -n = value after reset

Table 12-3086 PCIE_CORE_RP_I_DL_FEATURE_EXTENDED_CAPABILITY_HEADER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	DLFNXCAP	R	920h	The offset to the next PCI Extended Capability structure.
19-16	DLFCAPVER	R	1h	This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.
15-0	DLFCAPID	R	25h	Indicates that the associated extended capability structure is the DL Feature Extended Capability. This field returns a Capability ID of 0025h.

3.5.3.85 PCIE_CORE_RP_I_DL_FEATURE_CAPABILITIES_REG Register (Offset = 914h) [reset = 80000001h]

PCIE_CORE_RP_I_DL_FEATURE_CAPABILITIES_REG is shown in Figure 12-1573 and described in Table 12-3088.

Return to the Summary Table.

Data Link Feature Capabilities Register..

Table 12-3087 PCIE_CORE_RP_I_DL_FEATURE_CAPABILITIES_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0914h

Figure 12-1573 PCIE_CORE_RP_I_DL_FEATURE_CAPABILITIES_REG Register

31	30	29	28	27	26	25	24
DLFEXEN	R0
R-1h	R-0h

23	22	21	20	19	18	17	16
R0
R-0h

15	14	13	12	11	10	9	8
R0
R-0h

7	6	5	4	3	2	1	0
R0							DLFCAPVER
R-0h							R-1h

LEGEND: R = Read Only; -n = value after reset

Table 12-3088 PCIE_CORE_RP_I_DL_FEATURE_CAPABILITIES_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DLFEXEN	R	1h	If Set, this bit indicates that this Port will enter the DL_Feature negotiation state prior to Link Initialization.
30-1	R0	R	0h	Reserved
0	DLFCAPVER	R	1h	This bit indicates that this Port supports the Scaled Flow Control Feature.

3.5.3.86 PCIE_CORE_RP_I_DL_FEATURE_STATUS_REG Register (Offset = 918h) [reset = 0h]

PCIE_CORE_RP_I_DL_FEATURE_STATUS_REG is shown in Figure 12-1574 and described in Table 12-3090.

Return to the Summary Table.

Data Link Feature Status Register..

Table 12-3089 PCIE_CORE_RP_I_DL_FEATURE_STATUS_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0918h

Figure 12-1574 PCIE_CORE_RP_I_DL_FEATURE_STATUS_REG Register

31	30	29	28	27	26	25	24
RDLFSVAL	R1
R-0h	R-0h

23	22	21	20	19	18	17	16
R23	R0
R-0h	R-0h

15	14	13	12	11	10	9	8
R0
R-0h

7	6	5	4	3	2	1	0
R0							RSFSUP
R-0h							R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3090 PCIE_CORE_RP_I_DL_FEATURE_STATUS_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RDLFSVAL	R	0h	This bit indicates that the Port has received a Data Link Feature DLLP in state DL_Feature [see Section 3.2.1] and that the Remote Data Link Feature Supported and Remote Data Link Feature Ack fields are meaningful. This bit is Cleared on entry to state DL_Inactive. Default is 0b.
30-24	R1	R	0h	Reserved
23	R23	R	0h	Reserved
22-1	R0	R	0h	Reserved
0	RSFSUP	R	0h	This bit indicates that the Remote end Device supports the Scaled Flow Control Feature.

3.5.3.87 PCIE_CORE_RP_I_MARGINING_EXTENDED_CAPABILITY_HEADER_REG Register (Offset = 920h) [reset = 9C010027h]

PCIE_CORE_RP_I_MARGINING_EXTENDED_CAPABILITY_HEADER_REG is shown in Figure 12-1575 and described in Table 12-3092.

Return to the Summary Table.

Margining Extended Capability Structure is used to configure the device for Receiver Margining.

Table 12-3091 PCIE_CORE_RP_I_MARGINING_EXTENDED_CAPABILITY_HEADER_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0920h

Figure 12-1575 PCIE_CORE_RP_I_MARGINING_EXTENDED_CAPABILITY_HEADER_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MARNXCAP												MARCAPVER
R-9C0h												R-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MARCAPID
R-27h

LEGEND: R = Read Only; -n = value after reset

Table 12-3092 PCIE_CORE_RP_I_MARGINING_EXTENDED_CAPABILITY_HEADER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	MARNXCAP	R	9C0h	The offset to the next PCI Extended Capability structure.
19-16	MARCAPVER	R	1h	This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.
15-0	MARCAPID	R	27h	Indicates that the associated extended capability structure is the Margining Extended Capability. This field returns a Capability ID of 0027h.

3.5.3.88 PCIE_CORE_RP_I_MARGINING_PORT_CAPABILITIES_STATUS_REG Register (Offset = 924h) [reset = 1h]

PCIE_CORE_RP_I_MARGINING_PORT_CAPABILITIES_STATUS_REG is shown in Figure 12-1576 and described in Table 12-3094.

Return to the Summary Table.

Margining Port Capabilities and Status Register.

Table 12-3093 PCIE_CORE_RP_I_MARGINING_PORT_CAPABILITIES_STATUS_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0924h

Figure 12-1576 PCIE_CORE_RP_I_MARGINING_PORT_CAPABILITIES_STATUS_REG Register

31	30	29	28	27	26	25	24
R1
R-0h

23	22	21	20	19	18	17	16
R1						MSRDY	MRDY
R-0h						R-0h	R-0h

15	14	13	12	11	10	9	8
R0
R-0h

7	6	5	4	3	2	1	0
R0							MARUDS
R-0h							R-1h

LEGEND: R = Read Only; -n = value after reset

Table 12-3094 PCIE_CORE_RP_I_MARGINING_PORT_CAPABILITIES_STATUS_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	R1	R	0h	Reserved
17	MSRDY	R	0h	When Margining uses Driver Software is Set, then this bit, when Set, indicates that the required software has performed the required initialization. The value of this bit is Undefined if Margining users Driver Software is Clear. The Controller implementation sets the default value of this bit to 0. The driver software must initialize the Rx Margining parameters in the Local Management Lane Margining Registers and then program this bit to 1.
16	MRDY	R	0h	Indicates when the Margining feature is ready to accept margining commands. If the Margining uses Driver Software bit is 1, then the Controller sets this status bit when the Margining Software Ready bit is set and the Link is in Gen4 L0 state. If the Margining uses Driver Software bit is 0, then the Controller sets this status bit when the Link is in Gen4 L0 state.
15-1	R0	R	0h	Reserved
0	MARUDS	R	1h	If Set, indicates that Margining is partially implemented using Device Driver software. Margining Software Ready indicates when this software is initialized. If Clear, Margining does not require device driver software. The Controller implementation requires driver software to initialize the Rx Margining parameter values in Local Management Registers for Lane Margining. Hence, the default value of this bit is set to 1.

3.5.3.89 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG0 Register (Offset = 928h) [reset = 9C38h]

PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG0 is shown in Figure 12-1577 and described in Table 12-3096.

Return to the Summary Table.

Margining Lane Control and Status Register for Lane 0.

Table 12-3095 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG0 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0928h

Figure 12-1577 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG0 Register

31	30	29	28	27	26	25	24
MPSTS
R-0h

23	22	21	20	19	18	17	16
R1	UMSTS	MTSTS			RNSTS
R-0h	R-0h	R-0h			R-0h

15	14	13	12	11	10	9	8
MRGPAY
R/W-9Ch

7	6	5	4	3	2	1	0
R0	USGMOD	MRGTYP			RCVNUM
R-0h	R/W-0h	R/W-7h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3096 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MPSTS	R	0h	Margin Payload Status for Margining Commands. This field is reset upon DL Down.
23	R1	R	0h	Reserved
22	UMSTS	R	0h	Usage Model Status for Margining Commands. This field is reset upon DL Down.
21-19	MTSTS	R	0h	Margin Type Status for Margining Commands. This field is reset upon DL Down.
18-16	RNSTS	R	0h	Receiver Number Status for Margining Commands. This field is reset upon DL Down.
15-8	MRGPAY	R/W	9Ch	Margin Payload for Margining Commands. This field is reset upon DL Down.
7	R0	R	0h	Reserved
6	USGMOD	R/W	0h	Usage Model for Margining Commands. This field is reset upon DL Down.
5-3	MRGTYP	R/W	7h	Margin Type for Margining Commands. This field is reset upon DL Down.
2-0	RCVNUM	R/W	0h	Receiver Number for Margining Commands. This field is reset upon DL Down.

3.5.3.90 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG1 Register (Offset = 92Ch) [reset = 9C38h]

PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG1 is shown in Figure 12-1578 and described in Table 12-3098.

Return to the Summary Table.

Margining Lane Control and Status Register for Lane 1.

Table 12-3097 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG1 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 092Ch

Figure 12-1578 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG1 Register

31	30	29	28	27	26	25	24
MPSTS
R-0h

23	22	21	20	19	18	17	16
R1	UMSTS	MTSTS			RNSTS
R-0h	R-0h	R-0h			R-0h

15	14	13	12	11	10	9	8
MRGPAY
R/W-9Ch

7	6	5	4	3	2	1	0
R0	USGMOD	MRGTYP			RCVNUM
R-0h	R/W-0h	R/W-7h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3098 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MPSTS	R	0h	Margin Payload Status for Margining Commands. This field is reset upon DL Down.
23	R1	R	0h	Reserved
22	UMSTS	R	0h	Usage Model Status for Margining Commands. This field is reset upon DL Down.
21-19	MTSTS	R	0h	Margin Type Status for Margining Commands. This field is reset upon DL Down.
18-16	RNSTS	R	0h	Receiver Number Status for Margining Commands. This field is reset upon DL Down.
15-8	MRGPAY	R/W	9Ch	Margin Payload for Margining Commands. This field is reset upon DL Down.
7	R0	R	0h	Reserved
6	USGMOD	R/W	0h	Usage Model for Margining Commands. This field is reset upon DL Down.
5-3	MRGTYP	R/W	7h	Margin Type for Margining Commands. This field is reset upon DL Down.
2-0	RCVNUM	R/W	0h	Receiver Number for Margining Commands. This field is reset upon DL Down.

3.5.3.91 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG2 Register (Offset = 930h) [reset = 9C38h]

PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG2 is shown in Figure 12-1579 and described in Table 12-3100.

Return to the Summary Table.

Margining Lane Control and Status Register for Lane 2.

Table 12-3099 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG2 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0930h

Figure 12-1579 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG2 Register

31	30	29	28	27	26	25	24
MPSTS
R-0h

23	22	21	20	19	18	17	16
R1	UMSTS	MTSTS			RNSTS
R-0h	R-0h	R-0h			R-0h

15	14	13	12	11	10	9	8
MRGPAY
R/W-9Ch

7	6	5	4	3	2	1	0
R0	USGMOD	MRGTYP			RCVNUM
R-0h	R/W-0h	R/W-7h			R/W-0h

Table 12-3100 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MPSTS	R	0h	Margin Payload Status for Margining Commands. This field is reset upon DL Down.
23	R1	R	0h	Reserved
22	UMSTS	R	0h	Usage Model Status for Margining Commands. This field is reset upon DL Down.
21-19	MTSTS	R	0h	Margin Type Status for Margining Commands. This field is reset upon DL Down.
18-16	RNSTS	R	0h	Receiver Number Status for Margining Commands. This field is reset upon DL Down.
15-8	MRGPAY	R/W	9Ch	Margin Payload for Margining Commands. This field is reset upon DL Down.
7	R0	R	0h	Reserved
6	USGMOD	R/W	0h	Usage Model for Margining Commands. This field is reset upon DL Down.
5-3	MRGTYP	R/W	7h	Margin Type for Margining Commands. This field is reset upon DL Down.
2-0	RCVNUM	R/W	0h	Receiver Number for Margining Commands. This field is reset upon DL Down.

3.5.3.92 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG3 Register (Offset = 934h) [reset = 9C38h]

PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG3 is shown in Figure 12-1580 and described in Table 12-3102.

Return to the Summary Table.

Margining Lane Control and Status Register for Lane 3.

Table 12-3101 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG3 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0934h

Figure 12-1580 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG3 Register

31	30	29	28	27	26	25	24
MPSTS
R-0h

23	22	21	20	19	18	17	16
R1	UMSTS	MTSTS			RNSTS
R-0h	R-0h	R-0h			R-0h

15	14	13	12	11	10	9	8
MRGPAY
R/W-9Ch

7	6	5	4	3	2	1	0
R0	USGMOD	MRGTYP			RCVNUM
R-0h	R/W-0h	R/W-7h			R/W-0h

Table 12-3102 PCIE_CORE_RP_I_MARGINING_LANE_CONTROL_STATUS_REG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MPSTS	R	0h	Margin Payload Status for Margining Commands. This field is reset upon DL Down.
23	R1	R	0h	Reserved
22	UMSTS	R	0h	Usage Model Status for Margining Commands. This field is reset upon DL Down.
21-19	MTSTS	R	0h	Margin Type Status for Margining Commands. This field is reset upon DL Down.
18-16	RNSTS	R	0h	Receiver Number Status for Margining Commands. This field is reset upon DL Down.
15-8	MRGPAY	R/W	9Ch	Margin Payload for Margining Commands. This field is reset upon DL Down.
7	R0	R	0h	Reserved
6	USGMOD	R/W	0h	Usage Model for Margining Commands. This field is reset upon DL Down.
5-3	MRGTYP	R/W	7h	Margin Type for Margining Commands. This field is reset upon DL Down.
2-0	RCVNUM	R/W	0h	Receiver Number for Margining Commands. This field is reset upon DL Down.

3.5.3.93 PCIE_CORE_RP_I_PL_16GTS_EXTENDED_CAPABILITY_HEADER_REG Register (Offset = 9C0h) [reset = A2010026h]

PCIE_CORE_RP_I_PL_16GTS_EXTENDED_CAPABILITY_HEADER_REG is shown in Figure 12-1581 and described in Table 12-3104.

Return to the Summary Table.

Physical Layer 16 GT/s Extended Capability Structure is used to configure the device for Gen4 Equalization and Gen4 Lane Error Reporting.

Table 12-3103 PCIE_CORE_RP_I_PL_16GTS_EXTENDED_CAPABILITY_HEADER_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 09C0h

Figure 12-1581 PCIE_CORE_RP_I_PL_16GTS_EXTENDED_CAPABILITY_HEADER_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PL16NXCAP												PL16CAPVER
R-A20h												R-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PL16CAPID
R-26h

LEGEND: R = Read Only; -n = value after reset

Table 12-3104 PCIE_CORE_RP_I_PL_16GTS_EXTENDED_CAPABILITY_HEADER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	PL16NXCAP	R	A20h	The offset to the next PCI Extended Capability structure.
19-16	PL16CAPVER	R	1h	This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.
15-0	PL16CAPID	R	26h	Indicates that the associated extended capability structure is for Physical layer 16 GT/s. This field returns a Capability ID of 0026h.

3.5.3.94 PCIE_CORE_RP_I_PL_16GTS_CAPABILITIES_REG Register (Offset = 9C4h) [reset = 0h]

PCIE_CORE_RP_I_PL_16GTS_CAPABILITIES_REG is shown in Figure 12-1582 and described in Table 12-3106.

Return to the Summary Table.

Physical Layer 16GTs Capabilities Register.

Table 12-3105 PCIE_CORE_RP_I_PL_16GTS_CAPABILITIES_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 09C4h

Figure 12-1582 PCIE_CORE_RP_I_PL_16GTS_CAPABILITIES_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3106 PCIE_CORE_RP_I_PL_16GTS_CAPABILITIES_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	R0	R	0h	Reserved

3.5.3.95 PCIE_CORE_RP_I_PL_16GTS_CONTROL_REG Register (Offset = 9C8h) [reset = 0h]

PCIE_CORE_RP_I_PL_16GTS_CONTROL_REG is shown in Figure 12-1583 and described in Table 12-3108.

Return to the Summary Table.

Physical Layer 16GTs Control Register.

Table 12-3107 PCIE_CORE_RP_I_PL_16GTS_CONTROL_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 09C8h

Figure 12-1583 PCIE_CORE_RP_I_PL_16GTS_CONTROL_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3108 PCIE_CORE_RP_I_PL_16GTS_CONTROL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	R0	R	0h	Reserved

3.5.3.96 PCIE_CORE_RP_I_PL_16GTS_STATUS_REG Register (Offset = 9CCh) [reset = 0h]

PCIE_CORE_RP_I_PL_16GTS_STATUS_REG is shown in Figure 12-1584 and described in Table 12-3110.

Return to the Summary Table.

Physical Layer 16GTs Status Register.

Table 12-3109 PCIE_CORE_RP_I_PL_16GTS_STATUS_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 09CCh

Figure 12-1584 PCIE_CORE_RP_I_PL_16GTS_STATUS_REG Register

31	30	29	28	27	26	25	24
R0
R-0h

23	22	21	20	19	18	17	16
R0
R-0h

15	14	13	12	11	10	9	8
R0
R-0h

7	6	5	4	3	2	1	0
R0			LE16	EP3S16	EP2S16	EP1S16	EQC16
R-0h			R/W1C-0h	R-0h	R-0h	R-0h	R-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-3110 PCIE_CORE_RP_I_PL_16GTS_STATUS_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	R0	R	0h	Reserved
4	LE16	R/W1C	0h	When the Controller [RP] receives an 16GTs equalization request from an Upstream Port the Controller internally sets this bit to 1. [i.e. when RP is in the Recovery.RcvrCfg state and receives 8 consecutive TS2 Ordered Sets with the Request Equalization bit set to 1b] The LOCAL_INTERRUPT output is also asserted if Link Equalization Request Interrupt Enable is enabled.
3	EP3S16	R	0h	This bit, when set to 1, indicates that the Phase 3 of the Transmitter Equalization procedure has completed successfully for 16.0 GT/s. STICKY.
2	EP2S16	R	0h	This bit, when set to 1, indicates that the Phase 2 of the Transmitter Equalization procedure has completed successfully for 16.0 GT/s. STICKY.
1	EP1S16	R	0h	This bit, when set to 1, indicates that the Phase 1 of the Transmitter Equalization procedure has completed successfully for 16.0 GT/s. STICKY.
0	EQC16	R	0h	This bit, when set to 1, indicates that the Transmitter Equalization procedure has completed for 16.0 GT/s. STICKY.

3.5.3.97 PCIE_CORE_RP_I_PL_16GTS_LOCAL_DATA_PARITY_MISMATCH_STATUS_REG Register (Offset = 9D0h) [reset = 0h]

PCIE_CORE_RP_I_PL_16GTS_LOCAL_DATA_PARITY_MISMATCH_STATUS_REG is shown in Figure 12-1585 and described in Table 12-3112.

Return to the Summary Table.

Physical Layer 16GTs Local Data Parity Mismatch Status Register.

Table 12-3111 PCIE_CORE_RP_I_PL_16GTS_LOCAL_DATA_PARITY_MISMATCH_STATUS_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 09D0h

Figure 12-1585 PCIE_CORE_RP_I_PL_16GTS_LOCAL_DATA_PARITY_MISMATCH_STATUS_REG Register

31	30	29	28	27	26	25	24
R0
R-0h

23	22	21	20	19	18	17	16
R0
R-0h

15	14	13	12	11	10	9	8
R0
R-0h

7	6	5	4	3	2	1	0
R0				LDPMS16
R-0h				R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-3112 PCIE_CORE_RP_I_PL_16GTS_LOCAL_DATA_PARITY_MISMATCH_STATUS_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	R0	R	0h	N/A
3-0	LDPMS16	R/W1C	0h	Each bit indicates if the corresponding Lane detected a Data Parity mismatch. A value of 1b indicates that a mismatch was detected on the corresponding Lane Number.

3.5.3.98 PCIE_CORE_RP_I_PL_16GTS_FIRST_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Register (Offset = 9D4h) [reset = 0h]

PCIE_CORE_RP_I_PL_16GTS_FIRST_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG is shown in Figure 12-1586 and described in Table 12-3114.

Return to the Summary Table.

Physical Layer 16GTs First Retimer Data Parity Mismatch Status Register.

Table 12-3113 PCIE_CORE_RP_I_PL_16GTS_FIRST_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 09D4h

Figure 12-1586 PCIE_CORE_RP_I_PL_16GTS_FIRST_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Register

31	30	29	28	27	26	25	24
R0
R-0h

23	22	21	20	19	18	17	16
R0
R-0h

15	14	13	12	11	10	9	8
R0
R-0h

7	6	5	4	3	2	1	0
R0				FRDPMS16
R-0h				R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-3114 PCIE_CORE_RP_I_PL_16GTS_FIRST_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	R0	R	0h	N/A
3-0	FRDPMS16	R/W1C	0h	Each bit indicates if the first retimer in the corresponding Lane detected a Data Parity mismatch. A value of 1b indicates that a mismatch was detected on the corresponding Lane Number. The value of this field is undefined when no Retimers are present.

3.5.3.99 PCIE_CORE_RP_I_PL_16GTS_SECOND_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Register (Offset = 9D8h) [reset = 0h]

PCIE_CORE_RP_I_PL_16GTS_SECOND_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG is shown in Figure 12-1587 and described in Table 12-3116.

Return to the Summary Table.

Physical Layer 16GTs Second Retimer Data Parity Mismatch Status Register.

Table 12-3115 PCIE_CORE_RP_I_PL_16GTS_SECOND_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 09D8h

Figure 12-1587 PCIE_CORE_RP_I_PL_16GTS_SECOND_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Register

31	30	29	28	27	26	25	24
R0
R-0h

23	22	21	20	19	18	17	16
R0
R-0h

15	14	13	12	11	10	9	8
R0
R-0h

7	6	5	4	3	2	1	0
R0				SRDPMS16
R-0h				R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 12-3116 PCIE_CORE_RP_I_PL_16GTS_SECOND_RETIMER_DATA_PARITY_MISMATCH_STATUS_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	R0	R	0h	N/A
3-0	SRDPMS16	R/W1C	0h	Each bit indicates if the second retimer in the corresponding Lane detected a Data Parity mismatch. A value of 1b indicates that a mismatch was detected on the corresponding Lane Number. The value of this field is undefined when no Retimers are present.

3.5.3.100 PCIE_CORE_RP_I_PL_16GTS_RESERVED_REG Register (Offset = 9DCh) [reset = 0h]

PCIE_CORE_RP_I_PL_16GTS_RESERVED_REG is shown in Figure 12-1588 and described in Table 12-3118.

Return to the Summary Table.

Register at offset 1Ch in this capability is Reserved.

Table 12-3117 PCIE_CORE_RP_I_PL_16GTS_RESERVED_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 09DCh

Figure 12-1588 PCIE_CORE_RP_I_PL_16GTS_RESERVED_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3118 PCIE_CORE_RP_I_PL_16GTS_RESERVED_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	R0	R	0h	Reserved

3.5.3.101 PCIE_CORE_RP_I_PL_16GTS_LANE_EQUALIZATION_CONTROL_REG0 Register (Offset = 9E0h) [reset = FFFFFFFFh]

PCIE_CORE_RP_I_PL_16GTS_LANE_EQUALIZATION_CONTROL_REG0 is shown in Figure 12-1589 and described in Table 12-3120.

Return to the Summary Table.

This register contains the Downstream and Upstream Port 16.0GT/s Transmitter Preset for
lanes 0, 1, 2 and 3 that will be used for 16GT/s Link Equalization procedure when this port is operating as a Downstream Port.

Table 12-3119 PCIE_CORE_RP_I_PL_16GTS_LANE_EQUALIZATION_CONTROL_REG0 Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 09E0h

Figure 12-1589 PCIE_CORE_RP_I_PL_16GTS_LANE_EQUALIZATION_CONTROL_REG0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UPTP316				DPTP316				UPTP216				DPTP216
R-Fh				R-Fh				R-Fh				R-Fh

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UPTP116				DPTP116				UPTP016				DPTP016
R-Fh				R-Fh				R-Fh				R-Fh

LEGEND: R = Read Only; -n = value after reset

Table 12-3120 PCIE_CORE_RP_I_PL_16GTS_LANE_EQUALIZATION_CONTROL_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	UPTP316	R	Fh	16.0GT/s Lane 3 Transmitter Preset value that the Downstream Port sends on the associated Lane to the Endpoint device during 16GT/s Link Equalization.
27-24	DPTP316	R	Fh	Transmitter Preset used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port.
23-20	UPTP216	R	Fh	16.0GT/s Lane 2 Transmitter Preset value that the Downstream Port sends on the associated Lane to the Endpoint device during 16GT/s Link Equalization.
19-16	DPTP216	R	Fh	Transmitter Preset used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port.
15-12	UPTP116	R	Fh	16.0GT/s Lane 1 Transmitter Preset value that the Downstream Port sends on the associated Lane to the Endpoint device during 16GT/s Link Equalization.
11-8	DPTP116	R	Fh	Transmitter Preset used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port.
7-4	UPTP016	R	Fh	16.0GT/s Lane 0 Transmitter Preset value that the Downstream Port sends on the associated Lane to the Endpoint device during 16GT/s Link Equalization.
3-0	DPTP016	R	Fh	Transmitter Preset used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port.

3.5.3.102 PCIE_CORE_RP_I_PTM_EXTENDED_CAPABILITY_HEADER_REG Register (Offset = A20h) [reset = 0001001Fh]

PCIE_CORE_RP_I_PTM_EXTENDED_CAPABILITY_HEADER_REG is shown in Figure 12-1590 and described in Table 12-3122.

Return to the Summary Table.

Precision Time Measurement Extended Capability Structure is used discovering and controlling the distribution of a PTM hierarchy.

Table 12-3121 PCIE_CORE_RP_I_PTM_EXTENDED_CAPABILITY_HEADER_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0A20h

Figure 12-1590 PCIE_CORE_RP_I_PTM_EXTENDED_CAPABILITY_HEADER_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PTMNXCAP												PTMCAPVER
R-0h												R-1h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PTMCAPID
R-1Fh

LEGEND: R = Read Only; -n = value after reset

Table 12-3122 PCIE_CORE_RP_I_PTM_EXTENDED_CAPABILITY_HEADER_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	PTMNXCAP	R	0h	The offset to the next PCIe Extended Capability structure.
19-16	PTMCAPVER	R	1h	This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.
15-0	PTMCAPID	R	1Fh	Indicates that the associated extended capability structure is for Precision Time Measurement capability. This field returns a Capability ID of 001Fh.

3.5.3.103 PCIE_CORE_RP_I_PTM_CAPABILITIES_REG Register (Offset = A24h) [reset = 206h]

PCIE_CORE_RP_I_PTM_CAPABILITIES_REG is shown in Figure 12-1591 and described in Table 12-3124.

Return to the Summary Table.

PTM Capabilities Register.

Table 12-3123 PCIE_CORE_RP_I_PTM_CAPABILITIES_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0A24h

Figure 12-1591 PCIE_CORE_RP_I_PTM_CAPABILITIES_REG Register

31	30	29	28	27	26	25	24
R16
R-0h

23	22	21	20	19	18	17	16
R16
R-0h

15	14	13	12	11	10	9	8
LOCCLKGR
R-2h

7	6	5	4	3	2	1	0
R3					PTMRTCAP	PTMRSCAP	PTMRQCAP
R-0h					R-1h	R-1h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 12-3124 PCIE_CORE_RP_I_PTM_CAPABILITIES_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	R16	R	0h	Reserved
15-8	LOCCLKGR	R	2h	In RC Mode: The Controller uses the CORE_CLK as the Local Clock for PTM. This field is used to indicate the Time Period of the CORE_CLK. If the PTM Root Select is 1, then CORE_CLK is used to provide PTM Master Time. If the PTM Root Select is 0, then CORE_CLK is used to locally track the PTM Master Time received on the PTM_LOCAL_TIMER_IN [63:0] input. By default, this field is set to 8'd2. This bit can be programmed through the local management APB interface if required.
7-3	R3	R	0h	Reserved
2	PTMRTCAP	R	1h	This bit is used to indicate that the Controller implements PTM Time Source Role and is capable of serving as PTM Root. By default, this bit is set to 1 when the Controller is in RC Mode. This bit can be programmed through the local management APB interface if required. Note: If this bit is programmed to 1, then the PTM Responder Capable bit must also be programmed to 1 by FW.
1	PTMRSCAP	R	1h	This bit is used to indicate support for PTM Responder Role. By default, this bit is set to 1 when the Controller is in RC Mode. This bit can be programmed through the local management APB interface if required. Note: If the PTM Root Capable is programmed to 1, then this bit must also be programmed to 1 by FW.
0	PTMRQCAP	R	0h	This bit is used to indicate support for PTM Requester Role. By default, this bit is set to 0 when the Controller is in RC Mode. This bit can be programmed through the local management APB interface if required.

3.5.3.104 PCIE_CORE_RP_I_PTM_CONTROL_REG Register (Offset = A28h) [reset = 0h]

PCIE_CORE_RP_I_PTM_CONTROL_REG is shown in Figure 12-1592 and described in Table 12-3126.

Return to the Summary Table.

PTM Control Register.

Table 12-3125 PCIE_CORE_RP_I_PTM_CONTROL_REG Instances

Instance	Physical Address
PCIE1_CORE_DBN_CFG_PCIE_CORE	0D80 0A28h

Figure 12-1592 PCIE_CORE_RP_I_PTM_CONTROL_REG Register

31	30	29	28	27	26	25	24
R16
R-0h

23	22	21	20	19	18	17	16
R16
R-0h

15	14	13	12	11	10	9	8
EFFGRN
R-0h

7	6	5	4	3	2	1	0
R2						RTSEL	PTMEN
R-0h						R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 12-3126 PCIE_CORE_RP_I_PTM_CONTROL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	R16	R	0h	Reserved
15-8	EFFGRN	R	0h	This field is used only in PTM Requester Mode and is not used in RC Mode. This field is set to 00 by default in RC Mode.
7-2	R2	R	0h	Reserved
1	RTSEL	R/W	0h	This field is configured by System SW. When set to 1 and when PTM Enable bit is aslo set to 1, this PTM Source is the PTM Root. Default value of this bit is 0.
0	PTMEN	R/W	0h	When Set, this function is permitted to participate in the PTM mechanism as PTM Requester. By default, this bit is set to 0.

12.2.3.5.3 PCIE_CORE_RP Registers

3.5.3.1 PCIE_CORE_RP_I_VENDOR_ID_DEVICE_ID Register (Offset = 0h) [reset = 010017CDh]

3.5.3.2 PCIE_CORE_RP_I_COMMAND_STATUS Register (Offset = 4h) [reset = 00100000h]

3.5.3.3 PCIE_CORE_RP_I_REVISION_ID_CLASS_CODE Register (Offset = 8h) [reset = 0h]

3.5.3.4 PCIE_CORE_RP_I_BIST_HEADER_LATENCY_CACHE_LINE Register (Offset = Ch) [reset = 00010000h]

3.5.3.5 PCIE_CORE_RP_I_RC_BAR_0 Register (Offset = 10h) [reset = 0h]

3.5.3.6 PCIE_CORE_RP_I_RC_BAR_1 Register (Offset = 14h) [reset = 0h]

3.5.3.7 PCIE_CORE_RP_I_PCIE_BUS_NUMBERS Register (Offset = 18h) [reset = 0h]

3.5.3.8 PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT Register (Offset = 1Ch) [reset = 0h]

3.5.3.9 PCIE_CORE_RP_I_PCIE_MEM_BASE_LIMIT Register (Offset = 20h) [reset = 0h]

3.5.3.10 PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_LIMIT Register (Offset = 24h) [reset = 0h]

3.5.3.11 PCIE_CORE_RP_I_PCIE_PREFETCH_BASE_UPPER Register (Offset = 28h) [reset = 0h]

3.5.3.12 PCIE_CORE_RP_I_PCIE_PREFETCH_LIMIT_UPPER Register (Offset = 2Ch) [reset = 0h]

3.5.3.13 PCIE_CORE_RP_I_PCIE_IO_BASE_LIMIT_UPPER Register (Offset = 30h) [reset = 0h]

3.5.3.14 PCIE_CORE_RP_I_CAPABILITIES_POINTER Register (Offset = 34h) [reset = 80h]

3.5.3.15 PCIE_CORE_RP_RSVD_0E Register (Offset = 38h) [reset = 0h]

3.5.3.16 PCIE_CORE_RP_I_INTRPT_LINE_INTRPT_PIN Register (Offset = 3Ch) [reset = 1FFh]

3.5.3.17 PCIE_CORE_RP_I_PWR_MGMT_CAP Register (Offset = 80h) [reset = 5A039001h]

3.5.3.18 PCIE_CORE_RP_I_PWR_MGMT_CTRL_STAT_REP Register (Offset = 84h) [reset = 8h]

3.5.3.19 PCIE_CORE_RP_I_MSI_CTRL_REG Register (Offset = 90h) [reset = 0180B005h]

3.5.3.20 PCIE_CORE_RP_I_MSI_MSG_LOW_ADDR Register (Offset = 94h) [reset = 0h]

3.5.3.21 PCIE_CORE_RP_I_MSI_MSG_HI_ADDR Register (Offset = 98h) [reset = 0h]

3.5.3.22 PCIE_CORE_RP_I_MSI_MSG_DATA Register (Offset = 9Ch) [reset = 0h]

3.5.3.23 PCIE_CORE_RP_I_MSI_MASK Register (Offset = A0h) [reset = X]

3.5.3.24 PCIE_CORE_RP_I_MSI_PENDING_BITS Register (Offset = A4h) [reset = X]

3.5.3.25 PCIE_CORE_RP_I_MSIX_CTRL Register (Offset = B0h) [reset = C011h]

3.5.3.26 PCIE_CORE_RP_I_MSIX_TBL_OFFSET Register (Offset = B4h) [reset = 0h]

3.5.3.27 PCIE_CORE_RP_I_MSIX_PENDING_INTRPT Register (Offset = B8h) [reset = 8h]

3.5.3.28 PCIE_CORE_RP_I_PCIE_CAP_LIST Register (Offset = C0h) [reset = 01420010h]

3.5.3.29 PCIE_CORE_RP_I_PCIE_CAP Register (Offset = C4h) [reset = 8001h]

3.5.3.30 PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS Register (Offset = C8h) [reset = 2810h]

3.5.3.31 PCIE_CORE_RP_I_LINK_CAP Register (Offset = CCh) [reset = 0061AC44h]

3.5.3.32 PCIE_CORE_RP_I_LINK_CTRL_STATUS Register (Offset = D0h) [reset = 00410000h]

3.5.3.33 PCIE_CORE_RP_I_SLOT_CAPABILITY Register (Offset = D4h) [reset = 0h]

3.5.3.34 PCIE_CORE_RP_I_SLOT_CTRL_STATUS Register (Offset = D8h) [reset = 002007C0h]

3.5.3.35 PCIE_CORE_RP_I_ROOT_CTRL_CAP Register (Offset = DCh) [reset = 0h]

3.5.3.36 PCIE_CORE_RP_I_ROOT_STATUS Register (Offset = E0h) [reset = 0h]

3.5.3.37 PCIE_CORE_RP_I_PCIE_CAP_2 Register (Offset = E4h) [reset = X]

3.5.3.38 PCIE_CORE_RP_I_PCIE_DEV_CTRL_STATUS_2 Register (Offset = E8h) [reset = 0h]

3.5.3.39 PCIE_CORE_RP_I_LINK_CAP_2 Register (Offset = ECh) [reset = X]

3.5.3.40 PCIE_CORE_RP_I_LINK_CTRL_STATUS_2 Register (Offset = F0h) [reset = 00010004h]

3.5.3.41 PCIE_CORE_RP_I_AER_ENHNCD_CAP Register (Offset = 100h) [reset = 15020001h]

3.5.3.42 PCIE_CORE_RP_I_UNCORR_ERR_STATUS Register (Offset = 104h) [reset = 0h]

3.5.3.43 PCIE_CORE_RP_I_UNCORR_ERR_MASK Register (Offset = 108h) [reset = 00400000h]

3.5.3.44 PCIE_CORE_RP_I_UNCORR_ERR_SEVERITY Register (Offset = 10Ch) [reset = 00462030h]

3.5.3.45 PCIE_CORE_RP_I_CORR_ERR_STATUS Register (Offset = 110h) [reset = 0h]

3.5.3.46 PCIE_CORE_RP_I_CORR_ERR_MASK Register (Offset = 114h) [reset = E000h]

3.5.3.47 PCIE_CORE_RP_I_ADV_ERR_CAP_CTL Register (Offset = 118h) [reset = A0h]

3.5.3.48 PCIE_CORE_RP_I_HDR_LOG_0 Register (Offset = 11Ch) [reset = 0h]

3.5.3.49 PCIE_CORE_RP_I_HDR_LOG_1 Register (Offset = 120h) [reset = 0h]

3.5.3.50 PCIE_CORE_RP_I_HDR_LOG_2 Register (Offset = 124h) [reset = 0h]

3.5.3.51 PCIE_CORE_RP_I_HDR_LOG_3 Register (Offset = 128h) [reset = 0h]

3.5.3.52 PCIE_CORE_RP_I_ROOT_ERR_CMD Register (Offset = 12Ch) [reset = 0h]

3.5.3.53 PCIE_CORE_RP_I_ROOT_ERR_STAT Register (Offset = 130h) [reset = 0h]

3.5.3.54 PCIE_CORE_RP_I_ERR_SRC_ID Register (Offset = 134h) [reset = 0h]

3.5.3.55 PCIE_CORE_RP_I_TLP_PRE_LOG_0 Register (Offset = 138h) [reset = 0h]

3.5.3.56 PCIE_CORE_RP_I_DEV_SER_NUM_CAP_HDR Register (Offset = 150h) [reset = 30010003h]

3.5.3.57 PCIE_CORE_RP_I_DEV_SER_NUM_0 Register (Offset = 154h) [reset = 0h]

3.5.3.58 PCIE_CORE_RP_I_DEV_SER_NUM_1 Register (Offset = 158h) [reset = 0h]

3.5.3.59 PCIE_CORE_RP_I_SEC_PCIE_CAP_HDR_REG Register (Offset = 300h) [reset = 4C010019h]

3.5.3.60 PCIE_CORE_RP_I_LINK_CONTROL3 Register (Offset = 304h) [reset = 0h]

3.5.3.61 PCIE_CORE_RP_I_LANE_ERROR_STATUS Register (Offset = 308h) [reset = 0h]

3.5.3.62 PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_0 Register (Offset = 30Ch) [reset = 7F7F7F7Fh]

3.5.3.63 PCIE_CORE_RP_I_LANE_EQUALIZATION_CONTROL_1 Register (Offset = 310h) [reset = 7F7F7F7Fh]

3.5.3.64 PCIE_CORE_RP_I_VC_ENH_CAP_HEADER_REG Register (Offset = 4C0h) [reset = 5C010002h]

3.5.3.65 PCIE_CORE_RP_I_PORT_VC_CAP_REG_1 Register (Offset = 4C4h) [reset = X]

3.5.3.66 PCIE_CORE_RP_I_PORT_VC_CAP_REG_2 Register (Offset = 4C8h) [reset = 0h]

3.5.3.67 PCIE_CORE_RP_I_PORT_VC_CTRL_STS_REG Register (Offset = 4CCh) [reset = 0h]

3.5.3.68 PCIE_CORE_RP_I_VC_RES_CAP_REG_0 Register (Offset = 4D0h) [reset = 0h]

3.5.3.69 PCIE_CORE_RP_I_VC_RES_CTRL_REG_0 Register (Offset = 4D4h) [reset = X]

3.5.3.70 PCIE_CORE_RP_I_VC_RES_STS_REG_0 Register (Offset = 4D8h) [reset = X]

3.5.3.71 PCIE_CORE_RP_I_VC_RES_CAP_REG_1 Register (Offset = 4DCh) [reset = 0h]

3.5.3.72 PCIE_CORE_RP_I_VC_RES_CTRL_REG_1 Register (Offset = 4E0h) [reset = X]

3.5.3.73 PCIE_CORE_RP_I_VC_RES_STS_REG_1 Register (Offset = 4E4h) [reset = X]

3.5.3.74 PCIE_CORE_RP_I_VC_RES_CAP_REG_2 Register (Offset = 4E8h) [reset = 0h]

3.5.3.75 PCIE_CORE_RP_I_VC_RES_CTRL_REG_2 Register (Offset = 4ECh) [reset = X]

3.5.3.76 PCIE_CORE_RP_I_VC_RES_STS_REG_2 Register (Offset = 4F0h) [reset = X]

3.5.3.77 PCIE_CORE_RP_I_VC_RES_CAP_REG_3 Register (Offset = 4F4h) [reset = 0h]

3.5.3.78 PCIE_CORE_RP_I_VC_RES_CTRL_REG_3 Register (Offset = 4F8h) [reset = X]

3.5.3.79 PCIE_CORE_RP_I_VC_RES_STS_REG_3 Register (Offset = 4FCh) [reset = X]