SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 5-1369 lists all available steps used in exiting LPM.
Step Label | Responsible HW/SW | Step Description |
---|---|---|
LPM_Ex-01 | SoC | SoC and PMIC are in SuspendToRAM mode. |
LPM_Ex-02 | PMIC | PMIC detects an external wakeup event from SuspendToRAM, it can be any, but not limited to the events below:
|
LPM_Ex-03 | PMIC | PMIC wakeup and enables power supply to full SoC. |
LPM_Ex-03a | PMIC | PMIC wakeup and enables power supply to MCU domain and MCU-IOs. |
LPM_Ex-04.1a | SoC | WKUP/MCU goes through PORz reset and starts ROM boot sequence. |
LPM_Ex-04.1b | SW(MCU_R5FSSx) | R5FSS boots to SBL. |
LPM_Ex-04.1c | SW(MCU_R5FSSx) | SBL sends command to PMIC via WKUP_I2C0 to check SuspendToRAM flag to identify if this is COLD or SuspendToRAM-boot. |
LPM_Ex-04.2 | SoC | Main domain goes through PORz reset |
LPM_Ex-05 | SW(MCU_R5FSSx) | SBL detects device recovered from SuspendToRAM. |
LPM_Ex-05.1a | SW(MCU_R5FSSx) | SBL reads from boot-strap boot-mode regiters that this is MCU-ONLY boot. |
LPM_Ex-05.1b | SW(MCU_R5FSSx) | SBL reads from boot-strap boot-mode registers that this is full-SoC boot. |
LPM_Ex-05.2 | SW(MCU_R5FSSx) | SBL does restore to MCU domain (no DDR available). |
LPM_Ex-06 | FW/SW(MCU_R5FSSx) | - Restore required context to main domain from DDR and RESUME. - DMSC (or potentially R5F) sets to power-up all PDs and ENABLE all the LPSCs (or as required per usage case and per as seen per context saving information ). - Sequence power-up and LPSC enable as per dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). - Restore required context to MAIN domain from DDR and RESUME. |
LPM_Ex-07-0 | Start MCU-Only R5FSS-OFF | - PD_MCU_R5FSS = OFF - LPSC_WKUP_GPIO is in DISABLE (not SwRstDis) state, such that it could generate wake-up events - LPSC_WKUP_ALWAYSON and LPSC_DMSC are in ENABLE state - All other LPSCs are in SwRstDis state - DMSC in LPM4 or LPM3. |
LPM_Ex-07-1 | Start MCU-Only | MCU is in functional mode, PLLCNTRL in clock bypass mode, MCU_R5FSS in WFI/WFE, DMSC in LPM0(WFI). |
LPM_Ex-07-2 | IO | One of the IOs enable to detect wakeup events is toggled from the board. - Event will propagate asynchronous through all of the IO-PM daisy chain (DCH) and eventually reaches DMSC. - The IO-PM wake-up event corresponding to each of the 2 IO-PM-DCH were set prior to enter LPM4/3. - The DMSC ASYNC-starts driving WKUP_HFOSC0 to enable state and PWR-ON - The DMSC wake-up FSM running of the 32-kHz RC oscillator starts the wake-up of DMSC. - DMSC eventually exits LPM4/3 and the interrupt map to the IO-PM-DCHs will cause M3 to exit WFI. - M3 executes corresponding wakeup ISR |
LPM_Ex-10 | FW | DMSC puts main IO back to normal state. When peripherals are initialized, CTRLMMR_WKUP_DEEPSLEEP_CTRL override for main domain can be released to allow IO to be controlled by core logic again. |
LPM_Ex-11 | DMSC-FW | -DMSC Powers-ON PD_MCU_R5FSS and enables R5x as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). -MCU-R5x reboot |
LPM_Ex-12 | MCU SW | MCU_R5FSS SW decides to SoC transition to active mode by requesting to DMSC. |
LPM_Ex-13 | FW | DMSC powers up the power domains in the main domain to enter active mode. |
LPM_Ex-14 | FW/SW(MCU_R5FSSx) | Wake-up events CASE-1: - CASE1: An interrupt defined for the purpose of wake-up from active peripherals, as per the list below, is detected in the MCU_R5FSS. If MCU_R5FSS is in WFI/WFE mode, it exits WFI/WFE mode and respond to interrupt. When MCU_R5FSS is ACTIVE or WFI the interrupt can be from any of the peripherals or timer events in MCU map to MCU_R5FSS: Examples - I2C, UART, ADC, SPI etc. |
LPM_Ex-14-2 | DMSC-FW | Wake-up events CASE-2 and 3: For the below wakeup cases only DMSC can detect the wake-up condition. - CASE2: When R5F is OFF or in CLKSTOP only interrupts map to DMSC could cause wakeup. - CASE3: Even if R5F is ON, when the wake-up event is map to be detected by the IO-PM daisy chain either in WKUP/MCU or MAIN, only DMSC can detect such event. |
LPM_Ex-15-2-1 | FW/SW(MCU_R5FSSx) | Wake-up events CASE-1: R5F ON and enabled and out of WFI/WFE executing ISR. The ISR will also ID if SoC_MAIN needs to be ON. |
LPM_Ex-15-2-2 | DMSC-FW | Wake-up events CASE-3: - R5F is ON, but wake-up event is only map as an interrupt and wake-up event for DMSC to detect it. - DMSC runs ISR which depending on the WKUP source might not require to turn ON SoC_MAIN. - If wakeup source is from WKUP-IO-PM-DCH then DMSC needs to check all CTRLMMR_WKUP_PADCONFIGi (i = 0 to 93) registers to figure out the periperhal whose IO caused the wkup event - If wakeup source is from MAIN-IO-PM-DCH then DMSC will need to power-ON SoC_MAIN. |
LPM_Ex-15-2-3 | DMSC-FW | Wake-up events CASE-2: - R5F is OFF, wake-up event is only map as an interrupt and wake-up event for DMSC to detect it. - DMSC runs ISR which depending on the WKUP source might not require to turn ON SoC_MAIN. - If wakeup source is from MAIN-IO-PM-DCH then DMSC will have to power-on SoC_MAIN. |
LPM_Ex-15-2-5 | FW/SW (MCU_R5FSSx) | If SoC_MAIN needs to be ON there are 2 cases: -If PMIC_PIN_CTRL: PMIC control is via pin MCU_R5FSS0x core will send request message to DMSC to power-ON main. -Else If PMIC_I2C_CTRL: then MCU_R5FSS0x will run the PMIC driver itself and message to DMSC once main is ON for the FW to stay in sync. |
LPM_Ex-15-2-6 | DMSC-FW | - Set MMR inside WKUP_PLLCTRL0 PLLCTL[0] PLLEN = 1 and PLLCTL[5] PLLENSRC = 1. - Switch the input clock for WKUP_PLLC0TRL from WKUP_HFOSC0_CLKOUT to MCU_PLL0/HSDIV_CLKOUT. - By now WKUP_PLLCTRL0 should be out of bypass mode and running of MCU_PLL0. - If required as part of the context restore, turn-ON/Enable HFOSC1. - If required as part of the context restore, turn-ON/Enable MCU_PLL1 and MCU_PLL2. |
LPM_Ex-15-2-7 | FW | DMSC (or potentially R5F) sets to ENABLE all the LPSCs (or as required per usage case) in the WKUP_PSC based on dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). With the exception of the LPSCs listed below, which will be enable at a later step: - LPSC_WKUPMCU2MAIN, LPSC_MAIN2WKUPMCU, LPSC_DEBUG2DMSC, LPSC_MCU_DEBUG. |
LPM_Ex-15-2-8 | DMSC-FW | DMSC to remove wkup-IO-PM-DCH from isolation mode and move them to functional mode. When peripherals are initialized, CTRLMMR_WKUP_DEEPSLEEP_CTRL override for WKUP can be released to allow IO to be controlled by core logic again. |
LPM_Ex-15-2-9 | FW | -Via WKUP_CTRL_MMR0 module, confirm removal of the reset-isolation blocking on the main_porz propagation: CTRLMMR_WKUP_POR_RST_CTRL[0] POR_RST_ISO_DONE_Z = 0. -Via WKUP_CTRL_MMR0 module apply PORz to SoC_MAIN: CTRLMMR_WKUP_POR_RST_CTRL[19-16] SW_MAIN_POR = 4'b0110 . |
LPM_Ex-16-1 | FW | DMSC sets CTRLMMR_WKUP_MAIN_PWR_CTRL[0] PWR_EN to turn on the main voltage domain. This information is further transported through pin to PMIC to turn on the main voltage domain supply. |
LPM_Ex-16-2 | FW | -Clear PGOOD status bit in POK modules related to SoC_MAIN core portion of the SoC via WKUP_CTRL_MMR0 module: CTRLMMR_WKUP_MAIN_PRG_STAT[31] POK_CLR = 1. POK_VDD_CORE_UV_CTRL, POK_VDD_CPU_UV_CTRL, POK_VDDR_CORE_UV_CTRL, POK_VMON_EXT_UV_CTRL POK_VDD_CORE_OV_CTRL,POK_VDD_CPU_OV_CTRL, POK_VDDR_CORE_OV_CTRL, POK_VMON_EXT_OV_CTRL |
LPM_Ex-16-3 | FW | -Poll until all POK UV and OV status bitts indicate PGOOD status for all POK modules related to SoC_MAIN core portion of the SoC via WKUP_CTRL_MMR0 module: CTRLMMR_WKUP_MAIN_PRG_STAT corresponidng POK_*_OV/UV = 1. POK_VDD_CORE_UV_CTRL, POK_VDD_CPU_UV_CTRL, POK_VDDR_CORE_UV_CTRL, POK_VMON_EXT_UV_CTRL POK_VDD_CORE_OV_CTRL,POK_VDD_CPU_OV_CTRL, POK_VDDR_CORE_OV_CTRL, POK_VMON_EXT_OV_CTRL |
LPM_Ex-16-4 | FW | -Restore the ESM and RESET -Gating values as they were prior to enter MCU_ONLY* mode for POK modules related to SoC_MAIN core portion of the SoC via WKUP_CTRL_MMR0 module. POK_VDD_CORE_UV_CTRL, POK_VDD_CPU_UV_CTRL, POK_VDDR_CORE_UV_CTRL, POK_VMON_EXT_UV_CTRL POK_VDD_CORE_OV_CTRL,POK_VDD_CPU_OV_CTRL, POK_VDDR_CORE_OV_CTRL, POK_VMON_EXT_OV_CTRL - First restore their contribution to ESM events. - Next restore their contribution to PRG reset, CTRLMMR_WKUP_MAIN_PRG_CTRL corresponidng POK_*_GATERST_EN = 0. |
LPM_Ex-17-1 | FW | Clear CTRLMMR_WKUP_MAIN_VDOM_CTRL[0] MAIN_VD_OFF = 0 in WKUP_CTRL_MMR0 module prior to powering off the main voltage domain to remove proper signal isolation. |
LPM_Ex-17-2 | SoC | Keep polling WKUP_CTRL_MMR0 register module bit RST_STAT[0] until it is '1' to make sure maing has gone through cold reset. |
LPM_Ex-17-3 | SoC | After main domain is out of reset and to enable the communication from main domain to WKUP/MCU domain, DMSC must enable LPSC_WKUPMCU2MAIN, LPSC_MAIN2WKUPMCU, LPSC_DEBUG2DMSC, LPSC_MCU_DEBUG as per dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). |
LPM_Ex-17.5 | FW | - Enable LPSC_EMIF_CFG0 as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). - Re-configure DDR EMIF. - Send command to PMIC via WKUP_I2C0 to drive to 0 the board DDR_RET chip input. - Enable LPSC_EMIF_DATA0 as per PSC dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). - Do a DDR read to wake-up from self-refresh. |
LPM_Ex-18-01 | FW | Restore CTRLMMR_MAIN_DEVSTAT from DMSC RAM. NOTE: CTRLMMR_MAIN_BOOTCFG is not restorable. |
LPM_Ex-18-03a | DMSC-FW | Ensure all the PLLs and HSDIVs used in MAIN prior to entering MCU_ONLY mode are running. |
LPM_Ex-18-03b | DMSC-FW | - Restore the contents of all CTRLMMR_PADCONFIGi (i = 0 to 172) context from DDR. - Check in DMSC-RAM, the look-up table that show which CTRLMMR_PADCONFIGi (i = 0 to 172) were enable to detect wake-up event prior to enter MCU-ONLY mode. - DMSC (or potentially R5F) sets to power-up all PDs and ENABLE all the LPSCs (or as required per usage case and per as seen per context saving information). - Sequence power-up and LPSC enable as per dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). - Restore required context to MAIN domain from DDR and RESUME. |
LPM_Ex-18-04 | DMSC-FW | Check in DMSC-RAM, the look-up table and power-up the PDs and ENABLE LPSCs associated with all the potential wake-up events. Do this as per dependency constrains (see Section 5.2.2.3.1.3.3, LPSC Dependences Overview). |
LPM_Ex-18-06 | FW | -Remove self-refresh from DDR. - Send read command via DDR to board SDRAM for DDR-self-refresh to be removed. |
LPM_Ex-18-07 | FW | -DMSC to remove MAIN-IO-PM-DCH from isolation mode and move them to functional mode. |
LPM_Ex-24 | FW | The SoC can awake from Standby by any interrupt routed to A72 through GIC |
LpEx300 | SoC | |
LpEx301 | Ext-Dbg | Debugger is attached externally to the SoC JTAG pins. |
LpEx302 | SoC | a) The SoC Icemelter detects the activity in TCK/TRST pins in the wake-up domain. b) Icemelter will drive "Debug Activated" condition into DMSC, PSC. c) DMSC drives pin PMIC_POWER_EN1 = 1. Resulting in PMIC driving all SOC_MAIN supplies to ON. d) PSC starts the sequence to ENABLE DEBUGSS. e) "Debug Activated" also maps as Cortex.INT[24] in DMSC. |
LpEx303 | Ext-Dbg | - DMSC takes Cortex-INT[24] and executes the LP-MCU-Only-DBG ISR. - As part of the LP-MCU-Only-DBG ISR all the steps listed after this are performed. |
LpEx304 | - | - By now the PSC should have completed the DEBUGSS ENABLE process. - DAP accesses should be possible now. |
Table 5-1370 through Table 5-1375 present the sequences to exit the device LPM using the Step Label from Table 5-1369.
Step | Step Label |
---|---|
1 | LPM_Ex-01 |
2 | LPM_Ex-02 |
3 | LPM_Ex-03 |
4 | LPM_Ex-04.1a |
5 | LPM_Ex-04.2 |
7 | LPM_Ex-04.1c |
8 | LPM_Ex-05 |
9 | LPM_Ex-05.1b |
10 | LPM_Ex-17-2 |
11 | LPM_Ex-17-3 |
12 | LPM_Ex-17.5 |
13 | LPM_Ex-06 |
Device is now in ACTIVE mode |
Step | Step Label |
---|---|
1 | LPM_Ex-01 |
2 | LPM_Ex-02 |
3 | LPM_Ex-03a |
4 | LPM_Ex-04.1a |
5 | LPM_Ex-04.1b |
6 | LPM_Ex-04.1c |
7 | LPM_Ex-05 |
8 | LPM_Ex-05.1a |
9 | LPM_Ex-05.2 |
Device is now in MCU-ONLY.R5FSS_ACTIVE mode |
Step | Step Label |
---|---|
1 | LPM_Ex-07-1 |
2 | LPM_Ex-14 |
3 | LPM_Ex-14-2 |
4 | LPM_Ex-15-2-1 |
5 | LPM_Ex-15-2-2 |
6 | LPM_Ex-15-2-6 |
7 | LPM_Ex-15-2-7 |
8 | LPM_Ex-15-2-8 |
9 | LPM_Ex-15-2-9 |
10 | LPM_Ex-15-2-5 |
11 | LPM_Ex-16-2 |
12 | LPM_Ex-16-3 |
13 | LPM_Ex-16-4 |
14 | LPM_Ex-17-1 |
15 | LPM_Ex-17-2 |
16 | LPM_Ex-17-3 |
17 | LPM_Ex-18-01 |
18 | LPM_Ex-18-03a |
19 | LPM_Ex-17.5 |
20 | LPM_Ex-18-03b |
21 | LPM_Ex-18-07 |
22 | LPM_Ex-06 |
The device is now in ACTIVE mode |
Step | Step Label |
---|---|
1 | LPM_Ex-07-2 |
2 | LPM_Ex-15-2-6 |
3 | LPM_Ex-15-2-8 |
4 | LPM_Ex-11 |
The device is now in CDP-OFF mode | |
5 | LPM_Ex-12 |
6 | LPM_Ex-13 |
7 | LPM_Ex-17.5 |
8 | LPM_Ex-18-07 |
9 | LPM_Ex-10 |
10 | LPM_Ex-06 |
The device is now in ACTIVE mode |
Step | Step Label |
---|---|
1 | LPM_Ex-24 |
The device is now in ACTIVE mode |
Step | Step Label |
---|---|
1 | LpEx00.2 |
2 | LpEx301 |
3 | LpEx302 |
4 | LpEx303 |
5 | LpEx-16-2 |
6 | LpEx-16-3 |
7 | LpEx-15-2-9 |
8 | LpEx-17-1 |
9 | LpEx-17-2 |
10 | LpEx-17-3 |
11 | LpEx304 |