SPRUIU1C July   2020  – February 2024 DRA821U , DRA821U-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation From Texas Instruments
    3.     Support Resources
    4.     Glossary
    5.     Export Control Notice
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Device Overview
    2. 1.2 Device Block Diagram
    3. 1.3 Device Main Domain
      1. 1.3.1  Arm Cortex-A72 Subsystem
      2. 1.3.2  Arm Cortex-R5F Processor
      3. 1.3.3  Navigator Subsystem
      4. 1.3.4  Region-based Address Translation Module
      5. 1.3.5  Multicore Shared Memory Controller
      6. 1.3.6  DDR Subsystem
      7. 1.3.7  General Purpose Input/Output Interface
      8. 1.3.8  Inter-Integrated Circuit Interface
      9. 1.3.9  Improved Inter-Integrated Circuit Interface
      10. 1.3.10 Multi-channel Serial Peripheral Interface
      11. 1.3.11 Universal Asynchronous Receiver/Transmitter
      12. 1.3.12 Gigabit Ethernet Switch
      13. 1.3.13 Peripheral Component Interconnect Express Subsystem
      14. 1.3.14 Universal Serial Bus (USB) Subsystem
      15. 1.3.15 SerDes
      16. 1.3.16 General Purpose Memory Controller with Error Location Module
      17. 1.3.17 Multimedia Card/Secure Digital Interface
      18. 1.3.18 Enhanced Capture Module
      19. 1.3.19 Enhanced Pulse-Width Modulation Module
      20. 1.3.20 Enhanced Quadrature Encoder Pulse Module
      21. 1.3.21 Controller Area Network
      22. 1.3.22 Audio Tracking Logic
      23. 1.3.23 Multi-channel Audio Serial Port
      24. 1.3.24 Timers
      25. 1.3.25 Internal Diagnostics Modules
    4. 1.4 Device MCU Domain
      1. 1.4.1  MCU Arm Cortex-R5F Processor
      2. 1.4.2  MCU Region-based Address Translation Module
      3. 1.4.3  MCU Navigator Subsystem
      4. 1.4.4  MCU Analog-to-Digital Converter
      5. 1.4.5  MCU Inter-Integrated Circuit Interface
      6. 1.4.6  MCU Improved Inter-Integrated Circuit Interface
      7. 1.4.7  MCU Multi-channel Serial Peripheral Interface
      8. 1.4.8  MCU Universal Asynchronous Receiver/Transmitter
      9. 1.4.9  MCU Gigabit Ethernet Switch
      10. 1.4.10 MCU Octal Serial Peripheral Interface and HyperBus Memory Controller as a Flash Subsystem
      11. 1.4.11 MCU Controller Area Network
      12. 1.4.12 MCU Timers
      13. 1.4.13 MCU Internal Diagnostics Modules
    5. 1.5 Device WKUP Domain
      1. 1.5.1 WKUP Device Management and Security Controller
      2. 1.5.2 WKUP General Purpose Input/Output Interface
      3. 1.5.3 WKUP Inter-Integrated Circuit Interface
      4. 1.5.4 WKUP Universal Asynchronous Receiver/Transmitter
      5. 1.5.5 WKUP Internal Diagnostics Modules
    6. 1.6 Device Identification
  4. 2 Memory Map
    1. 2.1 MAIN Domain Memory Map
    2. 2.2 MCU Domain Memory Map
    3. 2.3 WKUP Domain Memory Map
    4. 2.4 Processors View Memory Map
    5. 2.5 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1 System Interconnect Overview
    2. 3.2 System Interconnect Integration
      1. 3.2.1 Interconnect Integration in WKUP Domain
      2. 3.2.2 Interconnect Integration in MCU Domain
      3. 3.2.3 Interconnect Integration in MAIN Domain
    3. 3.3 System Interconnect Functional Description
      1. 3.3.1 Master-Slave Connections
      2. 3.3.2 Quality of Service (QoS)
      3. 3.3.3 Route ID
      4. 3.3.4 Initiator-Side Security Controls and Firewalls
        1. 3.3.4.1 Initiator-Side Security Controls (ISC)
          1. 3.3.4.1.1 Special System Level Priv-ID
          2. 3.3.4.1.2 Priv ID and ISC Assignment
        2. 3.3.4.2 Firewalls (FW)
          1. 3.3.4.2.1 Peripheral Firewalls (FW)
          2. 3.3.4.2.2 Memory or Region-based Firewalls
            1. 3.3.4.2.2.1 Region Based Firewall Functional Description
          3. 3.3.4.2.3 Channelized Firewalls
            1. 3.3.4.2.3.1 Channelized Firewall Functional Description
      5. 3.3.5 Null Error Reporting
      6. 3.3.6 VBUSM_TIMEOUT_GASKET (MCU_TIMEOUT_64B2)
        1. 3.3.6.1 Overview and Feature List
          1. 3.3.6.1.1 Features Supported
          2. 3.3.6.1.2 Features Not Supported
        2. 3.3.6.2 Functional Description
          1. 3.3.6.2.1 Functional Operation
            1. 3.3.6.2.1.1  Overview
            2. 3.3.6.2.1.2  FIFOs
            3. 3.3.6.2.1.3  ID Allocator
            4. 3.3.6.2.1.4  Timer
            5. 3.3.6.2.1.5  Timeout Queue
            6. 3.3.6.2.1.6  Write Scoreboard
            7. 3.3.6.2.1.7  Read Scoreboard
            8. 3.3.6.2.1.8  Flush Mode
            9. 3.3.6.2.1.9  Flushing
            10. 3.3.6.2.1.10 Timeout Error Reporting
            11. 3.3.6.2.1.11 Command Timeout Error Reporting
            12. 3.3.6.2.1.12 Unexpected Response Reporting
            13. 3.3.6.2.1.13 Latency and Stalls
            14. 3.3.6.2.1.14 Bypass
            15. 3.3.6.2.1.15 Safety
        3. 3.3.6.3 Interrupt Conditions
          1. 3.3.6.3.1 Transaction Error Interrupt
            1. 3.3.6.3.1.1 Transaction Timeout
            2. 3.3.6.3.1.2 Unexpected Response
            3. 3.3.6.3.1.3 Command Timeout
        4. 3.3.6.4 Memory Map
          1. 3.3.6.4.1  Revision Register (Base Address + 0x00)
          2. 3.3.6.4.2  Configuration Register (Base Address + 0x04)
          3. 3.3.6.4.3  Info Register (Base Address + 0x08)
          4. 3.3.6.4.4  Enable Register (Base Address + 0x0C)
          5. 3.3.6.4.5  Flush Register (Base Address + 0x10)
          6. 3.3.6.4.6  Timeout Value Register (Base Address + 0x14)
          7. 3.3.6.4.7  Timer Register (Base Address + 0x18)
          8. 3.3.6.4.8  Error Interrupt Raw Status/Set Register (Base Address + 0x20)
          9. 3.3.6.4.9  Error Interrupt Enabled Status/Clear Register (Base Address + 0x24)
          10. 3.3.6.4.10 Error Interrupt Mask Set Register (Base Address + 0x28)
          11. 3.3.6.4.11 Error Interrupt Mask Clear Register (Base Address + 0x2C)
          12. 3.3.6.4.12 Timeout Error Info Register (Base Address + 0x30)
          13. 3.3.6.4.13 Unexpected Response Info Register (Base Address + 0x34)
          14. 3.3.6.4.14 Error Transaction Valid/Dir/RouteID Register (Base Address + 0x38)
          15. 3.3.6.4.15 Error Transaction Tag/CommandID Register (Base Address + 0x3C)
          16. 3.3.6.4.16 Error Transaction Bytecnt Register (Base Address + 0x40)
          17. 3.3.6.4.17 Error Transaction Upper Address Register (Base Address + 0x44)
          18. 3.3.6.4.18 Error Transaction Lower Address Register (Base Address + 0x48)
        5. 3.3.6.5 Integration Overview
          1. 3.3.6.5.1 Parameterization Requirements
        6. 3.3.6.6 I/O Description
          1. 3.3.6.6.1 Clockstop Idle
          2. 3.3.6.6.2 Flush
          3. 3.3.6.6.3 Module I/O
        7. 3.3.6.7 User’s Guide
          1. 3.3.6.7.1 Programmer’s Guide
            1. 3.3.6.7.1.1 Initialization
            2. 3.3.6.7.1.2 Software Flush
      7. 3.3.7 Timeout Gasket (TOG)
    4. 3.4 System Interconnect Registers
      1. 3.4.1 QoS Registers
      2. 3.4.2 Firewall Exception Registers
      3. 3.4.3 Firewall Region Registers
      4. 3.4.4 Null Error Reporting Registers
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Terminology
    2. 4.2 Boot Process
      1. 4.2.1 MCU ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 DMSC ROM Description
      3. 4.2.3 Boot Process Flow
      4. 4.2.4 MCU Only vs Normal Boot
    3. 4.3 Boot Mode Pins
      1. 4.3.1  MCU_BOOTMODE Pin Mapping
      2. 4.3.2  BOOTMODE Pin Mapping
        1. 4.3.2.1 Primary Boot Mode Selection
        2. 4.3.2.2 Backup Boot Mode Selection When MCU Only = 0
        3. 4.3.2.3 Primary Boot Mode Configuration
        4. 4.3.2.4 Backup Boot Mode Configuration
      3. 4.3.3  No-boot/Dev-boot Configuration
      4. 4.3.4  Hyperflash Boot Device Configuration
      5. 4.3.5  OSPI Boot Device Configuration
      6. 4.3.6  QSPI Boot Device Configuration
      7. 4.3.7  SPI Boot Device Configuration
      8. 4.3.8  xSPI Boot Device Configuration
      9. 4.3.9  I2C Boot Device Configuration
      10. 4.3.10 MMC/SD Card Boot Device Configuration
      11. 4.3.11 eMMC Boot Device Configuration
      12. 4.3.12 Ethernet Boot Device Configuration
      13. 4.3.13 USB Boot Device Configuration
      14. 4.3.14 PCIe Boot Device Configuration
      15. 4.3.15 UART Boot Device Configuration
      16. 4.3.16 PLL Configuration
        1. 4.3.16.1 MCU_PLL0, MCU_PLL2, Main PLL0, and Main PLL3
        2. 4.3.16.2 MCU_PLL1
        3. 4.3.16.3 Main PLL1
        4. 4.3.16.4 Main PLL2
        5. 4.3.16.5 HSDIV Values
        6. 4.3.16.6 190
    4. 4.4 Boot Parameter Tables
      1. 4.4.1  Common Header
      2. 4.4.2  PLL Setup
      3. 4.4.3  PCIe Boot Parameter Table
      4. 4.4.4  I2C Boot Parameter Table
      5. 4.4.5  OSPI/QSPI/SPI Boot Parameter Table
      6. 4.4.6  Ethernet Boot Parameter Table
      7. 4.4.7  USB Boot Parameter Table
      8. 4.4.8  MMCSD Boot Parameter Table
      9. 4.4.9  UART Boot Parameter Table
      10. 4.4.10 Hyperflash Boot Parameter Table
    5. 4.5 Boot Image Format
      1. 4.5.1 Overall Structure
      2. 4.5.2 X.509 Certificate
      3. 4.5.3 Organizational Identifier (OID)
      4. 4.5.4 X.509 Extensions Specific to Boot
        1. 4.5.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.5.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.5.5 Extended Boot Info Extension
        1. 4.5.5.1 Impact on HS Device
        2. 4.5.5.2 Extended Boot Info Details
        3. 4.5.5.3 Certificate / Component Types
        4. 4.5.5.4 Extended Boot Encryption Info
        5. 4.5.5.5 Component Ordering
        6. 4.5.5.6 Memory Load Sections Overlap with Executable Components
        7. 4.5.5.7 Device Type and Extended Boot Extension
      6. 4.5.6 Generating X.509 Certificates
        1. 4.5.6.1 Key Generation
          1. 4.5.6.1.1 Degenerate RSA Keys
        2. 4.5.6.2 Configuration Script
      7. 4.5.7 Image Data
    6. 4.6 Boot Modes
      1. 4.6.1 I2C Bootloader Operation
        1. 4.6.1.1 I2C Initialization Process
          1. 4.6.1.1.1 Block Size
          2. 4.6.1.1.2 226
        2. 4.6.1.2 I2C Loading Process
          1. 4.6.1.2.1 Loading a Boot Image From EEPROM
      2. 4.6.2 SPI Bootloader Operation
        1. 4.6.2.1 SPI Initialization Process
        2. 4.6.2.2 SPI Loading Process
      3. 4.6.3 QSPI Bootloader Operation
        1. 4.6.3.1 QSPI Initialization Process
        2. 4.6.3.2 QSPI Loading Process
      4. 4.6.4 OSPI Bootloader Operation
        1. 4.6.4.1 OSPI Initialization Process
        2. 4.6.4.2 OSPI Loading Process
      5. 4.6.5 PCIe Bootloader Operation
        1. 4.6.5.1 PCIe Initialization Process
        2. 4.6.5.2 PCIe Loading Process
      6. 4.6.6 Ethernet Bootloader Operation
        1. 4.6.6.1 Ethernet Initialization Process
        2. 4.6.6.2 Ethernet Loading Process
          1. 4.6.6.2.1 Ethernet Boot Data Formats
            1. 4.6.6.2.1.1 Limitations
            2. 4.6.6.2.1.2 BOOTP Request
              1. 4.6.6.2.1.2.1 MAC Header (DIX)
              2. 4.6.6.2.1.2.2 IPv4 Header
              3. 4.6.6.2.1.2.3 UDP Header
              4. 4.6.6.2.1.2.4 BOOTP Payload
              5. 4.6.6.2.1.2.5 TFTP
        3. 4.6.6.3 Ethernet Hand Over Process
      7. 4.6.7 USB Bootloader Operation
        1. 4.6.7.1 USB-Specific Attributes
          1. 4.6.7.1.1 DFU Device Mode
      8. 4.6.8 MMCSD Bootloader Operation
      9. 4.6.9 UART Bootloader Operation
        1. 4.6.9.1 Initialization Process
        2. 4.6.9.2 UART Loading Process
          1. 4.6.9.2.1 UART XMODEM
        3. 4.6.9.3 UART Hand-Over Process
    7. 4.7 Boot Memory Maps
      1. 4.7.1 Memory Layout/MPU
      2. 4.7.2 Global Memory Addresses Used by ROM Code
      3. 4.7.3 Memory Reserved by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 WKUP_CTRL_MMR0
        1. 5.1.1.1 WKUP_CTRL_MMR0 Overview
        2. 5.1.1.2 WKUP_CTRL_MMR0 Integration
        3. 5.1.1.3 WKUP_CTRL_MMR0 Functional Description
          1. 5.1.1.3.1 Description for WKUP_CTRL_MMR0 Register Types
            1. 5.1.1.3.1.1  Pad Configuration Registers
            2. 5.1.1.3.1.2  Kick Protection Registers
            3. 5.1.1.3.1.3  WKUP_CTRL_MMR0 Module Interrupts
            4. 5.1.1.3.1.4  Clock Selection Registers
            5. 5.1.1.3.1.5  Device Feature Registers
            6. 5.1.1.3.1.6  POK Module Registers
            7. 5.1.1.3.1.7  Power and Reset Related Registers
            8. 5.1.1.3.1.8  PRG Related Registers
            9. 5.1.1.3.1.9  Voltage Glitch Detect Control and Status Registers
            10. 5.1.1.3.1.10 I/O Debounce Control Registers
        4. 5.1.1.4 WKUP_CTRL_MMR0 Registers
      2. 5.1.2 MCU_CTRL_MMR0
        1. 5.1.2.1 MCU_CTRL_MMR0 Overview
        2. 5.1.2.2 MCU_CTRL_MMR0 Integration
        3. 5.1.2.3 MCU_CTRL_MMR0 Functional Description
          1. 5.1.2.3.1 Description for MCU_CTRL_MMR0 Register Types
            1. 5.1.2.3.1.1 Kick Protection Registers
            2. 5.1.2.3.1.2 MCU_CTRL_MMR0 Module Interrupts
            3. 5.1.2.3.1.3 Inter-processor Communication Registers
            4. 5.1.2.3.1.4 Timer I/O Muxing Control Registers
            5. 5.1.2.3.1.5 Clock Muxing and Division Registers
            6. 5.1.2.3.1.6 MCU_CPSW0 MAC Address Registers
        4. 5.1.2.4 MCU_CTRL_MMR0 Registers
        5. 5.1.2.5 MCU_SEC_MMR0_DBG_CTRL Registers
        6. 5.1.2.6 MCU_SEC_MMR0_BOOT_CTRL Registers
      3. 5.1.3 CTRL_MMR0
        1. 5.1.3.1 CTRL_MMR0 Overview
        2. 5.1.3.2 CTRL_MMR0 Integration
        3. 5.1.3.3 CTRL_MMR0 Functional Description
          1. 5.1.3.3.1 Description for CTRL_MMR0 Register Types
            1. 5.1.3.3.1.1  Pad Configuration Registers
            2. 5.1.3.3.1.2  Kick Protection Registers
            3. 5.1.3.3.1.3  CTRL_MMR0 Module Interrupts
            4. 5.1.3.3.1.4  Inter-processor Communication Registers
            5. 5.1.3.3.1.5  Timer I/O Muxing Control Registers
            6. 5.1.3.3.1.6  EHRPWM/EQEP Control and Status Registers
            7. 5.1.3.3.1.7  Clock Muxing and Division Registers
            8. 5.1.3.3.1.8  Ethernet Port Operation Control Registers
            9. 5.1.3.3.1.9  SERDES Lane Function Control Registers
            10. 5.1.3.3.1.10 DDRSS Dynamic Frequency Change Registers
        4. 5.1.3.4 CTRL_MMR0 Registers
        5. 5.1.3.5 SEC_MMR0_DBG_CTRL Registers
        6. 5.1.3.6 SEC_MMR0_BOOT_CTRL Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 Power Management Subsystems
        1. 5.2.2.1 Power Subsystems Overview
          1. 5.2.2.1.1 POK Overview
          2. 5.2.2.1.2 PRG / PRG_PP Overview
          3. 5.2.2.1.3 POR Overview
          4. 5.2.2.1.4 POK / PRG(_PP) /POR Overview
          5. 5.2.2.1.5 Timing
          6. 5.2.2.1.6 Restrictions
        2. 5.2.2.2 Power System Modules
          1. 5.2.2.2.1 Power OK (POK) Modules
            1. 5.2.2.2.1.1 POK Programming Model
              1. 5.2.2.2.1.1.1 POK Threshold Setting Programming Sequence
          2. 5.2.2.2.2 Power on Reset (POR) Module
            1. 5.2.2.2.2.1 POR Overview
            2. 5.2.2.2.2.2 POR Integration
            3. 5.2.2.2.2.3 POR Programming Model
          3. 5.2.2.2.3 PoR/Reset Generator (PRG_PP) Modules
            1. 5.2.2.2.3.1 PRG_PP Overview
            2. 5.2.2.2.3.2 PRG_PP Integration
            3. 5.2.2.2.3.3 PRG_PP Programming Model
          4. 5.2.2.2.4 Power Glitch Detect (PGD) Modules
          5. 5.2.2.2.5 Voltage and Thermal Manager (VTM)
            1. 5.2.2.2.5.1 VTM Overview
              1. 5.2.2.2.5.1.1 VTM Features
              2. 5.2.2.2.5.1.2 VTM Not Supported Features
            2. 5.2.2.2.5.2 VTM Integration
            3. 5.2.2.2.5.3 VTM Functional Description
              1. 5.2.2.2.5.3.1 VTM Temperature Status and Thermal Management
                1. 5.2.2.2.5.3.1.1 10-bit Temperature Values Versus Temperature
              2. 5.2.2.2.5.3.2 VTM Temperature Driven Alerts and Interrupts
              3. 5.2.2.2.5.3.3 VTM VID Voltage Domains
              4. 5.2.2.2.5.3.4 VTM Clocking
              5. 5.2.2.2.5.3.5 VTM Retention Interface
              6. 5.2.2.2.5.3.6 VTM ECC Aggregator
              7. 5.2.2.2.5.3.7 VTM Programming Model
                1. 5.2.2.2.5.3.7.1 VTM Maximum Temperature Outrange Alert
                2. 5.2.2.2.5.3.7.2 Temperature Monitor during Low Power Modes
                3. 5.2.2.2.5.3.7.3 Sensors Programming Sequences
              8. 5.2.2.2.5.3.8 AVS-Class0
          6. 5.2.2.2.6 Distributed Power Clock and Reset Controller (DPCR)
        3. 5.2.2.3 Power Control Modules
          1. 5.2.2.3.1 Power Sleep Controller and Local Power Sleep Controllers
            1. 5.2.2.3.1.1 PSC Terminology
            2. 5.2.2.3.1.2 PSC Features
            3. 5.2.2.3.1.3 PSC: Device Power-Management Layout
              1. 5.2.2.3.1.3.1 WKUP_PSC0 Device-Specific Information
              2. 5.2.2.3.1.3.2 PSC0 Device-Specific Information
              3. 5.2.2.3.1.3.3 LPSC Dependences Overview
            4. 5.2.2.3.1.4 PSC: Power Domain and Module States
              1. 5.2.2.3.1.4.1 Power Domain States
              2. 5.2.2.3.1.4.2 Module States
              3. 5.2.2.3.1.4.3 Local Reset
            5. 5.2.2.3.1.5 PSC: Executing State Transitions
              1. 5.2.2.3.1.5.1 Power Domain State Transitions
              2. 5.2.2.3.1.5.2 Module State Transitions
              3. 5.2.2.3.1.5.3 Concurrent Power Domain/Module State Transitions
              4. 5.2.2.3.1.5.4 Recommendations for Power Domain/Module Sequencing
            6. 5.2.2.3.1.6 PSC: Emulation Support in the PSC
            7. 5.2.2.3.1.7 PSC: A72SS, MSMC, MCU Cortex-R5F, C71SS0, and C66SS Subsystem Power-Up and Power-Down Sequences
              1. 5.2.2.3.1.7.1 ARMi_COREn Power State Transition
              2. 5.2.2.3.1.7.2 A72SS Power State Transition
              3. 5.2.2.3.1.7.3 GIC0 Sequencing to Support A72SS Power Management
              4. 5.2.2.3.1.7.4 MSMC0 Clkstop/Powerdown/Disconnect Sequencing
              5. 5.2.2.3.1.7.5 MCU Cortex-R5F Power Modes
          2. 5.2.2.3.2 Integrated Power Management (DMSC)
            1. 5.2.2.3.2.1 DMSC Power Management Overview
              1. 5.2.2.3.2.1.1 DMSC Power Management Features
      3. 5.2.3 Device Power States
        1. 5.2.3.1 Overview of Device Low-Power Modes
        2. 5.2.3.2 Voltage Domains
        3. 5.2.3.3 Power Domains
        4. 5.2.3.4 Clock Sources States
        5. 5.2.3.5 Wake-up Sources
        6. 5.2.3.6 Device Power States and Transitions
          1. 5.2.3.6.1 LPM Entry Sequences
          2. 5.2.3.6.2 LPM Exit Sequences
          3. 5.2.3.6.3 IO Retention
          4. 5.2.3.6.4 DDRSS Self-Refresh
      4. 5.2.4 Dynamic Power Management
        1. 5.2.4.1 AVS Support
        2. 5.2.4.2 Dynamic Frequency Scaling (DFS) Operations
      5. 5.2.5 Thermal Management
      6. 5.2.6 Registers
        1. 5.2.6.1 WKUP_VTM0 Registers
        2. 5.2.6.2 PSC Registers
    3. 5.3 Reset
      1. 5.3.1 Reset Overview
      2. 5.3.2 Reset Sources
      3. 5.3.3 Reset Status
      4. 5.3.4 Reset Control
      5. 5.3.5 BOOTMODE Pins
      6. 5.3.6 Reset Sequences
        1. 5.3.6.1 MCU_PORz Overview
        2. 5.3.6.2 MCU_PORz Sequence
        3. 5.3.6.3 MCU_RESETz Sequence
        4. 5.3.6.4 PORz Sequence
        5. 5.3.6.5 RESET_REQz Sequence
      7. 5.3.7 PLL Behavior on Reset
    4. 5.4 Clocking
      1. 5.4.1 Overview
      2. 5.4.2 Clock Inputs
        1. 5.4.2.1 Overview
        2. 5.4.2.2 Mapping of Clock Inputs
      3. 5.4.3 Clock Outputs
        1. 5.4.3.1 Observation Clock Pins
          1. 5.4.3.1.1 MCU_OBSCLK0 Pin
          2. 5.4.3.1.2 424
          3. 5.4.3.1.3 OBSCLK0, OBSCLK1, and OBSCLK2 Pins
        2. 5.4.3.2 System Clock Pins
          1. 5.4.3.2.1 MCU_SYSCLKOUT0
          2. 5.4.3.2.2 SYSCLKOUT0
      4. 5.4.4 Device Oscillators
        1. 5.4.4.1 Device Oscillators Integration
          1. 5.4.4.1.1 Oscillators with External Crystal
          2. 5.4.4.1.2 Internal RC Oscillator
        2. 5.4.4.2 Oscillator Clock Loss Detection
      5. 5.4.5 PLLs
        1. 5.4.5.1 WKUP and MCU Domains PLL Overview
        2. 5.4.5.2 MAIN Domain PLLs Overview
        3. 5.4.5.3 PLL Reference Clocks
          1. 5.4.5.3.1 PLLs in MCU Domain
          2. 5.4.5.3.2 PLLs in MAIN Domain
        4. 5.4.5.4 Generic PLL Overview
          1. 5.4.5.4.1 PLLs Output Clocks Parameters
            1. 5.4.5.4.1.1 PLLs Input Clocks
            2. 5.4.5.4.1.2 PLL Output Clocks
              1. 5.4.5.4.1.2.1 PLLTS16FFCLAFRAC2 Type Output Clocks
              2. 5.4.5.4.1.2.2 PLLTS16FFCLAFRACF Type Output Clocks
              3. 5.4.5.4.1.2.3 PLL Lock
              4. 5.4.5.4.1.2.4 HSDIVIDER
              5. 5.4.5.4.1.2.5 ICG Module
              6. 5.4.5.4.1.2.6 PLL Power Down
              7. 5.4.5.4.1.2.7 PLL Calibration
          2. 5.4.5.4.2 PLL Spread Spectrum Modulation Module
            1. 5.4.5.4.2.1 Definition of SSMOD
            2. 5.4.5.4.2.2 SSMOD Configuration
        5. 5.4.5.5 PLLs Device-Specific Information
          1. 5.4.5.5.1 SSMOD Related Bitfields Table
          2. 5.4.5.5.2 Clock Synthesis Inputs to the PLLs
          3. 5.4.5.5.3 Clock Output Parameter
          4. 5.4.5.5.4 Calibration Related Bitfields
        6. 5.4.5.6 PLL and PLL Controller Connection
        7. 5.4.5.7 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.5.7.1 PLL Initialization
            1. 5.4.5.7.1.1 Kick Protection Mechanism
            2. 5.4.5.7.1.2 PLL Initialization to PLL Mode
            3. 5.4.5.7.1.3 PLL Programming Requirements
          2. 5.4.5.7.2 HSDIV PLL Programming
          3. 5.4.5.7.3 PLL Controllers Programming - Dividers PLLDIVn and GO Operation
            1. 5.4.5.7.3.1 GO Operation
            2. 5.4.5.7.3.2 Software Steps to Modify PLLDIV Ratios
          4. 5.4.5.7.4 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
      6. 5.4.6 Registers
        1. 5.4.6.1 MCU_PLL0_CFG Registers
        2. 5.4.6.2 PLL0_CFG Registers
        3. 5.4.6.3 PLLCTRL0 Registers
  8. 6 Processors and Accelerators
    1. 6.1 Compute Cluster
      1. 6.1.1 Compute Cluster Overview
      2. 6.1.2 Compute Cluster Functional Description
        1. 6.1.2.1 Compute Cluster Memory Regions
        2. 6.1.2.2 Compute Cluster Firewalls
        3. 6.1.2.3 Compute Cluster ECC Aggregators
      3. 6.1.3 Compute Cluster Registers
    2. 6.2 Dual-A72 MPU Subsystem
      1. 6.2.1 A72SS Overview
        1. 6.2.1.1 A72SS Introduction
        2. 6.2.1.2 A72SS Features
      2. 6.2.2 A72SS Integration
      3. 6.2.3 A72SS Functional Description
        1. 6.2.3.1  A72SS Block Diagram
        2. 6.2.3.2  A72SS A72 Cluster
        3. 6.2.3.3  A72SS Interfaces and Async Bridges
        4. 6.2.3.4  A72SS Interrupts
          1. 6.2.3.4.1 A72SS Interrupt Inputs
          2. 6.2.3.4.2 A72SS Interrupt Outputs
        5. 6.2.3.5  A72SS Power Management, Clocking and Reset
          1. 6.2.3.5.1 A72SS Power Management
          2. 6.2.3.5.2 A72SS Clocking
        6. 6.2.3.6  A72SS Debug Support
        7. 6.2.3.7  A72SS Timestamps
        8. 6.2.3.8  A72SS Watchdog
        9. 6.2.3.9  A72SS Internal Diagnostics
          1. 6.2.3.9.1 A72SS ECC Aggregators During Low Power States
          2. 6.2.3.9.2 A72SS CBASS Diagnostics
          3. 6.2.3.9.3 A72SS SRAM Diagnostics
          4. 6.2.3.9.4 A72SS SRAM ECC Aggregator Configurations
        10. 6.2.3.10 A72SS Cache Pre-Warming
        11. 6.2.3.11 A72SS Boot
        12. 6.2.3.12 A72SS IPC with Other CPUs
      4. 6.2.4 A72SS Registers
        1. 6.2.4.1 Arm A72 Cluster Registers
        2. 6.2.4.2 A72SS ECC Aggregator Registers
          1. 6.2.4.2.1 A72SS CLUSTER ECC Registers
          2. 6.2.4.2.2 A72SS CORE0 ECC Registers
          3. 6.2.4.2.3 A72SS CORE1 ECC Registers
    3. 6.3 Dual-R5F MCU Subsystem
      1. 6.3.1 R5FSS Overview
        1. 6.3.1.1 R5FSS Features
        2. 6.3.1.2 R5FSS Not Supported Features
      2. 6.3.2 R5FSS Integration
        1. 6.3.2.1 R5FSS Integration in MCU Domain
        2. 6.3.2.2 R5FSS Integration in MAIN Domain
      3. 6.3.3 R5FSS Functional Description
        1. 6.3.3.1  R5FSS Block Diagram
        2. 6.3.3.2  R5FSS Cortex-R5F Core
          1. 6.3.3.2.1 L1 Caches
          2. 6.3.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.3.3.2.3 R5FSS Special Signals
        3. 6.3.3.3  R5FSS Interfaces
          1. 6.3.3.3.1 R5FSS Master Interfaces
          2. 6.3.3.3.2 R5FSS Slave Interfaces
        4. 6.3.3.4  R5FSS Power, Clocking and Reset
          1. 6.3.3.4.1 R5FSS Power
          2. 6.3.3.4.2 R5FSS Clocking
            1. 6.3.3.4.2.1 Changing MCU_R5FSS0 CPU Clock Frequency
          3. 6.3.3.4.3 R5FSS Reset
        5. 6.3.3.5  R5FSS Lockstep Error Detection Logic
          1. 6.3.3.5.1 CPU Output Compare Block
            1. 6.3.3.5.1.1 Operating Modes
            2. 6.3.3.5.1.2 Compare Block Active Mode
            3. 6.3.3.5.1.3 Self Test Mode
            4. 6.3.3.5.1.4 Compare Match Test
            5. 6.3.3.5.1.5 Compare Mismatch Test
            6. 6.3.3.5.1.6 Error Forcing Mode
            7. 6.3.3.5.1.7 Self Test Error Forcing Mode
          2. 6.3.3.5.2 Inactivity Monitor Block
            1. 6.3.3.5.2.1 Operating Modes
            2. 6.3.3.5.2.2 Compare Block Active Mode
            3. 6.3.3.5.2.3 Self Test Mode
            4. 6.3.3.5.2.4 Compare Match Test
            5. 6.3.3.5.2.5 Compare Mismatch Test
            6. 6.3.3.5.2.6 Error Forcing Mode
            7. 6.3.3.5.2.7 Self Test Error Forcing Mode
          3. 6.3.3.5.3 Polarity Inversion Logic
        6. 6.3.3.6  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.3.3.6.1 VIM Overview
          2. 6.3.3.6.2 VIM Interrupt Inputs
          3. 6.3.3.6.3 VIM Interrupt Outputs
          4. 6.3.3.6.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.3.3.6.5 VIM Interrupt Prioritization
          6. 6.3.3.6.6 VIM ECC Support
          7. 6.3.3.6.7 VIM Lockstep Mode
          8. 6.3.3.6.8 VIM IDLE State
          9. 6.3.3.6.9 VIM Interrupt Handling
            1. 6.3.3.6.9.1 Servicing IRQ Through Vector Interface
            2. 6.3.3.6.9.2 Servicing IRQ Through MMR Interface
            3. 6.3.3.6.9.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.3.3.6.9.4 Servicing FIQ
            5. 6.3.3.6.9.5 Servicing FIQ (Alternative)
        7. 6.3.3.7  R5FSS Region Address Translation (RAT)
          1. 6.3.3.7.1 RAT Overview
          2. 6.3.3.7.2 RAT Operation
          3. 6.3.3.7.3 RAT Error Logging
          4. 6.3.3.7.4 RAT Protection
        8. 6.3.3.8  R5FSS ECC Support
        9. 6.3.3.9  R5FSS Memory View
        10. 6.3.3.10 R5FSS Debug and Trace
        11. 6.3.3.11 R5FSS Boot Options
        12. 6.3.3.12 R5FSS Core Memory ECC Events
      4. 6.3.4 R5FSS Registers
        1. 6.3.4.1 R5FSS_CCMR5 Registers
        2. 6.3.4.2 R5FSS_CPU0_ECC_AGGR_CFG_REGS Registers
        3. 6.3.4.3 R5FSS_CPU1_ECC_AGGR_CFG_REGS Registers
        4. 6.3.4.4 R5FSS_VIM Registers
        5. 6.3.4.5 R5FSS_RAT Registers
        6. 6.3.4.6 R5FSS_EVNT_BUS_VBUSP_MMRS Registers
  9. 7 Interprocessor Communication
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
        3. 7.1.1.3 Mailbox Not Supported Features
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
        1. 7.2.1.1 Spinlock Not Supported Features
      2. 7.2.2 Spinlock Integration
      3. 7.2.3 Spinlock Functional Description
        1. 7.2.3.1 Spinlock Software Reset
        2. 7.2.3.2 Spinlock Power Management
        3. 7.2.3.3 About Spinlocks
        4. 7.2.3.4 Spinlock Functional Operation
      4. 7.2.4 Spinlock Programming Guide
        1. 7.2.4.1 Spinlock Low-level Programming Models
          1. 7.2.4.1.1 Surrounding Modules Global Initialization
          2. 7.2.4.1.2 Basic Spinlock Operations
            1. 7.2.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.4.1.2.2 Take and Release Spinlock
  10. 8 Memory Controllers
    1. 8.1 Multicore Shared Memory Controller (MSMC)
      1. 8.1.1 MSMC Overview
        1. 8.1.1.1 MSMC Not Supported Features
      2. 8.1.2 MSMC Integration
        1. 8.1.2.1 MSMC Integration in MAIN Domain
        2. 8.1.2.2 639
      3. 8.1.3 MSMC Functional Description
        1. 8.1.3.1  MSMC Block Diagram
        2. 8.1.3.2  MSMC On-Chip Memory Banking
        3. 8.1.3.3  MSMC Snoop Filter and Data Cache
          1. 8.1.3.3.1 Way Partitioning
          2. 8.1.3.3.2 Cache Size Configuration and Associativity
        4. 8.1.3.4  MSMC Access Protection Checks
        5. 8.1.3.5  MSMC Null Slave
        6. 8.1.3.6  MSMC Resource Arbitration
        7. 8.1.3.7  MSMC Error Detection and Correction
          1. 8.1.3.7.1 On-chip SRAM and Pipeline Data Protection
          2. 8.1.3.7.2 On-chip SRAM L3 Cache Tag and Snoop Filter Protection
          3. 8.1.3.7.3 On-chip SRAM Memory Mapped SRAM Snoop Filter Protection
          4. 8.1.3.7.4 Background Parity Refresh (Scrubbing)
        8. 8.1.3.8  MSMC Interrupts
          1. 8.1.3.8.1 Raw Interrupt Registers
          2. 8.1.3.8.2 Interrupt Enable Registers
          3. 8.1.3.8.3 Triggered and Enabled Interrupts
        9. 8.1.3.9  MSMC Memory Regions
        10. 8.1.3.10 MSMC Hardware Coherence
          1. 8.1.3.10.1 Snoop Filter Broadcast Mode
        11. 8.1.3.11 MSMC Quality-of-Service
        12. 8.1.3.12 MSMC Memory Regions Protection
        13. 8.1.3.13 MSMC Cache Tag View
      4. 8.1.4 MSMC Registers
    2. 8.2 DDR Subsystem (DDRSS)
      1. 8.2.1 DDRSS Overview
        1. 8.2.1.1 DDRSS Not Supported Features
      2. 8.2.2 DDRSS Environment
      3. 8.2.3 DDRSS Integration
        1. 8.2.3.1 DDRSS Integration in MAIN Domain
      4. 8.2.4 DDRSS Functional Description
        1. 8.2.4.1 DDRSS MSMC2DDR Bridge
          1. 8.2.4.1.1 VBUSM.C Threads
          2. 8.2.4.1.2 Class of Service (CoS)
          3. 8.2.4.1.3 AXI Write Data All-Strobes
          4. 8.2.4.1.4 Inline ECC for SDRAM Data
            1. 8.2.4.1.4.1 ECC Cache
            2. 8.2.4.1.4.2 ECC Statistics
          5. 8.2.4.1.5 Opcode Checking
          6. 8.2.4.1.6 Address Alias Prevention
          7. 8.2.4.1.7 Data Error Detection and Correction
          8. 8.2.4.1.8 AXI Bus Timeout
        2. 8.2.4.2 DDRSS Interrupts
        3. 8.2.4.3 DDRSS Memory Regions
        4. 8.2.4.4 DDRSS ECC Support
        5. 8.2.4.5 DDRSS Dynamic Frequency Change Interface
        6. 8.2.4.6 DDR Controller Functional Description
          1. 8.2.4.6.1  DDR PHY Interface (DFI)
          2. 8.2.4.6.2  Command Queue
            1. 8.2.4.6.2.1 Placement Logic
            2. 8.2.4.6.2.2 Command Selection Logic
          3. 8.2.4.6.3  Low Power Control
          4. 8.2.4.6.4  Transaction Processing
          5. 8.2.4.6.5  BIST Engine
          6. 8.2.4.6.6  ECC Engine
          7. 8.2.4.6.7  Address Mapping
          8. 8.2.4.6.8  Paging Policy
          9. 8.2.4.6.9  DDR Controller Initialization
          10. 8.2.4.6.10 Programming LPDDR4 Memories
            1. 8.2.4.6.10.1 Frequency Set Point (FSP)
              1. 8.2.4.6.10.1.1 FSP Mode Register Programming During Initialization
              2. 8.2.4.6.10.1.2 FSP Mode Register Programming During Normal Operation
              3. 8.2.4.6.10.1.3 FSP Mode Register Programming During Dynamic Frequency Scaling
            2. 8.2.4.6.10.2 Data Bus Inversion (DBI)
            3. 8.2.4.6.10.3 On-Die Termination
              1. 8.2.4.6.10.3.1 LPDDR4 DQ ODT
              2. 8.2.4.6.10.3.2 LPDDR4 CA ODT
            4. 8.2.4.6.10.4 Byte Lane Swapping
            5. 8.2.4.6.10.5 DQS Interval Oscillator
              1. 8.2.4.6.10.5.1 Oscillator State Machine
            6. 8.2.4.6.10.6 Per-Bank Refresh (PBR)
              1. 8.2.4.6.10.6.1 Normal Operation
              2. 8.2.4.6.10.6.2 Continuous Refresh Request Mode
        7. 8.2.4.7 DDR PHY Functional Description
          1. 8.2.4.7.1  Data Slice
          2. 8.2.4.7.2  Address Slice
            1. 8.2.4.7.2.1 Address Swapping
          3. 8.2.4.7.3  Address/Control Slice
          4. 8.2.4.7.4  Clock Slice
          5. 8.2.4.7.5  DDR PHY Initialization
          6. 8.2.4.7.6  DDR PHY Dynamic Frequency Scaling (DFS)
          7. 8.2.4.7.7  Chip Select and Frequency Based Register Settings
          8. 8.2.4.7.8  Low-Power Modes
          9. 8.2.4.7.9  Training Support
            1. 8.2.4.7.9.1 Write Leveling
            2. 8.2.4.7.9.2 Read Gate Training
            3. 8.2.4.7.9.3 Read Data Eye Training
            4. 8.2.4.7.9.4 Write DQ Training
            5. 8.2.4.7.9.5 CA Training
            6. 8.2.4.7.9.6 CS Training
          10. 8.2.4.7.10 Data Bus Inversion (DBI)
          11. 8.2.4.7.11 I/O Pad Calibration
          12. 8.2.4.7.12 DQS Error
        8. 8.2.4.8 PI Functional Description
          1. 8.2.4.8.1 PI Initialization
      5. 8.2.5 DDRSS Registers
        1. 8.2.5.1 DDR Subsystem Registers
        2. 8.2.5.2 DDR Controller Registers
        3. 8.2.5.3 PI Registers
        4. 8.2.5.4 DDR PHY Registers
        5. 8.2.5.5 DDRSS0_ECC_AGGR_CTL Registers
        6. 8.2.5.6 DDRSS0_ECC_AGGR_VBUS Registers
        7. 8.2.5.7 DDRSS0_ECC_AGGR_CFG Registers
    3. 8.3 Peripheral Virtualization Unit (PVU)
      1. 8.3.1 PVU Overview
        1. 8.3.1.1 PVU Features
        2. 8.3.1.2 PVU Parameters
        3. 8.3.1.3 PVU Not Supported Features
      2. 8.3.2 PVU Integration
      3. 8.3.3 PVU Functional Description
        1. 8.3.3.1  Functional Operation Overview
        2. 8.3.3.2  PVU Channels
        3. 8.3.3.3  TLB
        4. 8.3.3.4  TLB Entry
        5. 8.3.3.5  TLB Selection
        6. 8.3.3.6  DMA Classes
        7. 8.3.3.7  General virtIDs
        8. 8.3.3.8  TLB Lookup
        9. 8.3.3.9  TLB Miss
        10. 8.3.3.10 Multiple Matching Entries
        11. 8.3.3.11 TLB Disable
        12. 8.3.3.12 TLB Chaining
        13. 8.3.3.13 TLB Permissions
        14. 8.3.3.14 Translation
        15. 8.3.3.15 Memory Attributes
        16. 8.3.3.16 Faulted Transactions
        17. 8.3.3.17 Non-Virtual Transactions
        18. 8.3.3.18 Allowed virtIDs
        19. 8.3.3.19 Software Control
        20. 8.3.3.20 Fault Logging
        21. 8.3.3.21 Alignment Restrictions
      4. 8.3.4 PVU Registers
        1. 8.3.4.1 NAVSS_PVU_CFG Registers
        2. 8.3.4.2 NAVSS0_PVU_CFG_TLBIF Registers
    4. 8.4 Region-based Address Translation (RAT) Module
      1. 8.4.1 RAT Functional Description
        1. 8.4.1.1 RAT Availability
        2. 8.4.1.2 RAT Operation
        3. 8.4.1.3 RAT Error Logging
      2. 8.4.2 RAT Registers
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GIC)
        1. 9.2.1.1 GIC Overview
          1. 9.2.1.1.1 GIC Features
          2. 9.2.1.1.2 GIC Not Supported Features
        2. 9.2.1.2 GIC Integration
        3. 9.2.1.3 GIC Functional Description
          1. 9.2.1.3.1 GIC Block Diagram
          2. 9.2.1.3.2 Arm GIC-500
          3. 9.2.1.3.3 GIC Interrupt Types
          4. 9.2.1.3.4 GIC Interfaces
          5. 9.2.1.3.5 GIC Interrupt Outputs
          6. 9.2.1.3.6 GIC ECC Support
          7. 9.2.1.3.7 GIC AXI2VBUSM and VBUSM2AXI Bridges
        4. 9.2.1.4 GIC Registers
          1. 9.2.1.4.1 Arm GIC-500 Registers
          2. 9.2.1.4.2 GIC_ECC_AGGR Registers
      2. 9.2.2 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Integration
        1. 9.3.2.1 WKUP_GPIOMUX_INTRTR0 Integration
        2. 9.3.2.2 GPIOMUX_INTRTR0 Integration
        3. 9.3.2.3 MAIN2MCU_LVL_INTRTR0 Integration
        4. 9.3.2.4 MAIN2MCU_PLS_INTRTR0 Integration
      3. 9.3.3 INTRTR Registers
        1. 9.3.3.1 WKUP_GPIOMUX_INTRTR0 Registers
        2. 9.3.3.2 GPIOMUX_INTRTR0 Registers
        3. 9.3.3.3 MAIN2MCU_LVL_INTRTR0 Registers
        4. 9.3.3.4 MAIN2MCU_PLS_INTRTR0 Registers
    4. 9.4 Interrupt Sources
      1. 9.4.1 WKUP Domain Interrupt Maps
        1. 9.4.1.1 WKUP_DMSC0 Interrupt Map
        2. 9.4.1.2 WKUP_GPIOMUX_INTRTR0 Interrupt Map
        3. 9.4.1.3 WKUP_GPIO0_VIRT Interrupt Map
        4. 9.4.1.4 WKUP_ESM0 Interrupt Map
      2. 9.4.2 MCU Domain Interrupt Maps
        1. 9.4.2.1 MCU_R5FSS0_CORE0 Interrupt Map
        2. 9.4.2.2 MCU_R5FSS0_CORE1 Interrupt Map
        3. 9.4.2.3 MCU_ESM0 Interrupt Map
      3. 9.4.3 MAIN Domain Interrupt Maps
        1. 9.4.3.1 COMPUTE_CLUSTER0 Interrupt Map
          1. 9.4.3.1.1 GIC500 PPI Interrupt Map
          2. 9.4.3.1.2 GIC500 SPI Interrupt Map
          3. 9.4.3.1.3 SoC Event Output Interrupt Map
        2. 9.4.3.2 R5FSS0_CORE0 Interrupt Map
        3. 9.4.3.3 R5FSS0_CORE1 Interrupt Map
        4. 9.4.3.4 MAIN2MCU_LVL_INTRTR0 Interrupt Map
        5. 9.4.3.5 MAIN2MCU_PLS_INTRTR0 Interrupt Map
        6. 9.4.3.6 GPIOMUX_INTRTR0 Interrupt Map
        7. 9.4.3.7 GPIO0_VIRT Interrupt Map
        8. 9.4.3.8 ESM0 Interrupt Map
  12. 10Data Movement Architecture (DMA)
    1. 10.1 DMA Architecture
      1. 10.1.1 Overview
        1. 10.1.1.1  Navigator Subsystem
        2. 10.1.1.2  Ring Accelerator (RA)
        3. 10.1.1.3  Proxy
        4. 10.1.1.4  Secure Proxy
        5. 10.1.1.5  Interrupt Aggregator (INTA)
        6. 10.1.1.6  Interrupt Router (IR)
        7. 10.1.1.7  Unified DMA – Third Party Channel Controller (UDMA-C)
        8. 10.1.1.8  Unified Transfer Controller (UTC)
        9. 10.1.1.9  Data Routing Unit (DRU)
        10. 10.1.1.10 Unified DMA – Peripheral Root Complex (UDMA-P)
          1. 10.1.1.10.1 Channel Classes
        11. 10.1.1.11 Peripheral DMA (PDMA)
        12. 10.1.1.12 Embedded DMA
        13. 10.1.1.13 Definition of Terms
      2. 10.1.2 UDMA Hardware/Software Interface
        1. 10.1.2.1 Data Buffers
        2. 10.1.2.2 Descriptors
          1. 10.1.2.2.1 Host Packet Descriptor
          2. 10.1.2.2.2 Host Buffer Descriptor
          3. 10.1.2.2.3 Monolithic Packet Descriptor
          4. 10.1.2.2.4 Transfer Request Descriptor
        3. 10.1.2.3 Transfer Request Record
          1. 10.1.2.3.1 Overview
          2. 10.1.2.3.2 Addressing Algorithm
            1. 10.1.2.3.2.1 Linear Addressing (Forward)
          3. 10.1.2.3.3 Transfer Request Formats
          4. 10.1.2.3.4 Flags Field Definition
            1. 10.1.2.3.4.1 Type: TR Type Field
            2. 10.1.2.3.4.2 STATIC: Static Field Definition
            3. 10.1.2.3.4.3 EVENT_SIZE: Event Generation Definition
            4. 10.1.2.3.4.4 TRIGGER INFO: TR Triggers
            5. 10.1.2.3.4.5 TRIGGERX_TYPE: Trigger Type
            6. 10.1.2.3.4.6 TRIGGERX: Trigger Selection
            7. 10.1.2.3.4.7 CMD ID: Command ID Field Definition
            8. 10.1.2.3.4.8 Configuration Specific Flags Definition
          5. 10.1.2.3.5 TR Address and Size Attributes
            1. 10.1.2.3.5.1  ICNT0
            2. 10.1.2.3.5.2  ICNT1
            3. 10.1.2.3.5.3  ADDR
            4. 10.1.2.3.5.4  DIM1
            5. 10.1.2.3.5.5  ICNT2
            6. 10.1.2.3.5.6  ICNT3
            7. 10.1.2.3.5.7  DIM2
            8. 10.1.2.3.5.8  DIM3
            9. 10.1.2.3.5.9  DDIM1
            10. 10.1.2.3.5.10 DADDR
            11. 10.1.2.3.5.11 DDIM2
            12. 10.1.2.3.5.12 DDIM3
            13. 10.1.2.3.5.13 DICNT0
            14. 10.1.2.3.5.14 DICNT1
            15. 10.1.2.3.5.15 DICNT2
            16. 10.1.2.3.5.16 DICNT3
          6. 10.1.2.3.6 FMTFLAGS
            1. 10.1.2.3.6.1 AMODE: Addressing Mode Definition
              1. 10.1.2.3.6.1.1 Linear Addressing
              2. 10.1.2.3.6.1.2 Circular Addressing
            2. 10.1.2.3.6.2 DIR: Addressing Mode Direction Definition
            3. 10.1.2.3.6.3 ELTYPE: Element Type Definition
            4. 10.1.2.3.6.4 DFMT: Data Formatting Algorithm Definition
            5. 10.1.2.3.6.5 SECTR: Secondary Transfer Request Definition
              1. 10.1.2.3.6.5.1 Secondary TR Formats
              2. 10.1.2.3.6.5.2 Secondary TR FLAGS
                1. 10.1.2.3.6.5.2.1 SEC_TR_TYPE: Secondary TR Type Field
                2. 10.1.2.3.6.5.2.2 Multiple Buffer Interleave
            6. 10.1.2.3.6.6 AMODE SPECIFIC: Addressing Mode Field
              1. 10.1.2.3.6.6.1 Circular Address Mode Specific Flags
                1. 10.1.2.3.6.6.1.1 CBK0 and CBK1: Circular Block Size Selection
                2. 10.1.2.3.6.6.1.2 Amx: Addressing Mode Selection
            7. 10.1.2.3.6.7 Cache Flags
        4. 10.1.2.4 Transfer Response Record
          1. 10.1.2.4.1 STATUS Field Definition
            1. 10.1.2.4.1.1 STATUS_TYPE Definition
              1. 10.1.2.4.1.1.1 Transfer Error
              2. 10.1.2.4.1.1.2 Aborted Error
              3. 10.1.2.4.1.1.3 Submission Error
              4. 10.1.2.4.1.1.4 Unsupported Feature
              5. 10.1.2.4.1.1.5 Transfer Exception
              6. 10.1.2.4.1.1.6 Teardown Flush
        5. 10.1.2.5 Queues
          1. 10.1.2.5.1 Queue Types
            1. 10.1.2.5.1.1 Transmit Queues (Pass By Reference)
            2. 10.1.2.5.1.2 Transmit Queues (Pass By Value)
            3. 10.1.2.5.1.3 Transmit Completion Queues (Pass By Reference)
            4. 10.1.2.5.1.4 Transmit Completion Queues (Pass By Value)
            5. 10.1.2.5.1.5 Receive Queues
            6. 10.1.2.5.1.6 Free Descriptor Queues
            7. 10.1.2.5.1.7 Free Descriptor/Buffer Queues
          2. 10.1.2.5.2 Ring Accelerator Queues Implementation
      3. 10.1.3 Operational Description
        1. 10.1.3.1  Resource Allocation
        2. 10.1.3.2  Ring Accelerator Operation
          1. 10.1.3.2.1 Queue Initialization
          2. 10.1.3.2.2 Queuing packets (Exposed Ring Mode)
          3. 10.1.3.2.3 De-queuing packets (Exposed Ring Mode)
          4. 10.1.3.2.4 Queuing packets (Queue Mode)
          5. 10.1.3.2.5 De-queuing packets (Queue Mode)
        3. 10.1.3.3  UDMA Internal Transmit Channel Setup (All Packet Types)
        4. 10.1.3.4  UDMA Internal Transmit Channel Teardown (All Packet Types)
        5. 10.1.3.5  UDMA External Transmit Channel Setup
        6. 10.1.3.6  UDMA Transmit External Channel Teardown
        7. 10.1.3.7  UDMA-P Transmit Channel Pause
        8. 10.1.3.8  UDMA-P Transmit Operation (Host Packet Type)
        9. 10.1.3.9  UDMA-P Transmit Operation (Monolithic Packet)
        10. 10.1.3.10 UDMA Transmit Operation (TR Packet)
        11. 10.1.3.11 UDMA Transmit Operation (Direct TR)
        12. 10.1.3.12 UDMA Transmit Error/Exception Handling
          1. 10.1.3.12.1 Null Icnt0 Error
          2. 10.1.3.12.2 Unsupported TR Type
          3. 10.1.3.12.3 Bus Errors
        13. 10.1.3.13 UDMA Receive Channel Setup (All Packet Types)
        14. 10.1.3.14 UDMA Receive Channel Teardown
        15. 10.1.3.15 UDMA-P Receive Channel Pause
        16. 10.1.3.16 UDMA-P Receive Free Descriptor/Buffer Queue Setup (Host Packets)
        17. 10.1.3.17 UDMA-P Receive FlowID Firewall Operation
        18. 10.1.3.18 UDMA-P Receive Operation (Host Packet)
        19. 10.1.3.19 UDMA-P Receive Operation (Monolithic Packet)
        20. 10.1.3.20 UDMA Receive Operation (TR Packet)
        21. 10.1.3.21 UDMA Receive Operation (Direct TR)
        22. 10.1.3.22 UDMA Receive Error/Exception Handling
          1. 10.1.3.22.1 Error Conditions
            1. 10.1.3.22.1.1 Bus Errors
            2. 10.1.3.22.1.2 Null Icnt0 Error
            3. 10.1.3.22.1.3 Unsupported TR Type
          2. 10.1.3.22.2 Exception Conditions Exception Conditions
            1. 10.1.3.22.2.1 Descriptor Starvation
            2. 10.1.3.22.2.2 Protocol Errors
            3. 10.1.3.22.2.3 Dropped Packets
            4. 10.1.3.22.2.4 Reception of EOL Delimiter
            5. 10.1.3.22.2.5 EOP Asserted Prematurely (Short Packet)
            6. 10.1.3.22.2.6 EOP Asserted Late (Long Packets)
        23. 10.1.3.23 UTC Operation
        24. 10.1.3.24 UTC Receive Error/Exception Handling
          1. 10.1.3.24.1 Error Handling
            1. 10.1.3.24.1.1 Null Icnt0 Error
            2. 10.1.3.24.1.2 Unsupported TR Type
          2. 10.1.3.24.2 Exception Conditions
            1. 10.1.3.24.2.1 Reception of EOL Delimiter
            2. 10.1.3.24.2.2 EOP Asserted Prematurely (Short Packet)
            3. 10.1.3.24.2.3 EOP Asserted Late (Long Packets)
    2. 10.2 Navigator Subsystem (NAVSS)
      1. 10.2.1  Main Navigator Subsystem (NAVSS)
        1. 10.2.1.1 NAVSS Overview
        2. 10.2.1.2 NAVSS Integration
          1. 10.2.1.2.1 NAVSS Interrupt Router Configuration
          2. 10.2.1.2.2 Global Event Map
          3. 10.2.1.2.3 PSI-L System Thread Map (All NAVSS)
          4. 10.2.1.2.4 NAVSS VBUSM Route ID Table
        3. 10.2.1.3 NAVSS Functional Description
        4. 10.2.1.4 NAVSS Interrupt Configuration
          1. 10.2.1.4.1 NAVSS Event and Interrupt Flow
            1. 10.2.1.4.1.1 NAVSS Interrupts Description
            2. 10.2.1.4.1.2 Application Example
        5. 10.2.1.5 NAVSS Top-level Registers
          1. 10.2.1.5.1 NAVSS0_CFG Registers
          2. 10.2.1.5.2 INTR0_INTR_ROUTER_CFG Registers
          3. 10.2.1.5.3 VIRTID_CFG_MMRS Registers
      2. 10.2.2  MCU Navigator Subsystem (MCU NAVSS)
        1. 10.2.2.1 MCU NAVSS Overview
        2. 10.2.2.2 MCU NAVSS Integration
          1. 10.2.2.2.1  MCU NAVSS Interrupt Router Configuration
          2. 10.2.2.2.2  MCU NAVSS UDMASS Interrupt Aggregator Configuration
          3. 10.2.2.2.3  MCU NAVSS UDMA Configuration
          4. 10.2.2.2.4  MCU NAVSS Ring Accelerator Configuration
          5. 10.2.2.2.5  MCU NAVSS Proxy Configuration
          6. 10.2.2.2.6  MCU NAVSS Secure Proxy Configuration
          7. 10.2.2.2.7  Global Event Map
          8. 10.2.2.2.8  PSI-L System Thread Map (All NAVSS)
          9. 10.2.2.2.9  MCU NAVSS VBUSM Route ID Table
          10. 10.2.2.2.10 1006
        3. 10.2.2.3 MCU NAVSS Functional Description
        4. 10.2.2.4 MCU NAVSS Top-Level Registers
          1. 10.2.2.4.1 MCU_NAVSS0_CFG Registers
          2. 10.2.2.4.2 MCU_NAVSS0_UDMASS_ECCAGGR0 Registers
      3. 10.2.3  Unified DMA Controller (UDMA)
        1. 10.2.3.1 UDMA Overview
          1. 10.2.3.1.1 UDMA Features
          2. 10.2.3.1.2 UDMA Parameters
        2. 10.2.3.2 UDMA Integration
        3. 10.2.3.3 UDMA Functional Description
          1. 10.2.3.3.1 Block Diagram
          2. 10.2.3.3.2 General Functionality
            1. 10.2.3.3.2.1  Operational States
            2. 10.2.3.3.2.2  Tx Channel Allocation
            3. 10.2.3.3.2.3  Rx Channel Allocation
            4. 10.2.3.3.2.4  Tx Teardown
            5. 10.2.3.3.2.5  Rx Teardown
            6. 10.2.3.3.2.6  Tx Clock Stop
            7. 10.2.3.3.2.7  Rx Clock Stop
            8. 10.2.3.3.2.8  Rx Thread Enables
            9. 10.2.3.3.2.9  Events
              1. 10.2.3.3.2.9.1 Local Event Inputs
              2. 10.2.3.3.2.9.2 Inbound Tx PSI-L Events
              3. 10.2.3.3.2.9.3 Outbound Rx PSI-L Events
            10. 10.2.3.3.2.10 Emulation Control
          3. 10.2.3.3.3 Packet Oriented Transmit Operation
            1. 10.2.3.3.3.1 Packet Mode VBUSM Master Interface Command ID Selection
          4. 10.2.3.3.4 Packet Oriented Receive Operation
            1. 10.2.3.3.4.1 Rx Packet Drop
            2. 10.2.3.3.4.2 Rx Starvation and the Starvation Timer
          5. 10.2.3.3.5 Third Party Mode Operation
            1. 10.2.3.3.5.1 Events and Flow Control
              1. 10.2.3.3.5.1.1 Channel Triggering
              2. 10.2.3.3.5.1.2 Internal TR Completion Events
            2. 10.2.3.3.5.2 Transmit Operation
              1. 10.2.3.3.5.2.1 Transfer Request
              2. 10.2.3.3.5.2.2 Transfer Response
              3. 10.2.3.3.5.2.3 Data Transfer
              4. 10.2.3.3.5.2.4 Memory Interface Transactions
              5. 10.2.3.3.5.2.5 Error Handling
            3. 10.2.3.3.5.3 Receive Operation
              1. 10.2.3.3.5.3.1 Transfer Request
              2. 10.2.3.3.5.3.2 Transfer Response
              3. 10.2.3.3.5.3.3 Error Handling
            4. 10.2.3.3.5.4 Data Transfer
              1. 10.2.3.3.5.4.1 Memory Interface Transactions
              2. 10.2.3.3.5.4.2 Rx Packet Drop
        4. 10.2.3.4 UDMA Registers
          1. 10.2.3.4.1 UDMASS_UDMAP0_CFG Registers
          2. 10.2.3.4.2 UDMASS_UDMAP0_CFG_TCHAN Registers
          3. 10.2.3.4.3 UDMASS_UDMAP0_CFG_RCHAN Registers
          4. 10.2.3.4.4 UDMASS_UDMAP0_CFG_RFLOW Registers
          5. 10.2.3.4.5 UDMASS_UDMAP0_CFG_RCHANRT Registers
          6. 10.2.3.4.6 UDMASS_UDMAP0_CFG_TCHANRT Registers
      4. 10.2.4  Ring Accelerator (RINGACC)
        1. 10.2.4.1 RINGACC Overview
          1. 10.2.4.1.1 RINGACC Features
          2. 10.2.4.1.2 RINGACC Not Supported Features
          3. 10.2.4.1.3 RINGACC Parameters
        2. 10.2.4.2 RINGACC Integration
        3. 10.2.4.3 RINGACC Functional Description
          1. 10.2.4.3.1 Block Diagram
            1. 10.2.4.3.1.1  Configuration Registers
            2. 10.2.4.3.1.2  Source Command FIFO
            3. 10.2.4.3.1.3  Source Write Data FIFO
            4. 10.2.4.3.1.4  Source Read Data FIFO
            5. 10.2.4.3.1.5  Source Write Status FIFO
            6. 10.2.4.3.1.6  Main State Machine
            7. 10.2.4.3.1.7  Destination Command FIFO
            8. 10.2.4.3.1.8  Destination Write Data FIFO
            9. 10.2.4.3.1.9  Destination Read Data FIFO
            10. 10.2.4.3.1.10 Destination Write Status FIFO
          2. 10.2.4.3.2 RINGACC Functional Operation
            1. 10.2.4.3.2.1 Queue Modes
              1. 10.2.4.3.2.1.1 Ring Mode
              2. 10.2.4.3.2.1.2 Messaging Mode
              3. 10.2.4.3.2.1.3 Credentials Mode
              4. 10.2.4.3.2.1.4 Queue Manager Mode
              5. 10.2.4.3.2.1.5 Peek Support
              6. 10.2.4.3.2.1.6 Index Register Operation
            2. 10.2.4.3.2.2 VBUSM Slave Ring Operations
            3. 10.2.4.3.2.3 VBUSM Master Interface Command ID Selection
            4. 10.2.4.3.2.4 Ring Push Operation (VBUSM Write to Source Interface)
            5. 10.2.4.3.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
            6. 10.2.4.3.2.6 Host Doorbell Access
            7. 10.2.4.3.2.7 Queue Push Operation (VBUSM Write to Source Interface)
            8. 10.2.4.3.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
            9. 10.2.4.3.2.9 Mismatched Element Size Handling
          3. 10.2.4.3.3 Events
          4. 10.2.4.3.4 Bus Error Handling
          5. 10.2.4.3.5 Monitors
            1. 10.2.4.3.5.1 Threshold Monitor
            2. 10.2.4.3.5.2 Watermark Monitor
            3. 10.2.4.3.5.3 Starvation Monitor
            4. 10.2.4.3.5.4 Statistics Monitor
            5. 10.2.4.3.5.5 Overflow
            6. 10.2.4.3.5.6 Ring Update Port
            7. 10.2.4.3.5.7 Tracing
        4. 10.2.4.4 RINGACC Registers
          1. 10.2.4.4.1 NAVSS0_UDMASS_RINGACC0_CFG Registers
          2. 10.2.4.4.2 NAVSS0_UDMASS_RINGACC0_GCFG Registers
          3. 10.2.4.4.3 NAVSS0_UDMASS_RINGACC0_CFG_MON Registers
          4. 10.2.4.4.4 NAVSS0_UDMASS_RINGACC0_CFG_RT Registers
          5. 10.2.4.4.5 NAVSS0_UDMASS_RINGACC0_SRC_FIFOS Registers
      5. 10.2.5  Proxy
        1. 10.2.5.1 Proxy Overview
          1. 10.2.5.1.1 Proxy Features
          2. 10.2.5.1.2 Proxy Parameters
          3. 10.2.5.1.3 Proxy Not Supported Features
        2. 10.2.5.2 Proxy Integration
        3. 10.2.5.3 Proxy Functional Description
          1. 10.2.5.3.1  Targets
            1. 10.2.5.3.1.1 Ring Accelerator
          2. 10.2.5.3.2  Proxy Sizes
          3. 10.2.5.3.3  Proxy Interleaving
          4. 10.2.5.3.4  Proxy Host States
          5. 10.2.5.3.5  Proxy Host Channel Selection
          6. 10.2.5.3.6  Proxy Host Access
            1. 10.2.5.3.6.1 Proxy Host Writes
            2. 10.2.5.3.6.2 Proxy Host Reads
          7. 10.2.5.3.7  Permission Inheritance
          8. 10.2.5.3.8  Buffer Size
          9. 10.2.5.3.9  Error Events
          10. 10.2.5.3.10 Debug Reads
        4. 10.2.5.4 Proxy Registers
          1. 10.2.5.4.1 NAVSS0_PROXY0_CFG_BUF_CFG Registers
          2. 10.2.5.4.2 NAVSS0_PROXY0_BUF_CFG Registers
          3. 10.2.5.4.3 NAVSS0_PROXY_BUF Registers
          4. 10.2.5.4.4 NAVSS0_PROXY_TARGET0_DATA Registers
      6. 10.2.6  Secure Proxy
        1. 10.2.6.1 Secure Proxy Overview
          1. 10.2.6.1.1 Secure Proxy Features
          2. 10.2.6.1.2 Secure Proxy Parameters
          3. 10.2.6.1.3 Secure Proxy Not Supported Features
        2. 10.2.6.2 Secure Proxy Integration
        3. 10.2.6.3 Secure Proxy Functional Description
          1. 10.2.6.3.1  Targets
            1. 10.2.6.3.1.1 Ring Accelerator
          2. 10.2.6.3.2  Buffers
            1. 10.2.6.3.2.1 Proxy Credits
            2. 10.2.6.3.2.2 Proxy Private Word
            3. 10.2.6.3.2.3 Completion Byte
          3. 10.2.6.3.3  Proxy Thread Sizes
          4. 10.2.6.3.4  Proxy Thread Interleaving
          5. 10.2.6.3.5  Proxy States
          6. 10.2.6.3.6  Proxy Host Access
            1. 10.2.6.3.6.1 Proxy Host Writes
            2. 10.2.6.3.6.2 Proxy Host Reads
            3. 10.2.6.3.6.3 Buffer Accesses
            4. 10.2.6.3.6.4 Target Access
            5. 10.2.6.3.6.5 Error State
          7. 10.2.6.3.7  Permission Inheritance
          8. 10.2.6.3.8  Resource Association
          9. 10.2.6.3.9  Direction
          10. 10.2.6.3.10 Threshold Events
          11. 10.2.6.3.11 Error Events
          12. 10.2.6.3.12 Bus Errors and Credits
          13. 10.2.6.3.13 Debug
        4. 10.2.6.4 Secure Proxy Registers
          1. 10.2.6.4.1 NAVSS0_SEC_PROXY0_CFG_MMRS Registers
          2. 10.2.6.4.2 NAVSS0_SEC_PROXY0_CFG_RT Registers
          3. 10.2.6.4.3 NAVSS0_SEC_PROXY0_CFG_SCFG Registers
          4. 10.2.6.4.4 NAVSS0_SEC_PROXY0_SRC_TARGET_DATA Registers
      7. 10.2.7  Interrupt Aggregator (INTR_AGGR)
        1. 10.2.7.1 INTR_AGGR Overview
          1. 10.2.7.1.1 INTR_AGGR Features
          2. 10.2.7.1.2 INTR_AGGR Parameters
        2. 10.2.7.2 INTR_AGGR Integration
        3. 10.2.7.3 INTR_AGGR Functional Description
          1. 10.2.7.3.1 Submodule Descriptions
            1. 10.2.7.3.1.1 Status/Mask Registers
            2. 10.2.7.3.1.2 Interrupt Mapping Block
            3. 10.2.7.3.1.3 Global Event Input (GEVI) Counters
            4. 10.2.7.3.1.4 Local Event Input (LEVI) to Global Event Conversion
            5. 10.2.7.3.1.5 Global Event Multicast
          2. 10.2.7.3.2 General Functionality
            1. 10.2.7.3.2.1 Event to Interrupt Bit Steering
            2. 10.2.7.3.2.2 Interrupt Status
            3. 10.2.7.3.2.3 Interrupt Masked Status
            4. 10.2.7.3.2.4 Enabling/Disabling Individual Interrupt Source Bits
            5. 10.2.7.3.2.5 Interrupt Output Generation
            6. 10.2.7.3.2.6 Global Event Counting
            7. 10.2.7.3.2.7 Local Event to Global Event Conversion
            8. 10.2.7.3.2.8 Global Event Multicast
        4. 10.2.7.4 INTR_AGGR Registers
          1. 10.2.7.4.1  MODSS_INTA_CFG Registers
          2. 10.2.7.4.2  MODSS_INTA_CFG_IMAP Registers
          3. 10.2.7.4.3  MODSS_INTA_CFG_INTR Registers
          4. 10.2.7.4.4  UDMASS_INTA0_CFG Registers
          5. 10.2.7.4.5  UDMASS_INTA0_CFG_INTR Registers
          6. 10.2.7.4.6  UDMASS_INTA0_CFG_IMAP Registers
          7. 10.2.7.4.7  UDMASS_INTA0_CFG_L2G Registers
          8. 10.2.7.4.8  UDMASS_INTA0_CFG_MCAST Registers
          9. 10.2.7.4.9  UDMASS_INTA0_CFG_GCNTCFG Registers
          10. 10.2.7.4.10 UDMASS_INTA0_CFG_GCNTRTI Registers
      8. 10.2.8  Packet Streaming Interface Link (PSI-L)
        1. 10.2.8.1 PSI-L Overview
        2. 10.2.8.2 PSI-L Functional Description
          1. 10.2.8.2.1 PSI-L Introduction
          2. 10.2.8.2.2 PSI-L Operation
            1. 10.2.8.2.2.1 Event Transport
            2. 10.2.8.2.2.2 Threads
            3. 10.2.8.2.2.3 Arbitration Protocol
            4. 10.2.8.2.2.4 Thread Configuration
              1. 10.2.8.2.2.4.1 Thread Pairing
                1. 10.2.8.2.2.4.1.1 Configuration Transaction Pairing
              2. 10.2.8.2.2.4.2 Configuration Registers Region
        3. 10.2.8.3 PSI-L Configuration Registers
        4. 10.2.8.4 PSI-L CFG_PROXY Registers
      9. 10.2.9  PSIL Subsystem (PSILSS)
        1. 10.2.9.1 PSILSS Overview
          1. 10.2.9.1.1 PSILSS Features
        2. 10.2.9.2 PSILSS Functional Description
          1. 10.2.9.2.1 PSILSS Basic Operation
          2. 10.2.9.2.2 PSILSS Event Routing
          3. 10.2.9.2.3 PSILSS Link Down Detection
          4. 10.2.9.2.4 PSILSS Configuration
        3. 10.2.9.3 PSILSS Registers
          1. 10.2.9.3.1 PDMA_USART_PSILSS0 Registers
          2. 10.2.9.3.2 PDMA_SPI_PSILSS0 Registers
      10. 10.2.10 NAVSS North Bridge (NB)
        1. 10.2.10.1 NB Overview
          1. 10.2.10.1.1 Features Supported
          2. 10.2.10.1.2 NB Parameters
            1. 10.2.10.1.2.1 Compliance to Standards
            2. 10.2.10.1.2.2 Features Not Supported
        2. 10.2.10.2 NB Functional Description
          1. 10.2.10.2.1  VBUSM Slave Interfaces
          2. 10.2.10.2.2  VBUSM Master Interface
          3. 10.2.10.2.3  VBUSM.C Interfaces
            1. 10.2.10.2.3.1 Multi-Threading
            2. 10.2.10.2.3.2 Write Command Crediting
            3. 10.2.10.2.3.3 Early Credit Response
            4. 10.2.10.2.3.4 Priority Escalation
          4. 10.2.10.2.4  Source M2M Bridges
          5. 10.2.10.2.5  Destination M2M Bridge
          6. 10.2.10.2.6  M2C Bridge
          7. 10.2.10.2.7  Memory Attribute Tables
          8. 10.2.10.2.8  Outstanding Read Data Limiter
          9. 10.2.10.2.9  Ordering
          10. 10.2.10.2.10 Quality of Service
          11. 10.2.10.2.11 IDLE Behavior
          12. 10.2.10.2.12 Clock Power Management
        3. 10.2.10.3 NB Registers
          1. 10.2.10.3.1 NAVSS0_NBSS_CFG_REGS0_MMRS Registers
          2. 10.2.10.3.2 NAVSS0_NBSS_NB_CFG_MMRS Registers
    3. 10.3 Peripheral DMA (PDMA)
      1. 10.3.1 PDMA Controller
        1. 10.3.1.1 PDMA Overview
          1. 10.3.1.1.1 PDMA Features
            1. 10.3.1.1.1.1  MCU_PDMA0 (MCU_PDMA_MISC_G0) Features
            2. 10.3.1.1.1.2  MCU_PDMA1 (MCU_PDMA_MISC_G1) Features
            3. 10.3.1.1.1.3  MCU_PDMA2 (MCU_PDMA_MISC_G2) Features
            4. 10.3.1.1.1.4  MCU_PDMA3 (MCU_PDMA_ADC) Features
            5. 10.3.1.1.1.5  PDMA2 (PDMA_DEBUG_CCMCU) Features
            6. 10.3.1.1.1.6  PDMA5 (PDMA_MCAN) Features
            7. 10.3.1.1.1.7  PDMA6 (PDMA_MCASP_G0) Features
            8. 10.3.1.1.1.8  PDMA9 (PDMA_SPI_G0) Features
            9. 10.3.1.1.1.9  PDMA10 (PDMA_SPI_G1) Features
            10. 10.3.1.1.1.10 PDMA13 (PDMA_USART_G0) Features
            11. 10.3.1.1.1.11 PDMA14 (PDMA_USART_G1) Features
            12. 10.3.1.1.1.12 PDMA15 (PDMA_USART_G2) Features
        2. 10.3.1.2 PDMA Integration
          1. 10.3.1.2.1 PDMA Integration in MCU Domain
          2. 10.3.1.2.2 PDMA Integration in MAIN Domain
        3. 10.3.1.3 PDMA Functional Description
          1. 10.3.1.3.1 PDMA Functional Blocks
            1. 10.3.1.3.1.1 Scheduler
            2. 10.3.1.3.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 10.3.1.3.1.3 Tx DMA Unit (Tx Engine)
            4. 10.3.1.3.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 10.3.1.3.1.5 Rx DMA Unit (Rx Engine)
          2. 10.3.1.3.2 PDMA General Functionality
            1. 10.3.1.3.2.1 Operational States
            2. 10.3.1.3.2.2 Clock Stop
            3. 10.3.1.3.2.3 Emulation Control
          3. 10.3.1.3.3 PDMA Events and Flow Control
            1. 10.3.1.3.3.1 Channel Types
              1. 10.3.1.3.3.1.1 X-Y FIFO Mode
              2. 10.3.1.3.3.1.2 MCAN Mode
              3. 10.3.1.3.3.1.3 AASRC Mode
              4. 10.3.1.3.3.1.4 1288
            2. 10.3.1.3.3.2 Channel Triggering
            3. 10.3.1.3.3.3 Completion Events
          4. 10.3.1.3.4 PDMA Transmit Operation
            1. 10.3.1.3.4.1 Destination (Tx) Channel Allocation
            2. 10.3.1.3.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 10.3.1.3.4.3 Destination Channel Initialization
              1. 10.3.1.3.4.3.1 PSI-L Destination Thread Pairing
              2. 10.3.1.3.4.3.2 Static Transfer Request Setup
              3. 10.3.1.3.4.3.3 1297
              4. 10.3.1.3.4.3.4 PSI-L Destination Thread Enables
            4. 10.3.1.3.4.4 Data Transfer
              1. 10.3.1.3.4.4.1 X-Y FIFO Mode Channel
                1. 10.3.1.3.4.4.1.1 X-Y FIFO Burst Mode
              2. 10.3.1.3.4.4.2 MCAN Mode Channel
                1. 10.3.1.3.4.4.2.1 MCAN Burst Mode
              3. 10.3.1.3.4.4.3 AASRC Mode Channel
            5. 10.3.1.3.4.5 Tx Pause
            6. 10.3.1.3.4.6 Tx Teardown
            7. 10.3.1.3.4.7 Tx Channel Reset
            8. 10.3.1.3.4.8 Tx Debug/State Registers
          5. 10.3.1.3.5 PDMA Receive Operation
            1. 10.3.1.3.5.1 Source (Rx) Channel Allocation
            2. 10.3.1.3.5.2 Source Channel Initialization
              1. 10.3.1.3.5.2.1 PSI-L Source Thread Pairing
              2. 10.3.1.3.5.2.2 Static Transfer Request Setup
              3. 10.3.1.3.5.2.3 PSI-L Source Thread Enables
            3. 10.3.1.3.5.3 Data Transfer
              1. 10.3.1.3.5.3.1 X-Y FIFO Mode Channel
              2. 10.3.1.3.5.3.2 MCAN Mode Channel
                1. 10.3.1.3.5.3.2.1 MCAN Burst Mode
              3. 10.3.1.3.5.3.3 AASRC Mode Channel
            4. 10.3.1.3.5.4 Rx Pause
            5. 10.3.1.3.5.5 Rx Teardown
            6. 10.3.1.3.5.6 Rx Channel Reset
            7. 10.3.1.3.5.7 Rx Debug/State Register
          6. 10.3.1.3.6 PDMA ECC Support
        4. 10.3.1.4 PDMA Registers
          1. 10.3.1.4.1 PDMA5 ECC Registers
          2. 10.3.1.4.2 PDMA9 ECC Registers
          3. 10.3.1.4.3 PDMA10 ECC Registers
          4. 10.3.1.4.4 PDMA PSI-L TX Configuration Registers
          5. 10.3.1.4.5 PDMA PSI-L RX Configuration Registers
      2. 10.3.2 PDMA Sources
        1. 10.3.2.1 MCU Domain PDMA Event Maps
          1. 10.3.2.1.1 MCU_PDMA_MISC_G0 Event Map
          2. 10.3.2.1.2 MCU_PDMA_MISC_G1 Event Map
          3. 10.3.2.1.3 MCU_PDMA_MISC_G2 Event Map
          4. 10.3.2.1.4 MCU_PDMA_ADC Event Map
        2. 10.3.2.2 MAIN Domain PDMA Event Maps
          1. 10.3.2.2.1 PDMA_DEBUG_CCMCU Event Map
          2. 10.3.2.2.2 PDMA_MCAN Event Map
          3. 10.3.2.2.3 PDMA_MCASP_G0 Event Map
          4. 10.3.2.2.4 PDMA_SPI_G0 Event Map
          5. 10.3.2.2.5 PDMA_SPI_G1 Event Map
          6. 10.3.2.2.6 PDMA_USART_G0 Event Map
          7. 10.3.2.2.7 PDMA_USART_G1 Event Map
          8. 10.3.2.2.8 PDMA_USART_G2 Event Map
  13. 11Time Sync
    1. 11.1 Time Sync Module (CPTS)
      1. 11.1.1 CPTS Overview
        1. 11.1.1.1 CPTS Features
        2. 11.1.1.2 CPTS Not Supported Features
      2. 11.1.2 CPTS Integration
      3. 11.1.3 CPTS Functional Description
        1. 11.1.3.1  CPTS Architecture
        2. 11.1.3.2  CPTS Initialization
        3. 11.1.3.3  32-bit Time Stamp Value
        4. 11.1.3.4  64-bit Time Stamp Value
          1. 11.1.3.4.1 64-Bit Timestamp Nudge
          2. 11.1.3.4.2 64-bit Timestamp PPM
        5. 11.1.3.5  Event FIFO
        6. 11.1.3.6  Timestamp Compare Output
          1. 11.1.3.6.1 Non-Toggle Mode
          2. 11.1.3.6.2 Toggle Mode
        7. 11.1.3.7  Timestamp Sync Output
        8. 11.1.3.8  Timestamp GENF Output
          1. 11.1.3.8.1 GENFn Nudge
          2. 11.1.3.8.2 GENFn PPM
        9. 11.1.3.9  Time Sync Events
          1. 11.1.3.9.1 Time Stamp Push Event
          2. 11.1.3.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 11.1.3.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 11.1.3.9.4 Hardware Time Stamp Push Event
        10. 11.1.3.10 Timestamp Compare Event
        11. 11.1.3.11 CPTS Interrupt Handling
      4. 11.1.4 CPTS Registers
    2. 11.2 Timer Manager
      1. 11.2.1 Timer Manager Overview
        1. 11.2.1.1 Timer Manager Features
        2. 11.2.1.2 Timer Manager Not Supported Features
      2. 11.2.2 Timer Manager Integration
      3. 11.2.3 Timer Manager Functional Description
        1. 11.2.3.1 Timer Manager Function Overview
        2. 11.2.3.2 Timer Counter
          1. 11.2.3.2.1 Timer Counter Rollover
        3. 11.2.3.3 Timer Control Module (FSM)
        4. 11.2.3.4 Timer Reprogramming
          1. 11.2.3.4.1 Periodic Hardware Timers
        5. 11.2.3.5 Event FIFO
        6. 11.2.3.6 Output Event Lookup (OES RAM)
      4. 11.2.4 Timer Manager Programming Guide
        1. 11.2.4.1 Timer Manager Low-level Programming Models
          1. 11.2.4.1.1 Surrounding Modules Global Initialization
          2. 11.2.4.1.2 Initialization Sequence
          3. 11.2.4.1.3 Real-time Operating Requirements
            1. 11.2.4.1.3.1 Timer Touch
            2. 11.2.4.1.3.2 Timer Disable
            3. 11.2.4.1.3.3 Timer Enable
          4. 11.2.4.1.4 Power Up/Power Down Sequence
      5. 11.2.5 Timer Manager Registers
        1. 11.2.5.1 TIMERMGR_CFG_CFG Registers
        2. 11.2.5.2 TIMERMGR_CFG_OES Registers
        3. 11.2.5.3 TIMERMGR_CFG_TIMERS Registers
    3. 11.3 Time Sync and Compare Events
      1. 11.3.1 Time Sync Architecture
        1. 11.3.1.1 Time Sync Architecture Overview
      2. 11.3.2 Time Sync Routers
        1. 11.3.2.1 Time Sync Routers Overview
        2. 11.3.2.2 Time Sync Routers Integration
          1. 11.3.2.2.1 TIMESYNC_INTRTR0 Integration
          2. 11.3.2.2.2 CMPEVT_INTRTR0 Integration
        3. 11.3.2.3 Time Sync Routers Registers
          1. 11.3.2.3.1 TIMESYNC_INTRTR0 Registers
          2. 11.3.2.3.2 CMPEVT_INTRTR0 Registers
      3. 11.3.3 Time Sync Event Sources
        1. 11.3.3.1 CMPEVT_INTRTR0 Event Map
        2. 11.3.3.2 TIMESYNC_INTRTR0 Event Map
        3. 11.3.3.3 DMSS0 Sync Event Map
        4. 11.3.3.4 PCIE1 Sync Event Map
        5. 11.3.3.5 MCU_CPSW0 Sync Event Map
        6. 11.3.3.6 CPSW0 Sync Event Map
        7. 11.3.3.7 I/O Sync Event Map
  14. 12Peripherals
    1. 12.1 General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Not Supported Features
        2. 12.1.1.2 ADC Environment
          1. 12.1.1.2.1 ADC Interface Signals
        3. 12.1.1.3 ADC Integration
          1. 12.1.1.3.1 ADC Integration in MCU Domain
        4. 12.1.1.4 ADC Functional Description
          1. 12.1.1.4.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.4.1.1 Step Enable
            2. 12.1.1.4.1.2 Step Configuration
              1. 12.1.1.4.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.4.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.4.1.2.3 Averaging of Samples
              4. 12.1.1.4.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.4.1.2.5 Differential Control
              6. 12.1.1.4.1.2.6 FIFO Select
              7. 12.1.1.4.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.4.1.3 Open Delay and Sample Delay
              1. 12.1.1.4.1.3.1 Open Delay
              2. 12.1.1.4.1.3.2 Sample Delay
            4. 12.1.1.4.1.4 Interrupts
            5. 12.1.1.4.1.5 Power Management
            6. 12.1.1.4.1.6 DMA Requests
          2. 12.1.1.4.2 ADC AFE Functional Description
            1. 12.1.1.4.2.1 AFE Functional Block Diagram
            2. 12.1.1.4.2.2 ADC GPI Integration
          3. 12.1.1.4.3 ADC FIFOs and DMA
            1. 12.1.1.4.3.1 FIFOs
            2. 12.1.1.4.3.2 DMA
          4. 12.1.1.4.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.4.4.1 Testing ECC Error Injection
          5. 12.1.1.4.5 ADC Functional Internal Diagnostic Debug Mode
        5. 12.1.1.5 ADC Programming Guide
          1. 12.1.1.5.1 ADC Low-Level Programming Models
            1. 12.1.1.5.1.1 Global Initialization
              1. 12.1.1.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.1.5.1.1.2 General Programming Model
            2. 12.1.1.5.1.2 During Operation
        6. 12.1.1.6 ADC Registers
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Not Supported Features
        2. 12.1.2.2 GPIO Environment
          1. 12.1.2.2.1 GPIO Interface Signals
        3. 12.1.2.3 GPIO Integration
          1. 12.1.2.3.1 GPIO Integration in WKUP Domain
          2. 12.1.2.3.2 GPIO Integration in MAIN Domain
        4. 12.1.2.4 GPIO Functional Description
          1. 12.1.2.4.1 GPIO Block Diagram
          2. 12.1.2.4.2 GPIO Function
          3. 12.1.2.4.3 GPIO Interrupt and Event Generation
            1. 12.1.2.4.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.4.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.4.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.4.4 GPIO Interrupt Connectivity
          5. 12.1.2.4.5 GPIO DeepSleep Mode
          6. 12.1.2.4.6 GPIO Emulation Halt Operation
        5. 12.1.2.5 GPIO Programming Guide
          1. 12.1.2.5.1 GPIO Low-Level Programming Models
            1. 12.1.2.5.1.1 Global Initialization
              1. 12.1.2.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.2.5.1.1.2 GPIO Module Global Initialization
            2. 12.1.2.5.1.2 GPIO Operational Modes Configuration
              1. 12.1.2.5.1.2.1 GPIO Read Input Register
              2. 12.1.2.5.1.2.2 GPIO Set Bit Function
              3. 12.1.2.5.1.2.3 GPIO Clear Bit Function
        6. 12.1.2.6 GPIO Registers
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Not Supported Features
        2. 12.1.3.2 I2C Environment
          1. 12.1.3.2.1 I2C Typical Application
            1. 12.1.3.2.1.1 I2C Pins for Typical Connections in I2C Mode
            2. 12.1.3.2.1.2 I2C Interface Typical Connections
            3. 12.1.3.2.1.3 1501
          2. 12.1.3.2.2 I2C Typical Connection Protocol and Data Format
            1. 12.1.3.2.2.1  I2C Serial Data Format
            2. 12.1.3.2.2.2  I2C Data Validity
            3. 12.1.3.2.2.3  I2C Start and Stop Conditions
            4. 12.1.3.2.2.4  I2C Addressing
              1. 12.1.3.2.2.4.1 Data Transfer Formats in F/S Mode
              2. 12.1.3.2.2.4.2 Data Transfer Format in HS Mode
            5. 12.1.3.2.2.5  I2C Controller Transmitter
            6. 12.1.3.2.2.6  I2C Controller Receiver
            7. 12.1.3.2.2.7  I2C Target Transmitter
            8. 12.1.3.2.2.8  I2C Target Receiver
            9. 12.1.3.2.2.9  I2C Bus Arbitration
            10. 12.1.3.2.2.10 I2C Clock Generation and Synchronization
        3. 12.1.3.3 I2C Integration
          1. 12.1.3.3.1 I2C Integration in WKUP Domain
          2. 12.1.3.3.2 I2C Integration in MCU Domain
          3. 12.1.3.3.3 I2C Integration in MAIN Domain
        4. 12.1.3.4 I2C Functional Description
          1. 12.1.3.4.1 I2C Block Diagram
          2. 12.1.3.4.2 I2C Clocks
            1. 12.1.3.4.2.1 I2C Clocking
            2. 12.1.3.4.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.4.3 I2C Software Reset
          4. 12.1.3.4.4 I2C Power Management
          5. 12.1.3.4.5 I2C Interrupt Requests
          6. 12.1.3.4.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.4.7 I2C FIFO Management
            1. 12.1.3.4.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.4.7.2 I2C FIFO Polling Mode
            3. 12.1.3.4.7.3 I2C Draining Feature
          8. 12.1.3.4.8 I2C Noise Filter
          9. 12.1.3.4.9 I2C System Test Mode
        5. 12.1.3.5 I2C Programming Guide
          1. 12.1.3.5.1 I2C Low-Level Programming Models
            1. 12.1.3.5.1.1 I2C Programming Model
              1. 12.1.3.5.1.1.1 Main Program
                1. 12.1.3.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.5.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.5.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.5.1.1.1.4 Initiate a Transfer
                5. 12.1.3.5.1.1.1.5 Receive Data
                6. 12.1.3.5.1.1.1.6 Transmit Data
              2. 12.1.3.5.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.5.1.1.3 Programming Flow-Diagrams
        6. 12.1.3.6 I2C Registers
      4. 12.1.4 Improved Inter-Integrated Circuit (I3C) Interface
        1. 12.1.4.1 I3C Overview
          1. 12.1.4.1.1 I3C Features
          2. 12.1.4.1.2 I3C Not Supported Features
        2. 12.1.4.2 I3C Environment
          1. 12.1.4.2.1 I3C Typical Application
            1. 12.1.4.2.1.1 I3C Pins for Typical Connections
            2. 12.1.4.2.1.2 I3C Interface Typical Connections
            3. 12.1.4.2.1.3 1555
        3. 12.1.4.3 I3C Integration
          1. 12.1.4.3.1 I3C Integration in MCU Domain
          2. 12.1.4.3.2 I3C Integration in MAIN Domain
        4. 12.1.4.4 I3C Functional Description
          1. 12.1.4.4.1  I3C Block Diagram
          2. 12.1.4.4.2  I3C Clock Configuration
            1. 12.1.4.4.2.1 Setting Base Frequencies
            2. 12.1.4.4.2.2 Asymmetric Push-Pull SCL Timing
            3. 12.1.4.4.2.3 Open-Drain SCL Timing
            4. 12.1.4.4.2.4 Changing Programmed Frequencies
          3. 12.1.4.4.3  I3C Interrupt Requests
          4. 12.1.4.4.4  I3C Power Configuration
          5. 12.1.4.4.5  I3C Dynamic Address Management
          6. 12.1.4.4.6  I3C Retaining Registers Space
          7. 12.1.4.4.7  I3C Dynamic Address Assignment Procedure
          8. 12.1.4.4.8  I3C Sending CCC Messages
          9. 12.1.4.4.9  I3C In-Band Interrupt
            1. 12.1.4.4.9.1 Regular I3C Slave In-Band Interrupt
            2. 12.1.4.4.9.2 Current Master Takeover In-Band Interrupt
          10. 12.1.4.4.10 I3C Hot-Join Request
          11. 12.1.4.4.11 I3C Immediate Commands
          12. 12.1.4.4.12 I3C Host Commands
          13. 12.1.4.4.13 I3C Sending Private Data in SDR Messages
            1. 12.1.4.4.13.1 SDR Private Write Message
            2. 12.1.4.4.13.2 SDR Private Read Message
            3. 12.1.4.4.13.3 SDR Payload Length Adjustment
        5. 12.1.4.5 I3C Programming Guide
          1. 12.1.4.5.1 I3C Power-On Programming Model
          2. 12.1.4.5.2 I3C Static Devices Programming
          3. 12.1.4.5.3 I3C DAA Procedure Initiation
          4. 12.1.4.5.4 I3C SDR Write Message Programming Model
          5. 12.1.4.5.5 I3C SDR Read Message Programming Model
          6. 12.1.4.5.6 I3C DDR Write Message Programming Model
          7. 12.1.4.5.7 I3C DDR Read Message Programming Model
        6. 12.1.4.6 I3C Registers
      5. 12.1.5 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.5.1 MCSPI Overview
          1. 12.1.5.1.1 SPI Features
          2. 12.1.5.1.2 MCSPI Not Supported Features
        2. 12.1.5.2 MCSPI Environment
          1. 12.1.5.2.1 Basic MCSPI Pins for Master Mode
          2. 12.1.5.2.2 Basic MCSPI Pins for Slave Mode
          3. 12.1.5.2.3 MCSPI Internal Connectivity
          4. 12.1.5.2.4 MCSPI Protocol and Data Format
            1. 12.1.5.2.4.1 Transfer Format
          5. 12.1.5.2.5 MCSPI in Controller Mode
          6. 12.1.5.2.6 MCSPI in Peripheral Mode
        3. 12.1.5.3 MCSPI Integration
          1. 12.1.5.3.1 MCSPI Integration in MCU Domain
          2. 12.1.5.3.2 MCSPI Integration in MAIN Domain
        4. 12.1.5.4 MCSPI Functional Description
          1. 12.1.5.4.1 SPI Block Diagram
          2. 12.1.5.4.2 MCSPI Reset
          3. 12.1.5.4.3 MCSPI Controller Mode
            1. 12.1.5.4.3.1 Controller Mode Features
            2. 12.1.5.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.5.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.5.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.5.4.3.5 Single-Channel Controller Mode
              1. 12.1.5.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.5.4.3.5.2 Force SPIEN[i] Mode
              3. 12.1.5.4.3.5.3 Turbo Mode
            6. 12.1.5.4.3.6 Start-Bit Mode
            7. 12.1.5.4.3.7 Chip-Select Timing Control
            8. 12.1.5.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.5.4.3.8.1 Clock Ratio Granularity
          4. 12.1.5.4.4 MCSPI Peripheral Mode
            1. 12.1.5.4.4.1 Dedicated Resources
            2. 12.1.5.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.5.4.4.3 Peripheral Transmit-Only Mode
            4. 12.1.5.4.4.4 Peripheral Receive-Only Mode
          5. 12.1.5.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.5.4.6 MCSPI FIFO Buffer Management
            1. 12.1.5.4.6.1 Buffer Almost Full
            2. 12.1.5.4.6.2 Buffer Almost Empty
            3. 12.1.5.4.6.3 End of Transfer Management
            4. 12.1.5.4.6.4 Multiple MCSPI Word Access
            5. 12.1.5.4.6.5 First MCSPI Word Delay
          7. 12.1.5.4.7 MCSPI Interrupts
            1. 12.1.5.4.7.1 Interrupt Events in Controller Mode
              1. 12.1.5.4.7.1.1 TXx_EMPTY
              2. 12.1.5.4.7.1.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.1.3 RXx_ FULL
              4. 12.1.5.4.7.1.4 End Of Word Count
            2. 12.1.5.4.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.5.4.7.2.1 TXx_EMPTY
              2. 12.1.5.4.7.2.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.2.3 RXx_FULL
              4. 12.1.5.4.7.2.4 RX0_OVERFLOW
              5. 12.1.5.4.7.2.5 End Of Word Count
            3. 12.1.5.4.7.3 Interrupt-Driven Operation
            4. 12.1.5.4.7.4 Polling
          8. 12.1.5.4.8 MCSPI DMA Requests
          9. 12.1.5.4.9 MCSPI Power Saving Management
            1. 12.1.5.4.9.1 Normal Mode
            2. 12.1.5.4.9.2 Idle Mode
              1. 12.1.5.4.9.2.1 Force-Idle Mode
        5. 12.1.5.5 MCSPI Programming Guide
          1. 12.1.5.5.1 MCSPI Global Initialization
            1. 12.1.5.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.5.5.1.2 MCSPI Global Initialization
              1. 12.1.5.5.1.2.1 Main Sequence – MCSPI Global Initialization
          2. 12.1.5.5.2 MCSPI Operational Mode Configuration
            1. 12.1.5.5.2.1 MCSPI Operational Modes
              1. 12.1.5.5.2.1.1 Common Transfer Sequence
              2. 12.1.5.5.2.1.2 End of Transfer Sequences
              3. 12.1.5.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.5.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.5.5.2.1.4.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.4.2 Based on DMA Write Requests
              5. 12.1.5.5.2.1.5 Controller Normal Receive-Only
                1. 12.1.5.5.2.1.5.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.5.2 Based on DMA Read Requests
              6. 12.1.5.5.2.1.6 Controller Turbo Receive-Only
                1. 12.1.5.5.2.1.6.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.6.2 Based on DMA Read Requests
              7. 12.1.5.5.2.1.7 Peripheral Receive-Only
              8. 12.1.5.5.2.1.8 Transfer Procedures With FIFO
                1. 12.1.5.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.5.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.5.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.5.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.5.5.2.1.8.5 Transmit-Only
                6. 12.1.5.5.2.1.8.6 Receive-Only With Word Count
                7. 12.1.5.5.2.1.8.7 Receive-Only Without Word Count
              9. 12.1.5.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.5.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.5.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.5.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.5.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
        6. 12.1.5.6 MCSPI Registers
      6. 12.1.6 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.6.1 UART Overview
          1. 12.1.6.1.1 UART Features
          2. 12.1.6.1.2 IrDA Features
          3. 12.1.6.1.3 CIR Features
          4. 12.1.6.1.4 UART Not Supported Features
        2. 12.1.6.2 UART Environment
          1. 12.1.6.2.1 UART Functional Interfaces
            1. 12.1.6.2.1.1 System Using UART Communication With Hardware Handshake
            2. 12.1.6.2.1.2 UART Interface Description
            3. 12.1.6.2.1.3 UART Protocol and Data Format
            4. 12.1.6.2.1.4 UART 9-bit Mode Data Format
          2. 12.1.6.2.2 RS-485 Functional Interfaces
            1. 12.1.6.2.2.1 System Using RS-485 Communication
            2. 12.1.6.2.2.2 RS-485 Interface Description
          3. 12.1.6.2.3 IrDA Functional Interfaces
            1. 12.1.6.2.3.1 System Using IrDA Communication Protocol
            2. 12.1.6.2.3.2 IrDA Interface Description
            3. 12.1.6.2.3.3 IrDA Protocol and Data Format
              1. 12.1.6.2.3.3.1 SIR Mode
                1. 12.1.6.2.3.3.1.1 Frame Format
                2. 12.1.6.2.3.3.1.2 Asynchronous Transparency
                3. 12.1.6.2.3.3.1.3 Abort Sequence
                4. 12.1.6.2.3.3.1.4 Pulse Shaping
                5. 12.1.6.2.3.3.1.5 Encoder
                6. 12.1.6.2.3.3.1.6 Decoder
                7. 12.1.6.2.3.3.1.7 IR Address Checking
              2. 12.1.6.2.3.3.2 SIR Free-Format Mode
              3. 12.1.6.2.3.3.3 MIR Mode
                1. 12.1.6.2.3.3.3.1 MIR Encoder/Decoder
                2. 12.1.6.2.3.3.3.2 SIP Generation
              4. 12.1.6.2.3.3.4 FIR Mode
          4. 12.1.6.2.4 CIR Functional Interfaces
            1. 12.1.6.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 12.1.6.2.4.2 CIR Interface Description
            3. 12.1.6.2.4.3 CIR Protocol and Data Format
              1. 12.1.6.2.4.3.1 Carrier Modulation
              2. 12.1.6.2.4.3.2 Pulse Duty Cycle
              3. 12.1.6.2.4.3.3 Consumer IR Encoding/Decoding
        3. 12.1.6.3 UART Integration
          1. 12.1.6.3.1 UART Integration in WKUP Domain
          2. 12.1.6.3.2 UART Integration in MCU Domain
          3. 12.1.6.3.3 UART Integration in MAIN Domain
        4. 12.1.6.4 UART Functional Description
          1. 12.1.6.4.1 UART Block Diagram
          2. 12.1.6.4.2 UART Clock Configuration
          3. 12.1.6.4.3 UART Software Reset
            1. 12.1.6.4.3.1 Independent TX/RX
          4. 12.1.6.4.4 UART Power Management
            1. 12.1.6.4.4.1 UART Mode Power Management
              1. 12.1.6.4.4.1.1 Module Power Saving
              2. 12.1.6.4.4.1.2 System Power Saving
            2. 12.1.6.4.4.2 IrDA Mode Power Management
              1. 12.1.6.4.4.2.1 Module Power Saving
              2. 12.1.6.4.4.2.2 System Power Saving
            3. 12.1.6.4.4.3 CIR Mode Power Management
              1. 12.1.6.4.4.3.1 Module Power Saving
              2. 12.1.6.4.4.3.2 System Power Saving
            4. 12.1.6.4.4.4 Local Power Management
          5. 12.1.6.4.5 UART Interrupt Requests
            1. 12.1.6.4.5.1 UART Mode Interrupt Management
              1. 12.1.6.4.5.1.1 UART Interrupts
              2. 12.1.6.4.5.1.2 Wake-Up Interrupt
            2. 12.1.6.4.5.2 IrDA Mode Interrupt Management
              1. 12.1.6.4.5.2.1 IrDA Interrupts
              2. 12.1.6.4.5.2.2 Wake-Up Interrupts
            3. 12.1.6.4.5.3 CIR Mode Interrupt Management
              1. 12.1.6.4.5.3.1 CIR Interrupts
              2. 12.1.6.4.5.3.2 Wake-Up Interrupts
          6. 12.1.6.4.6 UART FIFO Management
            1. 12.1.6.4.6.1 FIFO Trigger
              1. 12.1.6.4.6.1.1 Transmit FIFO Trigger
              2. 12.1.6.4.6.1.2 Receive FIFO Trigger
            2. 12.1.6.4.6.2 FIFO Interrupt Mode
            3. 12.1.6.4.6.3 FIFO Polled Mode Operation
            4. 12.1.6.4.6.4 FIFO DMA Mode Operation
              1. 12.1.6.4.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.6.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.6.4.6.4.3 DMA Transmission
              4. 12.1.6.4.6.4.4 DMA Reception
          7. 12.1.6.4.7 UART Mode Selection
            1. 12.1.6.4.7.1 Register Access Modes
              1. 12.1.6.4.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.6.4.7.1.2 Register Access Submode
              3. 12.1.6.4.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.6.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.6.4.7.2.1 Registers Available for the UART Function
              2. 12.1.6.4.7.2.2 Registers Available for the IrDA Function
              3. 12.1.6.4.7.2.3 Registers Available for the CIR Function
          8. 12.1.6.4.8 UART Protocol Formatting
            1. 12.1.6.4.8.1 UART Mode
              1. 12.1.6.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.6.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.1.3 UART Data Formatting
                1. 12.1.6.4.8.1.3.1 Frame Formatting
                2. 12.1.6.4.8.1.3.2 Hardware Flow Control
                3. 12.1.6.4.8.1.3.3 Software Flow Control
                  1. 1.6.4.8.1.3.3.1 Receive (RX)
                  2. 1.6.4.8.1.3.3.2 Transmit (TX)
                4. 12.1.6.4.8.1.3.4 Autobauding Modes
                5. 12.1.6.4.8.1.3.5 Error Detection
                6. 12.1.6.4.8.1.3.6 Overrun During Receive
                7. 12.1.6.4.8.1.3.7 Time-Out and Break Conditions
                  1. 1.6.4.8.1.3.7.1 Time-Out Counter
                  2. 1.6.4.8.1.3.7.2 Break Condition
            2. 12.1.6.4.8.2 RS-485 Mode
              1. 12.1.6.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.6.4.8.3 IrDA Mode
              1. 12.1.6.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.6.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.3.3 IrDA Data Formatting
                1. 12.1.6.4.8.3.3.1  IR RX Polarity Control
                2. 12.1.6.4.8.3.3.2  IrDA Reception Control
                3. 12.1.6.4.8.3.3.3  IR Address Checking
                4. 12.1.6.4.8.3.3.4  Frame Closing
                5. 12.1.6.4.8.3.3.5  Store and Controlled Transmission
                6. 12.1.6.4.8.3.3.6  Error Detection
                7. 12.1.6.4.8.3.3.7  Underrun During Transmission
                8. 12.1.6.4.8.3.3.8  Overrun During Receive
                9. 12.1.6.4.8.3.3.9  Status FIFO
                10. 12.1.6.4.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.6.4.8.3.3.11 Time-guard
              4. 12.1.6.4.8.3.4 SIR Mode Data Formatting
                1. 12.1.6.4.8.3.4.1 Abort Sequence
                2. 12.1.6.4.8.3.4.2 Pulse Shaping
                3. 12.1.6.4.8.3.4.3 SIR Free Format Programming
              5. 12.1.6.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.6.4.8.4 CIR Mode
              1. 12.1.6.4.8.4.1 CIR Mode Clock Generation
              2. 12.1.6.4.8.4.2 CIR Data Formatting
                1. 12.1.6.4.8.4.2.1 IR RX Polarity Control
                2. 12.1.6.4.8.4.2.2 CIR Transmission
                3. 12.1.6.4.8.4.2.3 CIR Reception
        5. 12.1.6.5 UART Programming Guide
          1. 12.1.6.5.1 UART Global Initialization
            1. 12.1.6.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.6.5.1.2 UART Module Global Initialization
          2. 12.1.6.5.2 UART Mode selection
          3. 12.1.6.5.3 UART Submode selection
          4. 12.1.6.5.4 UART Load FIFO trigger and DMA mode settings
            1. 12.1.6.5.4.1 DMA mode Settings
            2. 12.1.6.5.4.2 FIFO Trigger Settings
          5. 12.1.6.5.5 UART Protocol, Baud rate and interrupt settings
            1. 12.1.6.5.5.1 Baud rate settings
            2. 12.1.6.5.5.2 Interrupt settings
            3. 12.1.6.5.5.3 Protocol settings
            4. 12.1.6.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.6.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 12.1.6.5.6 UART Hardware and Software Flow Control Configuration
            1. 12.1.6.5.6.1 Hardware Flow Control Configuration
            2. 12.1.6.5.6.2 Software Flow Control Configuration
          7. 12.1.6.5.7 IrDA Programming Model
            1. 12.1.6.5.7.1 SIR mode
              1. 12.1.6.5.7.1.1 Receive
              2. 12.1.6.5.7.1.2 Transmit
            2. 12.1.6.5.7.2 MIR mode
              1. 12.1.6.5.7.2.1 Receive
              2. 12.1.6.5.7.2.2 Transmit
            3. 12.1.6.5.7.3 FIR mode
              1. 12.1.6.5.7.3.1 Receive
              2. 12.1.6.5.7.3.2 Transmit
        6. 12.1.6.6 UART Registers
    2. 12.2 High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet MAC (MCU_CPSW0)
        1. 12.2.1.1 MCU_CPSW0 Overview
          1. 12.2.1.1.1 MCU_CPSW0 Features
          2. 12.2.1.1.2 MCU_CPSW0 Not Supported Features
          3. 12.2.1.1.3 Terminology
        2. 12.2.1.2 MCU_CPSW0 Environment
          1. 12.2.1.2.1 MCU_CPSW0 RMII Interface
          2. 12.2.1.2.2 MCU_CPSW0 RGMII Interface
        3. 12.2.1.3 MCU_CPSW0 Integration
        4. 12.2.1.4 MCU_CPSW0 Functional Description
          1. 12.2.1.4.1 Functional Block Diagram
          2. 12.2.1.4.2 CPSW Ports
            1. 12.2.1.4.2.1 Interface Mode Selection
          3. 12.2.1.4.3 Clocking
            1. 12.2.1.4.3.1 Subsystem Clocking
            2. 12.2.1.4.3.2 Interface Clocking
              1. 12.2.1.4.3.2.1 RGMII Interface Clocking
              2. 12.2.1.4.3.2.2 RMII Interface Clocking
              3. 12.2.1.4.3.2.3 MDIO Clocking
          4. 12.2.1.4.4 Software IDLE
          5. 12.2.1.4.5 Interrupt Functionality
            1. 12.2.1.4.5.1 EVNT_PEND Interrupt
            2. 12.2.1.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.1.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.1.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.1.4.5.5 MDIO Interrupts
          6. 12.2.1.4.6 CPSW_2G
            1. 12.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.1.4.6.1.1  Error Handling
              2. 12.2.1.4.6.1.2  Bypass Operations
              3. 12.2.1.4.6.1.3  OUI Deny or Accept
              4. 12.2.1.4.6.1.4  Statistics Counting
              5. 12.2.1.4.6.1.5  Automotive Security Features
              6. 12.2.1.4.6.1.6  CPSW Switching Solutions
                1. 12.2.1.4.6.1.6.1 Basics of 2-port Switch Type
              7. 12.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.1.4.6.1.7.1 InterVLAN Routing
                2. 12.2.1.4.6.1.7.2 OAM Operations
              8. 12.2.1.4.6.1.8  Supervisory packets
              9. 12.2.1.4.6.1.9  Address Table Entry
                1. 12.2.1.4.6.1.9.1 Free Table Entry
                2. 12.2.1.4.6.1.9.2 Multicast Address Table Entry
                3. 12.2.1.4.6.1.9.3 VLAN/Multicast Address Table Entry
                4. 12.2.1.4.6.1.9.4 Unicast Address Table Entry
                5. 12.2.1.4.6.1.9.5 OUI Unicast Address Table Entry
                6. 12.2.1.4.6.1.9.6 VLAN/Unicast Address Table Entry
                7. 12.2.1.4.6.1.9.7 VLAN Table Entry
              10. 12.2.1.4.6.1.10 ALE Policing and Classification
                1. 12.2.1.4.6.1.10.1 ALE Classification
                  1. 2.1.4.6.1.10.1.1 Classifier to CPPI Transmit Flow ID Mapping
              11. 12.2.1.4.6.1.11 DSCP
              12. 12.2.1.4.6.1.12 Packet Forwarding Processes
                1. 12.2.1.4.6.1.12.1 Ingress Filtering Process
                2. 12.2.1.4.6.1.12.2 VLAN_Aware Lookup Process
                3. 12.2.1.4.6.1.12.3 Egress Process
                4. 12.2.1.4.6.1.12.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.12.4.1 Learning Process
                  2. 2.1.4.6.1.12.4.2 Updating Process
                  3. 2.1.4.6.1.12.4.3 Touching Process
              13. 12.2.1.4.6.1.13 VLAN Aware Mode
              14. 12.2.1.4.6.1.14 VLAN Unaware Mode
            2. 12.2.1.4.6.2  Packet Priority Handling
              1. 12.2.1.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.1.4.6.3  CPPI Port Ingress
            4. 12.2.1.4.6.4  Packet CRC Handling
              1. 12.2.1.4.6.4.1 Transmit VLAN Processing
                1. 12.2.1.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.1.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.1.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.1.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.1.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.1.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.1.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.1.4.6.5  FIFO Memory Control
            6. 12.2.1.4.6.6  FIFO Transmit Queue Control
              1. 12.2.1.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.1.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.1.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.1.4.6.7.1 IET Configuration
            8. 12.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
              7. 12.2.1.4.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
            9. 12.2.1.4.6.9  Audio Video Bridging
              1. 12.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.1.4.6.10 Ethernet MAC Sliver
              1. 12.2.1.4.6.10.1 1945
                1. 12.2.1.4.6.10.1.1 1946
                  1. 2.1.4.6.10.1.1.1 CRC Insertion
                  2. 2.1.4.6.10.1.1.2 MTXER
                  3. 2.1.4.6.10.1.1.3 Adaptive Performance Optimization (APO)
                  4. 2.1.4.6.10.1.1.4 Inter-Packet-Gap Enforcement
                  5. 2.1.4.6.10.1.1.5 Back Off
                  6. 2.1.4.6.10.1.1.6 Programmable Transmit Inter-Packet Gap
                  7. 2.1.4.6.10.1.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 12.2.1.4.6.10.2 RMII Interface
                1. 12.2.1.4.6.10.2.1 Features
                2. 12.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 12.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 12.2.1.4.6.10.3 RGMII Interface
                1. 12.2.1.4.6.10.3.1 Features
                2. 12.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 12.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 12.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 12.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 12.2.1.4.6.10.4 Frame Classification
              5. 12.2.1.4.6.10.5 Receive FIFO Architecture
            11. 12.2.1.4.6.11 Embedded Memories
            12. 12.2.1.4.6.12 Memory Error Detection and Correction
              1. 12.2.1.4.6.12.1 Packet Header ECC
              2. 12.2.1.4.6.12.2 Packet Protect CRC
              3. 12.2.1.4.6.12.3 Aggregator RAM Control
            13. 12.2.1.4.6.13 Ethernet Port Flow Control
              1. 12.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.1.4.6.13.2 Flow Control Trigger
              3. 12.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 12.2.1.4.6.15 Ethernet Switch Latency
            16. 12.2.1.4.6.16 MAC Emulation Control
            17. 12.2.1.4.6.17 MAC Command IDLE
            18. 12.2.1.4.6.18 CPSW Network Statistics
              1. 12.2.1.4.6.18.1  Rx-only Statistics Descriptions
                1. 12.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h - Port 0 or Offset = 3A200h - Port 1)
                2. 12.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h - Port 0 or Offset = 3A204h - Port 1)
                3. 12.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h - Port 0 or Offset = 3A208h - Port 1)
                4. 12.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A20Ch - Port 1)
                5. 12.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h - Port 0 or Offset = 3A210h - Port 1)
                6. 12.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A214h - Port 1)
                7. 12.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h - Port 0 or Offset = 3A218h - Port 1)
                8. 12.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A21Ch - Port 1)
                9. 12.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h- Port 0 or Offset = 3A220h - Port 1)
                10. 12.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h - Port 0 or Offset = 3A224h - Port 1)
                11. 12.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A25Ch - Port 1)
                12. 12.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h - Port 0 or Offset = 3A228h - Port 1)
                13. 12.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch - Port 0 or Offset = 3A22Ch - Port 1)
                14. 12.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h - Port 0 or Offset = 3A230h - Port 1)
                15. 12.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h - Port 0 or Offset = 3A284h - Port 1)
                16. 12.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h - Port 0 or Offset = 3A288h - Port 1)
                17. 12.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch - Port 0 or Offset = 3A28Ch - Port 1)
                18. 12.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h - Port 0 or Offset = 3A290h - Port 1)
                19. 12.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h - Port 0 or Offset = 3A294h - Port 1)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h - Port 0 or Offset = 3A298h - Port 1)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch - Port 0 or Offset = 3A29Ch - Port 1)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h - Port 0 or Offset = 3A2A0h - Port 1)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h - Port 0 or Offset = 3A2A4h - Port 1)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h - Port 0 or Offset = 3A2A8h - Port 1)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh - Port 0 or Offset = 3A2ACh - Port 1)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h - Port 0 or Offset = 3A2B0h - Port 1)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h - Port 0 or Offset = 3A2B4h - Port 1)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h - Port 0 or Offset = 3A2B8h - Port 1)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh - Port 0 or Offset = 3A2BCh - Port 1)
                  11. 2.1.4.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h - Port 0 or Offset = 3A2C0h - Port 1)
              2. 12.2.1.4.6.18.2  ALE Policer Match Red (Offset = 3A0C4h - Port 0 or Offset = 3A2C4h - Port 1)
              3. 12.2.1.4.6.18.3  ALE Policer Match Yellow (Offset = 3A0C8h - Port 0 or Offset = 3A2C8h - Port 1)
              4. 12.2.1.4.6.18.4  IET Receive Assembly Error (Offset = 3A140h - Port 0 or Offset = 3A340h - Port 1)
              5. 12.2.1.4.6.18.5  IET Receive Assembly OK (Offset = 3A144h - Port 0 or Offset = 3A344h - Port 1)
              6. 12.2.1.4.6.18.6  IET Receive SMD Error (Offset = 3A148h - Port 0 or Offset = 3A348h - Port 1)
              7. 12.2.1.4.6.18.7  IET Receive Merge Fragment Count (Offset = 3A14Ch - Port 0 or Offset = 3A34Ch - Port 1)
              8. 12.2.1.4.6.18.8  Tx-only Statistics Descriptions
                1. 12.2.1.4.6.18.8.1  Good Tx Frames (Offset = 3A034h - Port 0 or Offset = 3A234h - Port 1)
                2. 12.2.1.4.6.18.8.2  Broadcast Tx Frames (Offset = 3A038h - Port 0 or Offset = 3A238h - Port 1)
                3. 12.2.1.4.6.18.8.3  Multicast Tx Frames (Offset = 3A03Ch - Port 0 or Offset = 3A23Ch - Port 1)
                4. 12.2.1.4.6.18.8.4  Pause Tx Frames (Offset = 3A240h - Port 1)
                5. 12.2.1.4.6.18.8.5  Deferred Tx Frames (Offset = 3A244h - Port 1)
                6. 12.2.1.4.6.18.8.6  Collisions (Offset = 3A248h - Port 1)
                7. 12.2.1.4.6.18.8.7  Single Collision Tx Frames (Offset = 3A24Ch - Port 1)
                8. 12.2.1.4.6.18.8.8  Multiple Collision Tx Frames (Offset = 3A250h - Port 1)
                9. 12.2.1.4.6.18.8.9  Excessive Collisions (Offset = 3A254h - Port 1)
                10. 12.2.1.4.6.18.8.10 Late Collisions (Offset = 3A258h - Port 1)
                11. 12.2.1.4.6.18.8.11 Carrier Sense Errors (Offset = 3A260h - Port 1)
                12. 12.2.1.4.6.18.8.12 Tx Octets (Offset = 3A064h - Port 0 or Offset = 3A264h - Port 1 )
                13. 12.2.1.4.6.18.8.13 Transmit Priority 0-7 (Offset = 3A380h to 3A3A8h - Port 1)
                14. 12.2.1.4.6.18.8.14 Transmit Priority 0-7 Drop (Offset = 3A3C0h to 3A3E8 - Port 1)
                15. 12.2.1.4.6.18.8.15 Tx Memory Protect Errors (Offset = 3A17Ch - Port 0 or Offset = 3A37Ch - Port 1)
                16. 12.2.1.4.6.18.8.16 IET Transmit Merge Hold Count (Offset = 3A350h - Port 1)
                17. 12.2.1.4.6.18.8.17 IET Transmit Merge Fragment Count (Offset = 3A154h - Port 0 or Offset = 3A354h - Port 1)
              9. 12.2.1.4.6.18.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.1.4.6.18.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h - Port 0 or Offset = 3A268h - Port 1)
                2. 12.2.1.4.6.18.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch - Port 0 or Offset = 3A26Ch - Port 1)
                3. 12.2.1.4.6.18.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h - Port 0 or Offset = 3A270h - Port 1)
                4. 12.2.1.4.6.18.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h - Port 0 or Offset = 3A274h - Port 1)
                5. 12.2.1.4.6.18.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h - Port 0 or Offset = 3A278h - Port 1)
                6. 12.2.1.4.6.18.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch - Port 0 or Offset = 3A27Ch - Port 1)
                7. 12.2.1.4.6.18.9.7 Net Octets (Offset = 3A080h - Port 0 or Offset = 3A280h - Port 1)
              10. 12.2.1.4.6.18.10 2045
          7. 12.2.1.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.1.4.7.1  MCU_CPSW0 CPTS Integration
            2. 12.2.1.4.7.2  CPTS Architecture
            3. 12.2.1.4.7.3  CPTS Initialization
            4. 12.2.1.4.7.4  32-bit Time Stamp Value
            5. 12.2.1.4.7.5  64-bit Time Stamp Value
            6. 12.2.1.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.1.4.7.7  64-bit Timestamp PPM
            8. 12.2.1.4.7.8  Event FIFO
            9. 12.2.1.4.7.9  Timestamp Compare Output
              1. 12.2.1.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.1.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.1.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.1.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.1.4.7.10 Timestamp Sync Output
            11. 12.2.1.4.7.11 Timestamp GENFn Output
              1. 12.2.1.4.7.11.1 GENFn Nudge
              2. 12.2.1.4.7.11.2 GENFn PPM
            12. 12.2.1.4.7.12 Timestamp ESTFn
            13. 12.2.1.4.7.13 Time Sync Events
              1. 12.2.1.4.7.13.1 Time Stamp Push Event
              2. 12.2.1.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.1.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.1.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.1.4.7.13.5 Ethernet Port Events
                1. 12.2.1.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.1.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.1.4.7.13.5.3 2073
            14. 12.2.1.4.7.14 Timestamp Compare Event
              1. 12.2.1.4.7.14.1 32-Bit Mode
              2. 12.2.1.4.7.14.2 64-Bit Mode
            15. 12.2.1.4.7.15 Host Transmit Event
            16. 12.2.1.4.7.16 CPTS Interrupt Handling
          8. 12.2.1.4.8 CPPI Streaming Packet Interface
            1. 12.2.1.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_2G Egress)
            2. 12.2.1.4.8.2 Port 0 CPPI Receive Packet Streaming Interface (CPSW_2G Ingress)
            3. 12.2.1.4.8.3 CPPI Checksum Offload
              1. 12.2.1.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.1.4.8.3.1.1 IPV4 UDP
                2. 12.2.1.4.8.3.1.2 IPV4 TCP
                3. 12.2.1.4.8.3.1.3 IPV6 UDP
                4. 12.2.1.4.8.3.1.4 IPV6 TCP
            4. 12.2.1.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.1.4.8.5 Egress Packet Operations
          9. 12.2.1.4.9 MII Management Interface (MDIO)
            1. 12.2.1.4.9.1 MDIO Frame Formats
            2. 12.2.1.4.9.2 MDIO Functional Description
        5. 12.2.1.5 MCU_CPSW0 Programming Guide
          1. 12.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.5.2 CPSW Reset
          3. 12.2.1.5.3 MDIO Software Interface
            1. 12.2.1.5.3.1 Initializing the MDIO Module
            2. 12.2.1.5.3.2 Writing Data To a PHY Register
            3. 12.2.1.5.3.3 Reading Data From a PHY Register
        6. 12.2.1.6 MCU_CPSW0 Registers
          1. 12.2.1.6.1  MCU_CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.1.6.2  MCU_CPSW0_SGMII Registers
          3. 12.2.1.6.3  MCU_CPSW0_MDIO Registers
          4. 12.2.1.6.4  MCU_CPSW0_CPTS Registers
          5. 12.2.1.6.5  MCU_CPSW0_CONTROL Registers
          6. 12.2.1.6.6  MCU_CPSW0_CPINT Registers
          7. 12.2.1.6.7  MCU_CPSW0_RAM Registers
          8. 12.2.1.6.8  MCU_CPSW0_STAT0 Registers
          9. 12.2.1.6.9  MCU_CPSW0_STAT1 Registers
          10. 12.2.1.6.10 MCU_CPSW0_ALE Registers
          11. 12.2.1.6.11 MCU_CPSW0_ECC Registers
      2. 12.2.2 Gigabit Ethernet Switch (CPSW0)
        1. 12.2.2.1 CPSW0 Overview
          1. 12.2.2.1.1 CPSW0 Features
          2. 12.2.2.1.2 CPSW0 Not Supported Features
          3. 12.2.2.1.3 Terminology
        2. 12.2.2.2 CPSW0 Environment
          1. 12.2.2.2.1 CPSW0 RMII Interface
          2. 12.2.2.2.2 CPSW0 RGMII Interface
        3. 12.2.2.3 CPSW0 Integration
        4. 12.2.2.4 CPSW0 Functional Description
          1. 12.2.2.4.1 Functional Block Diagram
          2. 12.2.2.4.2 CPSW Ports
            1. 12.2.2.4.2.1 Interface Mode Selection
          3. 12.2.2.4.3 Clocking
            1. 12.2.2.4.3.1 Subsystem Clocking
            2. 12.2.2.4.3.2 Interface Clocking
              1. 12.2.2.4.3.2.1 RGMII Interface Clocking
              2. 12.2.2.4.3.2.2 RMII Interface Clocking
              3. 12.2.2.4.3.2.3 MDIO Clocking
          4. 12.2.2.4.4 Software IDLE
          5. 12.2.2.4.5 Interrupt Functionality
            1. 12.2.2.4.5.1 EVNT_PEND Interrupt
            2. 12.2.2.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.2.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.2.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.2.4.5.5 MDIO Interrupts
          6. 12.2.2.4.6 CPSW_5X
            1. 12.2.2.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.2.4.6.1.1  Error Handling
              2. 12.2.2.4.6.1.2  Bypass Operations
              3. 12.2.2.4.6.1.3  OUI Deny or Accept
              4. 12.2.2.4.6.1.4  Statistics Counting
              5. 12.2.2.4.6.1.5  Automotive Security Features
              6. 12.2.2.4.6.1.6  CPSW Switching Solutions
                1. 12.2.2.4.6.1.6.1 Basics of 5-port Switch Type
              7. 12.2.2.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.2.4.6.1.7.1 InterVLAN Routing
                2. 12.2.2.4.6.1.7.2 OAM Operations
              8. 12.2.2.4.6.1.8  Supervisory packets
              9. 12.2.2.4.6.1.9  Address Table Entry
                1. 12.2.2.4.6.1.9.1  Free Table Entry
                2. 12.2.2.4.6.1.9.2  Multicast Address Table Entry (Bit 40 == 0)
                3. 12.2.2.4.6.1.9.3  Multicast Address Table Entry (Bit 40 == 1)
                4. 12.2.2.4.6.1.9.4  VLAN Unicast Address Table Entry (Bit 40 == 0)
                5. 12.2.2.4.6.1.9.5  OUI Unicast Address Table Entry
                6. 12.2.2.4.6.1.9.6  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                7. 12.2.2.4.6.1.9.7  VLAN/ Multicast Address Table Entry (Bit 40 == 1)
                8. 12.2.2.4.6.1.9.8  Inner VLAN Table Entry
                9. 12.2.2.4.6.1.9.9  Outer VLAN Table Entry
                10. 12.2.2.4.6.1.9.10 EtherType Table Entry
                11. 12.2.2.4.6.1.9.11 IPv4 Table Entry
                12. 12.2.2.4.6.1.9.12 IPv6 Table Entry High
                13. 12.2.2.4.6.1.9.13 IPv6 Table Entry Low
              10. 12.2.2.4.6.1.10 Multicast Address
                1. 12.2.2.4.6.1.10.1 Multicast Ranges
              11. 12.2.2.4.6.1.11 Supervisory Packets
              12. 12.2.2.4.6.1.12 Aging and Auto Aging
              13. 12.2.2.4.6.1.13 ALE Policing and Classification
                1. 12.2.2.4.6.1.13.1 ALE Policing
                2. 12.2.2.4.6.1.13.2 Classifier to Host Thread Mapping
                3. 12.2.2.4.6.1.13.3 ALE Classification
                  1. 2.2.4.6.1.13.3.1 Classifier to CPPI Transmit Flow ID Mapping
              14. 12.2.2.4.6.1.14 Mirroring
              15. 12.2.2.4.6.1.15 Trunking
              16. 12.2.2.4.6.1.16 DSCP
              17. 12.2.2.4.6.1.17 Packet Forwarding Processes
                1. 12.2.2.4.6.1.17.1 Ingress Filtering Process
                2. 12.2.2.4.6.1.17.2 VLAN_Aware Lookup Process
                3. 12.2.2.4.6.1.17.3 Egress Process
                4. 12.2.2.4.6.1.17.4 Learning/Updating/Touching Processes
                  1. 2.2.4.6.1.17.4.1 Learning Process
                  2. 2.2.4.6.1.17.4.2 Updating Process
                  3. 2.2.4.6.1.17.4.3 Touching Process
              18. 12.2.2.4.6.1.18 VLAN Aware Mode
              19. 12.2.2.4.6.1.19 VLAN Unaware Mode
            2. 12.2.2.4.6.2  Packet Priority Handling
              1. 12.2.2.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.2.4.6.3  CPPI Port Ingress
            4. 12.2.2.4.6.4  Packet CRC Handling
              1. 12.2.2.4.6.4.1 Transmit VLAN Processing
                1. 12.2.2.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.2.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.2.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.2.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.2.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.2.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.2.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.2.4.6.5  FIFO Memory Control
            6. 12.2.2.4.6.6  FIFO Transmit Queue Control
              1. 12.2.2.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.2.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.2.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.2.4.6.7.1 IET Configuration
            8. 12.2.2.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.2.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.2.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.2.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.2.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.2.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.2.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
            9. 12.2.2.4.6.9  Audio Video Bridging
              1. 12.2.2.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.2.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.2.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.2.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.2.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.2.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.2.4.6.10 Ethernet MAC Sliver
              1. 12.2.2.4.6.10.1  CRC Insertion
              2. 12.2.2.4.6.10.2  MTXER
              3. 12.2.2.4.6.10.3  Adaptive Performance Optimization (APO)
              4. 12.2.2.4.6.10.4  Inter-Packet-Gap Enforcement
              5. 12.2.2.4.6.10.5  Back Off
              6. 12.2.2.4.6.10.6  Programmable Transmit Inter-Packet Gap
              7. 12.2.2.4.6.10.7  Speed, Duplex and Pause Frame Support Negotiation
              8. 12.2.2.4.6.10.8  RMII Interface
                1. 12.2.2.4.6.10.8.1 Features
                2. 12.2.2.4.6.10.8.2 RMII Receive (RX)
                3. 12.2.2.4.6.10.8.3 RMII Transmit (TX)
              9. 12.2.2.4.6.10.9  RGMII Interface
                1. 12.2.2.4.6.10.9.1 Features
                2. 12.2.2.4.6.10.9.2 RGMII Receive (RX)
                3. 12.2.2.4.6.10.9.3 In-Band Mode of Operation
                4. 12.2.2.4.6.10.9.4 Forced Mode of Operation
                5. 12.2.2.4.6.10.9.5 RGMII Transmit (TX)
              10. 12.2.2.4.6.10.10 Frame Classification
              11. 12.2.2.4.6.10.11 Receive FIFO Architecture
            11. 12.2.2.4.6.11 Embedded Memories
            12. 12.2.2.4.6.12 Memory Error Detection and Correction
              1. 12.2.2.4.6.12.1 Packet Header ECC
              2. 12.2.2.4.6.12.2 Packet Protect CRC
              3. 12.2.2.4.6.12.3 Aggregator RAM Control
            13. 12.2.2.4.6.13 Ethernet Port Flow Control
              1. 12.2.2.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.2.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.2.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.2.4.6.13.2 Qbb (10/100/1G/10G) Receive Priority Based Flow Control (PFC)
              3. 12.2.2.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.2.4.6.14 PFC Trigger Rules
              1. 12.2.2.4.6.14.1 Destination Based Rule
              2. 12.2.2.4.6.14.2 Sum of Outflows Rule
              3. 12.2.2.4.6.14.3 Sum of Blocks Per Port Rule
              4. 12.2.2.4.6.14.4 Sum of Blocks Total Rule
              5. 12.2.2.4.6.14.5 Top of Receive FIFO Rule
            15. 12.2.2.4.6.15 Energy Efficient Ethernet Support (802.3az)
            16. 12.2.2.4.6.16 Ethernet Switch Latency
            17. 12.2.2.4.6.17 MAC Emulation Control
            18. 12.2.2.4.6.18 MAC Command IDLE
            19. 12.2.2.4.6.19 CPSW Network Statistics
              1. 12.2.2.4.6.19.1  Rx-only Statistics Descriptions
                1. 12.2.2.4.6.19.1.1  Good Rx Frames (Offset = 3A000h)
                2. 12.2.2.4.6.19.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 12.2.2.4.6.19.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 12.2.2.4.6.19.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 12.2.2.4.6.19.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 12.2.2.4.6.19.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 12.2.2.4.6.19.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 12.2.2.4.6.19.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 12.2.2.4.6.19.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 12.2.2.4.6.19.1.10 Rx Fragments (Offset = 3A024h)
                11. 12.2.2.4.6.19.1.11 RX IPG Error
                12. 12.2.2.4.6.19.1.12 ALE Drop (Offset = 3A028h)
                13. 12.2.2.4.6.19.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 12.2.2.4.6.19.1.14 Rx Octets (Offset = 3A030h)
                15. 12.2.2.4.6.19.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 12.2.2.4.6.19.1.16 Portmask Drop (Offset = 3A088h)
                17. 12.2.2.4.6.19.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 12.2.2.4.6.19.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 12.2.2.4.6.19.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.2.4.6.19.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.2.4.6.19.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.2.4.6.19.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.2.4.6.19.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.2.4.6.19.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.2.4.6.19.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.2.4.6.19.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.2.4.6.19.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.2.4.6.19.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.2.4.6.19.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.2.4.6.19.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
              2. 12.2.2.4.6.19.2  ALE Policer Match Red (Offset = 3A0C4h)
              3. 12.2.2.4.6.19.3  ALE Policer Match Yellow (Offset = 3A0C8h)
              4. 12.2.2.4.6.19.4  IET Receive Assembly Error (Offset = 3A140h)
              5. 12.2.2.4.6.19.5  IET Receive Assembly OK (Offset = 3A144h)
              6. 12.2.2.4.6.19.6  IET Receive SMD Error (Offset = 3A148h)
              7. 12.2.2.4.6.19.7  IET Receive Merge Fragment Count (Offset = 3A14Ch)
              8. 12.2.2.4.6.19.8  Tx-only Statistics Descriptions
                1. 12.2.2.4.6.19.8.1  Good Tx Frames (Offset = 3A034h)
                2. 12.2.2.4.6.19.8.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 12.2.2.4.6.19.8.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 12.2.2.4.6.19.8.4  Pause Tx Frames (Offset = 3A040h)
                5. 12.2.2.4.6.19.8.5  Deferred Tx Frames (Offset = 3A044h)
                6. 12.2.2.4.6.19.8.6  Collisions (Offset = 3A048h)
                7. 12.2.2.4.6.19.8.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 12.2.2.4.6.19.8.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 12.2.2.4.6.19.8.9  Excessive Collisions (Offset = 3A054h)
                10. 12.2.2.4.6.19.8.10 Late Collisions (Offset = 3A058h)
                11. 12.2.2.4.6.19.8.11 Carrier Sense Errors (Offset = 3A060h)
                12. 12.2.2.4.6.19.8.12 Tx Octets (Offset = 3A064h)
                13. 12.2.2.4.6.19.8.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 12.2.2.4.6.19.8.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8h)
                15. 12.2.2.4.6.19.8.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 12.2.2.4.6.19.8.16 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
                17. 12.2.2.4.6.19.8.17 IET Transmit Merge Hold Count (Offset = 3A150h)
              9. 12.2.2.4.6.19.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.2.4.6.19.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 12.2.2.4.6.19.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 12.2.2.4.6.19.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 12.2.2.4.6.19.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 12.2.2.4.6.19.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 12.2.2.4.6.19.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 12.2.2.4.6.19.9.7 Net Octets (Offset = 3A080h)
              10. 12.2.2.4.6.19.10 2324
          7. 12.2.2.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.2.4.7.1  CPSW0 CPTS Integration
            2. 12.2.2.4.7.2  CPTS Architecture
            3. 12.2.2.4.7.3  CPTS Initialization
            4. 12.2.2.4.7.4  32-bit Time Stamp Value
            5. 12.2.2.4.7.5  64-bit Time Stamp Value
            6. 12.2.2.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.2.4.7.7  64-bit Timestamp PPM
            8. 12.2.2.4.7.8  Event FIFO
            9. 12.2.2.4.7.9  Timestamp Compare Output
              1. 12.2.2.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.2.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.2.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.2.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.2.4.7.10 Timestamp Sync Output
            11. 12.2.2.4.7.11 Timestamp GENFn Output
              1. 12.2.2.4.7.11.1 GENFn Nudge
              2. 12.2.2.4.7.11.2 GENFn PPM
            12. 12.2.2.4.7.12 Timestamp ESTFn
            13. 12.2.2.4.7.13 Time Sync Events
              1. 12.2.2.4.7.13.1 Time Stamp Push Event
              2. 12.2.2.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.2.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.2.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.2.4.7.13.5 Ethernet Port Events
                1. 12.2.2.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.2.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.2.4.7.13.5.3 2352
            14. 12.2.2.4.7.14 Timestamp Compare Event
              1. 12.2.2.4.7.14.1 32-Bit Mode
              2. 12.2.2.4.7.14.2 64-Bit Mode
            15. 12.2.2.4.7.15 Host Transmit Event
            16. 12.2.2.4.7.16 CPTS Interrupt Handling
          8. 12.2.2.4.8 CPPI Streaming Packet Interface
            1. 12.2.2.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_5X Egress)
            2. 12.2.2.4.8.2 CPPI Receive Packet Streaming Interface (CPSW Ingress)
            3. 12.2.2.4.8.3 CPPI Checksum Offload
              1. 12.2.2.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.2.4.8.3.1.1 IPV4 UDP
                2. 12.2.2.4.8.3.1.2 IPV4 TCP
                3. 12.2.2.4.8.3.1.3 IPV6 UDP
                4. 12.2.2.4.8.3.1.4 IPV6 TCP
            4. 12.2.2.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.2.4.8.5 Egress Packet Operations
          9. 12.2.2.4.9 MII Management Interface (MDIO)
            1. 12.2.2.4.9.1 MDIO Frame Formats
            2. 12.2.2.4.9.2 MDIO Functional Description
        5. 12.2.2.5 CPSW0 Programming Guide
          1. 12.2.2.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.2.5.2 Ethernet MAC Reset or XGMII/GMII Mode Change Configuration
          3. 12.2.2.5.3 MDIO Software Interface
            1. 12.2.2.5.3.1 Initializing the MDIO Module
            2. 12.2.2.5.3.2 Writing Data To a PHY Register
            3. 12.2.2.5.3.3 Reading Data From a PHY Register
        6. 12.2.2.6 CPSW0 Registers
          1. 12.2.2.6.1  CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.2.6.2  CPSW0_SGMII Registers
          3. 12.2.2.6.3  CPSW0_MDIO Registers
          4. 12.2.2.6.4  CPSW0_CPTS Registers
          5. 12.2.2.6.5  CPSW0_CONTROL Registers
          6. 12.2.2.6.6  CPSW0_CPINT Registers
          7. 12.2.2.6.7  CPSW0_RAM Registers
          8. 12.2.2.6.8  CPSW0_STAT Registers
          9. 12.2.2.6.9  CPSW0_ALE Registers
          10. 12.2.2.6.10 CPSW0_PCSR Registers
          11. 12.2.2.6.11 CPSW0_ECC Registers
      3. 12.2.3 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.3.1 PCIe Subsystem Overview
          1. 12.2.3.1.1 PCIe Subsystem Features
          2. 12.2.3.1.2 PCIe Subsystem Not Supported Features
        2. 12.2.3.2 PCIe Subsystem Environment
        3. 12.2.3.3 PCIe Subsystem Integration
        4. 12.2.3.4 PCIe Subsystem Functional Description
          1. 12.2.3.4.1  PCIe Subsystem Block Diagram
            1. 12.2.3.4.1.1 PCIe Core Module
            2. 12.2.3.4.1.2 PCIe PHY Interface
            3. 12.2.3.4.1.3 CBA Infrastructure
            4. 12.2.3.4.1.4 VBUSM to AXI Bridges
            5. 12.2.3.4.1.5 AXI to VBUSM Bridges
            6. 12.2.3.4.1.6 VBUSP to APB Bridge
            7. 12.2.3.4.1.7 Custom Logic
          2. 12.2.3.4.2  PCIe Subsystem Reset Schemes
            1. 12.2.3.4.2.1 PCIe Conventional Reset
            2. 12.2.3.4.2.2 PCIe Function Level Reset
            3. 12.2.3.4.2.3 PCIe Reset Isolation
              1. 12.2.3.4.2.3.1 Root Port Reset with Device Not Reset
              2. 12.2.3.4.2.3.2 Device Reset with Root Port Not Reset
              3. 12.2.3.4.2.3.3 End Point Device Reset with Root Port Not Reset
              4. 12.2.3.4.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.3.4.2.4 PCIe Reset Limitations
            5. 12.2.3.4.2.5 PCIe Reset Requirements
          3. 12.2.3.4.3  PCIe Subsystem Power Management
            1. 12.2.3.4.3.1 CBA Power Management
          4. 12.2.3.4.4  PCIe Subsystem Interrupts
            1. 12.2.3.4.4.1 Interrupts Aggregation
            2. 12.2.3.4.4.2 Interrupt Generation in EP Mode
              1. 12.2.3.4.4.2.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.3.4.4.2.2 MSI and MSI-X Interrupt Generation
            3. 12.2.3.4.4.3 Interrupt Reception in EP Mode
              1. 12.2.3.4.4.3.1 PCIe Core Downstream Interrupts
              2. 12.2.3.4.4.3.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.3.4.4.3.3 PCIe Core Power Management Event Interrupts
              4. 12.2.3.4.4.3.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.3.4.4.3.5 PTM Valid Interrupt
            4. 12.2.3.4.4.4 Interrupt Generation in RP Mode
            5. 12.2.3.4.4.5 Interrupt Reception in RP Mode
              1. 12.2.3.4.4.5.1 PCIe Legacy Interrupt Reception in RP Mode
              2. 12.2.3.4.4.5.2 MSI/MSI-X Interrupt Reception in RP Mode
              3. 12.2.3.4.4.5.3 Advanced Error Reporting Interrupt
            6. 12.2.3.4.4.6 Common Interrupt Reception in RP and EP Modes
              1. 12.2.3.4.4.6.1 PCIe Local Interrupt
              2. 12.2.3.4.4.6.2 PHY Interrupt
              3. 12.2.3.4.4.6.3 Link down Interrupt
              4. 12.2.3.4.4.6.4 Transaction Error Interrupts
              5. 12.2.3.4.4.6.5 Power Management Event Interrupt
              6. 12.2.3.4.4.6.6 Active Internal Diagnostics Interrupts
            7. 12.2.3.4.4.7 ECC Aggregator Interrupts
            8. 12.2.3.4.4.8 CPTS Interrupt
          5. 12.2.3.4.5  PCIe Subsystem DMA Support
            1. 12.2.3.4.5.1 PCIe DMA Support in RP Mode
            2. 12.2.3.4.5.2 PCIe DMA Support in EP Mode
          6. 12.2.3.4.6  PCIe Subsystem Transactions
            1. 12.2.3.4.6.1 PCIe Supported Transactions
            2. 12.2.3.4.6.2 PCIe Transaction Limitations
          7. 12.2.3.4.7  PCIe Subsystem Address Translation
            1. 12.2.3.4.7.1 PCIe Inbound Address Translation
              1. 12.2.3.4.7.1.1 Root Port Inbound PCIe to AXI Address Translation
              2. 12.2.3.4.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.3.4.7.2 PCIe Outbound Address Translation
              1. 12.2.3.4.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.3.4.8  PCIe Subsystem Virtualization Support
            1. 12.2.3.4.8.1 End Point SR-IOV Support
            2. 12.2.3.4.8.2 Root Port ATS Support
            3. 12.2.3.4.8.3 VirtID Mapping
          9. 12.2.3.4.9  PCIe Subsystem Quality-of-Service (QoS)
          10. 12.2.3.4.10 PCIe Subsystem Precision Time Measurement (PTM)
          11. 12.2.3.4.11 PCIe Subsystem Loopback
            1. 12.2.3.4.11.1 PCIe PIPE Loopback
              1. 12.2.3.4.11.1.1 PIPE Loopback Master Mode
              2. 12.2.3.4.11.1.2 PIPE Loopback Slave Mode
          12. 12.2.3.4.12 PCIe Subsystem Error Handling
            1. 12.2.3.4.12.1 PCIe AXI to/from VBUSM Bus Error Mapping
          13. 12.2.3.4.13 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.3.4.13.1 PCIe Parity
            2. 12.2.3.4.13.2 ECC Aggregators
            3. 12.2.3.4.13.3 RAM ECC Inversion
          14. 12.2.3.4.14 LTSSM State Encoding
        5. 12.2.3.5 PCIe Subsystem Registers
          1. 12.2.3.5.1  PCIE_CORE_EP_PF Registers
          2. 12.2.3.5.2  PCIE_CORE_EP_VF Registers
          3. 12.2.3.5.3  PCIE_CORE_RP Registers
          4. 12.2.3.5.4  PCIE_CORE_LM Registers
          5. 12.2.3.5.5  PCIE_CORE_AXI Registers
          6. 12.2.3.5.6  PCIE_INTD Registers
          7. 12.2.3.5.7  PCIE_VMAP Registers
          8. 12.2.3.5.8  PCIE_CPTS Registers
          9. 12.2.3.5.9  PCIE_USER_CFG Registers
          10. 12.2.3.5.10 PCIE_ECC_AGGR0 Registers
          11. 12.2.3.5.11 PCIE_ECC_AGGR1 Registers
          12. 12.2.3.5.12 PCIE_DAT0 Registers
          13. 12.2.3.5.13 PCIE_DAT1 Registers
      4. 12.2.4 Universal Serial Bus (USB) Subsystem
        1. 12.2.4.1 USB Overview
          1. 12.2.4.1.1 USB Features
          2. 12.2.4.1.2 USB Not Supported Features
          3. 12.2.4.1.3 USB Terminology
        2. 12.2.4.2 USB Environment
        3. 12.2.4.3 USB Integration
        4. 12.2.4.4 USB Functional Description
          1. 12.2.4.4.1 USB Type-C Connector Support
          2. 12.2.4.4.2 USB Controller Reset
          3. 12.2.4.4.3 Overcurrent Detection
          4. 12.2.4.4.4 Top-Level Initialization Sequence
        5. 12.2.4.5 USB Registers
          1. 12.2.4.5.1 USB3P0SS_MMR_MMRVBP_USBSS_CMN Registers
          2. 12.2.4.5.2 USB_ECC_AGGR_CFG Registers
          3. 12.2.4.5.3 USB_RAMS_INJ_CFG Registers
      5. 12.2.5 Serializer/Deserializer (SerDes)
        1. 12.2.5.1 SerDes Overview
          1. 12.2.5.1.1 SerDes Features
          2. 12.2.5.1.2 Industry Standards Compatibility
        2. 12.2.5.2 SerDes Environment
          1. 12.2.5.2.1 SerDes I/Os
        3. 12.2.5.3 SerDes Integration
          1. 12.2.5.3.1 WIZ Settings
            1. 12.2.5.3.1.1 Interface Selection
            2. 12.2.5.3.1.2 Reference Clock Distribution
            3. 12.2.5.3.1.3 Internal Reference Clock Selection
        4. 12.2.5.4 SerDes Functional Description
          1. 12.2.5.4.1 SerDes Block Diagram
          2. 12.2.5.4.2 SerDes Programming Guide
    3. 12.3 Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 FSS Not Supported Features
        2. 12.3.1.2 FSS Environment
          1. 12.3.1.2.1 FSS Typical Application
        3. 12.3.1.3 FSS Integration
          1. 12.3.1.3.1 FSS Integration in MCU Domain
        4. 12.3.1.4 FSS Functional Description
          1. 12.3.1.4.1 FSS Block Diagram
          2. 12.3.1.4.2 FSS ECC Support
            1. 12.3.1.4.2.1 FSS ECC Calculation
          3. 12.3.1.4.3 FSS Modes of Operation
          4. 12.3.1.4.4 FSS Regions
            1. 12.3.1.4.4.1 FSS Regions Boot Size Configuration
          5. 12.3.1.4.5 FSS Memory Regions
        5. 12.3.1.5 FSS Programming Guide
          1. 12.3.1.5.1 FSS Initialization Sequence
          2. 12.3.1.5.2 FSS Real-Time Operation
          3. 12.3.1.5.3 FSS Power Up/Down Sequence
        6. 12.3.1.6 FSS Registers
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Not Supported Features
        2. 12.3.2.2 OSPI Environment
        3. 12.3.2.3 OSPI Integration
          1. 12.3.2.3.1 OSPI Integration in MCU Domain
        4. 12.3.2.4 OSPI Functional Description
          1. 12.3.2.4.1  OSPI Block Diagram
            1. 12.3.2.4.1.1 Data Target Interface
            2. 12.3.2.4.1.2 Configuration Target Interface
            3. 12.3.2.4.1.3 OSPI Clock Domains
          2. 12.3.2.4.2  OSPI Modes
            1. 12.3.2.4.2.1 Read Data Capture
              1. 12.3.2.4.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.4.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.4.2.1.3 Data Capturing Mechanism Using PHY Module
            2. 12.3.2.4.2.2 External Pull Down on DQS
          3. 12.3.2.4.3  OSPI Power Management
          4. 12.3.2.4.4  Auto HW Polling
          5. 12.3.2.4.5  Flash Reset
          6. 12.3.2.4.6  OSPI Memory Regions
          7. 12.3.2.4.7  OSPI Interrupt Requests
          8. 12.3.2.4.8  OSPI Data Interface
            1. 12.3.2.4.8.1 Data Interface Address Remapping
            2. 12.3.2.4.8.2 Write Protection
            3. 12.3.2.4.8.3 Access Forwarding
          9. 12.3.2.4.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.4.10.1 Indirect Read Controller
              1. 12.3.2.4.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.4.10.2 Indirect Write Controller
              1. 12.3.2.4.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.4.10.3 Indirect Access Queuing
            4. 12.3.2.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.4.10.5 Accessing the SRAM
          11. 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.4.11.1 Servicing a STIG Request
            2. 12.3.2.4.11.2 2576
          12. 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.4.13 OSPI Command Translation
          14. 12.3.2.4.14 Selecting the Flash Instruction Type
          15. 12.3.2.4.15 OSPI Data Integrity
          16. 12.3.2.4.16 OSPI PHY Module
            1. 12.3.2.4.16.1 PHY Pipeline Mode
            2. 12.3.2.4.16.2 Read Data Capturing by the PHY Module
        5. 12.3.2.5 OSPI Programming Guide
          1. 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.5.4 Using SPI Legacy Mode
          5. 12.3.2.5.5 Entering XIP Mode from POR
          6. 12.3.2.5.6 Entering XIP Mode Otherwise
          7. 12.3.2.5.7 Exiting XIP Mode
        6. 12.3.2.6 OSPI Registers
      3. 12.3.3 HyperBus Interface
        1. 12.3.3.1 HyperBus Overview
          1. 12.3.3.1.1 HyperBus Features
          2. 12.3.3.1.2 HyperBus Not Supported Features
        2. 12.3.3.2 HyperBus Environment
        3. 12.3.3.3 HyperBus Integration
          1. 12.3.3.3.1 HyperBus Integration in MCU Domain
        4. 12.3.3.4 HyperBus Functional Description
          1. 12.3.3.4.1 HyperBus Interrupts
          2. 12.3.3.4.2 HyperBus ECC Support
            1. 12.3.3.4.2.1 ECC Aggregator
          3. 12.3.3.4.3 HyperBus Internal FIFOs
          4. 12.3.3.4.4 HyperBus Data Regions
          5. 12.3.3.4.5 HyperBus True Continuous Read (TCR) Mode
        5. 12.3.3.5 HyperBus Programming Guide
          1. 12.3.3.5.1 HyperBus Initialization Sequence
            1. 12.3.3.5.1.1 HyperFlash Access
            2. 12.3.3.5.1.2 HyperRAM Access
          2. 12.3.3.5.2 HyperBus Real-time Operating Requirements
          3. 12.3.3.5.3 HyperBus Power Up/Down Sequence
        6. 12.3.3.6 HyperBus Registers
      4. 12.3.4 General-Purpose Memory Controller (GPMC)
        1. 12.3.4.1 GPMC Overview
          1. 12.3.4.1.1 GPMC Features
          2. 12.3.4.1.2 GPMC Not Supported Features
        2. 12.3.4.2 GPMC Environment
          1. 12.3.4.2.1 GPMC Modes
          2. 12.3.4.2.2 GPMC I/O Signals
        3. 12.3.4.3 GPMC Integration
          1. 12.3.4.3.1 GPMC Integration in MAIN Domain
        4. 12.3.4.4 GPMC Functional Description
          1. 12.3.4.4.1  GPMC Block Diagram
          2. 12.3.4.4.2  GPMC Clock Configuration
          3. 12.3.4.4.3  GPMC Power Management
          4. 12.3.4.4.4  GPMC Interrupt Requests
          5. 12.3.4.4.5  GPMC Interconnect Port Interface
          6. 12.3.4.4.6  GPMC Address and Data Bus
            1. 12.3.4.4.6.1 GPMC I/O Configuration Setting
          7. 12.3.4.4.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.4.4.7.1 Chip-Select Base Address and Region Size
            2. 12.3.4.4.7.2 Access Protocol
              1. 12.3.4.4.7.2.1 Supported Devices
              2. 12.3.4.4.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.4.4.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.4.4.7.3 External Signals
              1. 12.3.4.4.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.4.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.4.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.4.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.4.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.4.4.7.3.1.5 Wait With NAND Device
                6. 12.3.4.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.4.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.4.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.4.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.4.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.4.4.7.3.2 DIR Pin
              3. 12.3.4.4.7.3.3 Reset
              4. 12.3.4.4.7.3.4 Write Protect Signal (nWP)
              5. 12.3.4.4.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.4.4.7.4 Error Handling
          8. 12.3.4.4.8  GPMC Timing Setting
            1. 12.3.4.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.4.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.4.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.4.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.4.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.4.4.8.6  GPMC_CLKOUT
            7. 12.3.4.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.4.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.4.4.8.8.1 Access Time on Read Access
              2. 12.3.4.4.8.8.2 Access Time on Write Access
            9. 12.3.4.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.4.4.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.4.4.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.4.4.8.10 Bus Keeping Support
          9. 12.3.4.4.9  GPMC NOR Access Description
            1. 12.3.4.4.9.1 Asynchronous Access Description
              1. 12.3.4.4.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.4.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.4.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.4.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.4.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.4.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.4.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.4.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.4.4.9.2 Synchronous Access Description
              1. 12.3.4.4.9.2.1 Synchronous Single Read
              2. 12.3.4.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.4.4.9.2.3 Synchronous Single Write
              4. 12.3.4.4.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.4.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.4.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.4.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.4.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.4.4.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.4.4.9.4 Page and Burst Support
            5. 12.3.4.4.9.5 System Burst vs External Device Burst Support
          10. 12.3.4.4.10 GPMC pSRAM Access Specificities
          11. 12.3.4.4.11 GPMC NAND Access Description
            1. 12.3.4.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.4.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.4.4.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.4.4.11.1.3 Command Latch Cycle
              4. 12.3.4.4.11.1.4 Address Latch Cycle
              5. 12.3.4.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.4.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.4.4.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.4.4.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.4.4.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.4.4.11.2 NAND Device-Ready Pin
              1. 12.3.4.4.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.4.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.4.4.11.3 ECC Calculator
              1. 12.3.4.4.11.3.1 Hamming Code
                1. 12.3.4.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.4.4.11.3.1.2 ECC Enabling
                3. 12.3.4.4.11.3.1.3 ECC Computation
                4. 12.3.4.4.11.3.1.4 ECC Comparison and Correction
                5. 12.3.4.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.4.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.4.4.11.3.2 BCH Code
                1. 12.3.4.4.11.3.2.1 Requirements
                2. 12.3.4.4.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.4.4.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.4.4.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.4.4.11.3.2.2.3 Wrapping Modes
                    1. 4.4.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 4.4.11.3.2.2.3.2  Mode 0x1
                    3. 4.4.11.3.2.2.3.3  Mode 0xA (10)
                    4. 4.4.11.3.2.2.3.4  Mode 0x2
                    5. 4.4.11.3.2.2.3.5  Mode 0x3
                    6. 4.4.11.3.2.2.3.6  Mode 0x7
                    7. 4.4.11.3.2.2.3.7  Mode 0x8
                    8. 4.4.11.3.2.2.3.8  Mode 0x4
                    9. 4.4.11.3.2.2.3.9  Mode 0x9
                    10. 4.4.11.3.2.2.3.10 Mode 0x5
                    11. 4.4.11.3.2.2.3.11 Mode 0xB (11)
                    12. 4.4.11.3.2.2.3.12 Mode 0x6
                3. 12.3.4.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.4.4.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.4.4.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.4.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.4.4.11.4 Prefetch and Write-Posting Engine
              1. 12.3.4.4.11.4.1 General Facts About the Engine Configuration
              2. 12.3.4.4.11.4.2 Prefetch Mode
              3. 12.3.4.4.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.4.4.11.4.4 Write-Posting Mode
              5. 12.3.4.4.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.4.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.4.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.4.4.12 GPMC Use Cases and Tips
            1. 12.3.4.4.12.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.4.4.12.1.1 External Memory Attached to the GPMC Module
              2. 12.3.4.4.12.1.2 Typical GPMC Setup
                1. 12.3.4.4.12.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.4.4.12.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.4.4.12.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.4.4.12.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.4.4.12.2.1 Supported Memories or Devices
                1. 12.3.4.4.12.2.1.1 Memory Pin Multiplexing
                2. 12.3.4.4.12.2.1.2 NAND Interface Protocol
                3. 12.3.4.4.12.2.1.3 NOR Interface Protocol
                4. 12.3.4.4.12.2.1.4 Other Technologies
        5. 12.3.4.5 GPMC Basic Programming Model
          1. 12.3.4.5.1 GPMC High-Level Programming Model Overview
          2. 12.3.4.5.2 GPMC Initialization
          3. 12.3.4.5.3 GPMC Configuration in NOR Mode
          4. 12.3.4.5.4 GPMC Configuration in NAND Mode
          5. 12.3.4.5.5 Set Memory Access
          6. 12.3.4.5.6 GPMC Timing Parameters
            1. 12.3.4.5.6.1 GPMC Timing Parameters Formulas
              1. 12.3.4.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.4.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.4.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
        6. 12.3.4.6 GPMC Registers
      5. 12.3.5 Error Location Module (ELM)
        1. 12.3.5.1 ELM Overview
          1. 12.3.5.1.1 ELM Features
          2. 12.3.5.1.2 ELM Not Supported Features
        2. 12.3.5.2 ELM Integration
          1. 12.3.5.2.1 ELM Integration in MAIN Domain
        3. 12.3.5.3 ELM Functional Description
          1. 12.3.5.3.1 ELM Software Reset
          2. 12.3.5.3.2 ELM Power Management
          3. 12.3.5.3.3 ELM Interrupt Requests
          4. 12.3.5.3.4 ELM Processing Initialization
          5. 12.3.5.3.5 ELM Processing Sequence
          6. 12.3.5.3.6 ELM Processing Completion
        4. 12.3.5.4 ELM Basic Programming Model
          1. 12.3.5.4.1 ELM Low-Level Programming Model
            1. 12.3.5.4.1.1 Processing Initialization
            2. 12.3.5.4.1.2 Read Results
            3. 12.3.5.4.1.3 2786
          2. 12.3.5.4.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.5.4.3 Use Case: ELM Used in Page Mode
        5. 12.3.5.5 ELM Registers
      6. 12.3.6 Multi-Media Card Secure Digital (MMCSD) Interface
        1. 12.3.6.1 MMCSD Overview
          1. 12.3.6.1.1 MMCSD Features
          2. 12.3.6.1.2 MMCSD Not Supported Features
        2. 12.3.6.2 MMCSD Environment
          1. 12.3.6.2.1 Protocol and Data Format
            1. 12.3.6.2.1.1 Protocol
            2. 12.3.6.2.1.2 Data Format
              1. 12.3.6.2.1.2.1 Coding Scheme for Command Token
              2. 12.3.6.2.1.2.2 Coding Scheme for Response Token
              3. 12.3.6.2.1.2.3 Coding Scheme for Data Token
        3. 12.3.6.3 MMCSD Integration
          1. 12.3.6.3.1 MMCSD Integration in MAIN Domain
        4. 12.3.6.4 MMCSD Functional Description
          1. 12.3.6.4.1 Block Diagram
          2. 12.3.6.4.2 Memory Regions
          3. 12.3.6.4.3 Interrupt Requests
          4. 12.3.6.4.4 ECC Support
            1. 12.3.6.4.4.1 ECC Aggregator
          5. 12.3.6.4.5 Advanced DMA
          6. 12.3.6.4.6 eMMC PHY BIST
            1. 12.3.6.4.6.1 BIST Overview
            2. 12.3.6.4.6.2 BIST Modes
              1. 12.3.6.4.6.2.1 DS Mode
              2. 12.3.6.4.6.2.2 HS Mode with TXDLY using DLL
              3. 12.3.6.4.6.2.3 HS Mode with TXDLY using Delay Chain
              4. 12.3.6.4.6.2.4 DDR50 Mode with TXDLY using DLL
              5. 12.3.6.4.6.2.5 DDR50 Mode with TXDLY using Delay Chain
              6. 12.3.6.4.6.2.6 HS200 Mode with TX/RXDLY using DLL
              7. 12.3.6.4.6.2.7 HS200 Mode with TX/RXDLY using Delay Chain
              8. 12.3.6.4.6.2.8 HS400 Mode
            3. 12.3.6.4.6.3 BIST Functionality
            4. 12.3.6.4.6.4 Signal Interface
            5. 12.3.6.4.6.5 Programming Flow
              1. 12.3.6.4.6.5.1 DS Mode
                1. 12.3.6.4.6.5.1.1 Configuration
                2. 12.3.6.4.6.5.1.2 BIST Programming
              2. 12.3.6.4.6.5.2 HS Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.2.1 Configuration
                2. 12.3.6.4.6.5.2.2 BIST Programming
              3. 12.3.6.4.6.5.3 HS Mode with DLL
                1. 12.3.6.4.6.5.3.1 Configuration
                2. 12.3.6.4.6.5.3.2 BIST Programming
              4. 12.3.6.4.6.5.4 DDR52 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.4.1 Configuration
                2. 12.3.6.4.6.5.4.2 BIST Programming
              5. 12.3.6.4.6.5.5 DDR52 Mode with DLL
                1. 12.3.6.4.6.5.5.1 Configuration
                2. 12.3.6.4.6.5.5.2 BIST Programming
              6. 12.3.6.4.6.5.6 HS200 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.6.1 Configuration
                2. 12.3.6.4.6.5.6.2 BIST Programming
              7. 12.3.6.4.6.5.7 HS200 Mode with DLL
                1. 12.3.6.4.6.5.7.1 Configuration
                2. 12.3.6.4.6.5.7.2 BIST Programming
              8. 12.3.6.4.6.5.8 HS400 Mode with DLL
                1. 12.3.6.4.6.5.8.1 Configuration
                2. 12.3.6.4.6.5.8.2 BIST Programming
            6. 12.3.6.4.6.6 HS200 BIST Result Check Procedure
        5. 12.3.6.5 MMCSD Programming Guide
          1. 12.3.6.5.1 Sequences
            1. 12.3.6.5.1.1  SD Card Detection
            2. 12.3.6.5.1.2  SD Clock Control
              1. 12.3.6.5.1.2.1 Internal Clock Setup Sequence
              2. 12.3.6.5.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.6.5.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.6.5.1.3  SD Bus Power Control
            4. 12.3.6.5.1.4  Changing Bus Width
            5. 12.3.6.5.1.5  Timeout Setting on DAT Line
            6. 12.3.6.5.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.6.5.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.6.5.1.7  SD Transaction Generation
              1. 12.3.6.5.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.6.5.1.7.1.2 The Sequence to Finalize a Command
                3. 12.3.6.5.1.7.1.3 2865
              2. 12.3.6.5.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.2.1 Not using DMA
                2. 12.3.6.5.1.7.2.2 Using SDMA
                3. 12.3.6.5.1.7.2.3 Using ADMA
            8. 12.3.6.5.1.8  Abort Transaction
              1. 12.3.6.5.1.8.1 Asynchronous Abort
              2. 12.3.6.5.1.8.2 Synchronous Abort
            9. 12.3.6.5.1.9  Changing Bus Speed Mode
            10. 12.3.6.5.1.10 Error Recovery
              1. 12.3.6.5.1.10.1 Error Interrupt Recovery
              2. 12.3.6.5.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.6.5.1.11 Wakeup Control (Optional)
            12. 12.3.6.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.6.5.1.12.1 Suspend Sequence
              2. 12.3.6.5.1.12.2 Resume Sequence
              3. 12.3.6.5.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.6.5.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.6.5.2 Driver Flow Sequence
            1. 12.3.6.5.2.1 Host Controller Setup and Card Detection
              1. 12.3.6.5.2.1.1 Host Controller Setup Sequence
              2. 12.3.6.5.2.1.2 Card Interface Detection Sequence
            2. 12.3.6.5.2.2 Boot Operation
              1. 12.3.6.5.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.6.5.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.6.5.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.6.5.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.6.5.2.3.1 Sampling Clock Tuning
              2. 12.3.6.5.2.3.2 Tuning Modes
              3. 12.3.6.5.2.3.3 Re-Tuning Mode 2
            4. 12.3.6.5.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.6.5.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.6.5.2.4.2 Task Issuance Sequence
              3. 12.3.6.5.2.4.3 Task Execution and Completion Sequence
              4. 12.3.6.5.2.4.4 Task Discard and Clear Sequence
              5. 12.3.6.5.2.4.5 Error Detect and Recovery when CQ is enabled
        6. 12.3.6.6 MMCSD Registers
          1. 12.3.6.6.1 MMCSD0 Subsystem Registers
          2. 12.3.6.6.2 MMCSD0 RX RAM ECC Aggregator Registers
          3. 12.3.6.6.3 MMCSD0 TX RAM ECC Aggregator Registers
          4. 12.3.6.6.4 MMCSD0 Host Controller Registers
          5. 12.3.6.6.5 MMCSD1 Subsystem Registers
          6. 12.3.6.6.6 MMCSD1 RX RAM ECC Aggregator Registers
          7. 12.3.6.6.7 MMCSD1 TX RAM ECC Aggregator Registers
          8. 12.3.6.6.8 MMCSD1 Host Controller Registers
    4. 12.4 Industrial and Control Interfaces
      1. 12.4.1 Enhanced Capture (ECAP) Module
        1. 12.4.1.1 ECAP Overview
          1. 12.4.1.1.1 ECAP Features
        2. 12.4.1.2 ECAP Environment
          1. 12.4.1.2.1 ECAP I/O Interface
        3. 12.4.1.3 ECAP Integration
          1. 12.4.1.3.1 Daisy-Chain Connectivity between ECAP Modules
        4. 12.4.1.4 ECAP Functional Description
          1. 12.4.1.4.1 Capture and APWM Operating Modes
            1. 12.4.1.4.1.1 ECAP Capture Mode Description
              1. 12.4.1.4.1.1.1 ECAP Event Prescaler
              2. 12.4.1.4.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.1.4.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.1.4.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.1.4.1.1.5 CAP1-CAP4 Registers
              6. 12.4.1.4.1.1.6 ECAP Interrupt Control
              7. 12.4.1.4.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.1.4.1.2 ECAP APWM Mode Operation
          2. 12.4.1.4.2 Summary of ECAP Functional Registers
        5. 12.4.1.5 ECAP Use Cases
          1. 12.4.1.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.1.5.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.1.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.1.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.1.5.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.1.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.1.5.5 Application of the APWM Mode
            1. 12.4.1.5.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.1.5.5.1.1 Code Snippet for APWM Mode
            2. 12.4.1.5.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.1.5.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.1.5.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.1.5.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
        6. 12.4.1.6 ECAP Registers
      2. 12.4.2 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.2.1 EPWM Overview
          1. 12.4.2.1.1 EPWM Features
          2. 12.4.2.1.2 EPWM Not Supported Features
          3. 12.4.2.1.3 2951
        2. 12.4.2.2 EPWM Environment
          1. 12.4.2.2.1 EPWM I/O Interface
        3. 12.4.2.3 EPWM Integration
          1. 12.4.2.3.1 Device Specific EPWM Features
          2. 12.4.2.3.2 Daisy-Chain Connectivity between EPWM Modules
          3. 12.4.2.3.3 ADC start of conversion signals (PWM_SOCA and PWM_SOCB)
          4. 12.4.2.3.4 EPWM Modules Time Base Clock Gating
        4. 12.4.2.4 EPWM Functional Description
          1. 12.4.2.4.1  EPWM Submodule Features
            1. 12.4.2.4.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.2.4.2  EPWM Time-Base (TB) Submodule
            1. 12.4.2.4.2.1 Overview
            2. 12.4.2.4.2.2 2964
            3. 12.4.2.4.2.3 Controlling and Monitoring the EPWM Time-Base Submodule
            4. 12.4.2.4.2.4 Calculating PWM Period and Frequency
              1. 12.4.2.4.2.4.1 EPWM Time-Base Period Shadow Register
              2. 12.4.2.4.2.4.2 EPWM Time-Base Counter Synchronization
            5. 12.4.2.4.2.5 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            6. 12.4.2.4.2.6 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.2.4.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.2.4.3.1 Overview
            2. 12.4.2.4.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.2.4.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.2.4.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.2.4.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.2.4.4.1 Overview
            2. 12.4.2.4.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.2.4.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.2.4.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.2.4.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.2.4.5.1 Overview
            2. 12.4.2.4.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.2.4.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.2.4.6  EPWM-Chopper (PC) Submodule
            1. 12.4.2.4.6.1 Overview
            2. 12.4.2.4.6.2 2987
            3. 12.4.2.4.6.3 Controlling the EPWM-Chopper Submodule
            4. 12.4.2.4.6.4 Operational Highlights for the EPWM-Chopper Submodule
            5. 12.4.2.4.6.5 EPWM-Chopper Waveforms
              1. 12.4.2.4.6.5.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.2.4.6.5.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.2.4.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.2.4.7.1 Overview
            2. 12.4.2.4.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.2.4.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.2.4.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.2.4.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.2.4.8.1 Overview
            2. 12.4.2.4.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.2.4.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.2.4.8.4 3002
          9. 12.4.2.4.9  EPWM High Resolution (HRPWM) Submodule
            1. 12.4.2.4.9.1 Overview
            2. 12.4.2.4.9.2 Architecture of the High-Resolution PWM Submodule
            3. 12.4.2.4.9.3 Controlling and Monitoring the High-Resolution PWM Submodule
            4. 12.4.2.4.9.4 Configuring the High-Resolution PWM Submodule
            5. 12.4.2.4.9.5 Operational Highlights for the High-Resolution PWM Submodule
              1. 12.4.2.4.9.5.1 HRPWM Edge Positioning
              2. 12.4.2.4.9.5.2 HRPWM Scaling Considerations
              3. 12.4.2.4.9.5.3 HRPWM Duty Cycle Range Limitation
          10. 12.4.2.4.10 EPWM / HRPWM Functional Register Groups
          11. 12.4.2.4.11 Proper EPWM Interrupt Initialization Procedure
        5. 12.4.2.5 EPWM Registers
      3. 12.4.3 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.3.1 EQEP Overview
          1. 12.4.3.1.1 EQEP Features
          2. 12.4.3.1.2 EQEP Not Supported Features
        2. 12.4.3.2 EQEP Environment
          1. 12.4.3.2.1 EQEP I/O Interface
        3. 12.4.3.3 EQEP Integration
          1. 12.4.3.3.1 Device Specific EQEP Features
        4. 12.4.3.4 EQEP Functional Description
          1. 12.4.3.4.1 EQEP Inputs
          2. 12.4.3.4.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.3.4.2.1 EQEP Position Counter Input Modes
              1. 12.4.3.4.2.1.1 Quadrature Count Mode
              2. 12.4.3.4.2.1.2 EQEP Direction-count Mode
              3. 12.4.3.4.2.1.3 EQEP Up-Count Mode
              4. 12.4.3.4.2.1.4 EQEP Down-Count Mode
            2. 12.4.3.4.2.2 EQEP Input Polarity Selection
            3. 12.4.3.4.2.3 EQEP Position-Compare Sync Output
          3. 12.4.3.4.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.3.4.3.1 EQEP Position Counter Operating Modes
              1. 12.4.3.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.3.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.3.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.3.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.3.4.3.2 EQEP Position Counter Latch
              1. 12.4.3.4.3.2.1 Index Event Latch
              2. 12.4.3.4.3.2.2 EQEP Strobe Event Latch
            3. 12.4.3.4.3.3 EQEP Position Counter Initialization
            4. 12.4.3.4.3.4 EQEP Position-Compare Unit
          4. 12.4.3.4.4 EQEP Edge Capture Unit
          5. 12.4.3.4.5 EQEP Watchdog
          6. 12.4.3.4.6 Unit Timer Base
          7. 12.4.3.4.7 EQEP Interrupt Structure
          8. 12.4.3.4.8 Summary of EQEP Functional Registers
        5. 12.4.3.5 EQEP Registers
      4. 12.4.4 Controller Area Network (MCAN)
        1. 12.4.4.1 MCAN Overview
          1. 12.4.4.1.1 MCAN Features
          2. 12.4.4.1.2 MCAN Not Supported Features
        2. 12.4.4.2 MCAN Environment
          1. 12.4.4.2.1 CAN Network Basics
        3. 12.4.4.3 MCAN Integration
          1. 12.4.4.3.1 MCAN Integration in MCU Domain
          2. 12.4.4.3.2 MCAN Integration in MAIN Domain
        4. 12.4.4.4 MCAN Functional Description
          1. 12.4.4.4.1  Module Clocking Requirements
          2. 12.4.4.4.2  Interrupt and DMA Requests
            1. 12.4.4.4.2.1 Interrupt Requests
            2. 12.4.4.4.2.2 DMA Requests
            3. 12.4.4.4.2.3 3064
          3. 12.4.4.4.3  Operating Modes
            1. 12.4.4.4.3.1 Software Initialization
            2. 12.4.4.4.3.2 Normal Operation
            3. 12.4.4.4.3.3 CAN FD Operation
            4. 12.4.4.4.3.4 Transmitter Delay Compensation
              1. 12.4.4.4.3.4.1 Description
              2. 12.4.4.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.4.4.3.5 Restricted Operation Mode
            6. 12.4.4.4.3.6 Bus Monitoring Mode
            7. 12.4.4.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.4.4.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.4.4.3.8 Power Down (Sleep Mode)
              1. 12.4.4.4.3.8.1 External Clock Stop Mode
              2. 12.4.4.4.3.8.2 Suspend Mode
              3. 12.4.4.4.3.8.3 Wakeup request
            9. 12.4.4.4.3.9 Test Modes
              1. 12.4.4.4.3.9.1 Internal Loopback Mode
          4. 12.4.4.4.4  Timestamp Generation
            1. 12.4.4.4.4.1 External Timestamp Counter
          5. 12.4.4.4.5  Timeout Counter
          6. 12.4.4.4.6  ECC Support
            1. 12.4.4.4.6.1 ECC Wrapper
            2. 12.4.4.4.6.2 ECC Aggregator
          7. 12.4.4.4.7  Rx Handling
            1. 12.4.4.4.7.1 Acceptance Filtering
              1. 12.4.4.4.7.1.1 Range Filter
              2. 12.4.4.4.7.1.2 Filter for specific IDs
              3. 12.4.4.4.7.1.3 Classic Bit Mask Filter
              4. 12.4.4.4.7.1.4 Standard Message ID Filtering
              5. 12.4.4.4.7.1.5 Extended Message ID Filtering
            2. 12.4.4.4.7.2 Rx FIFOs
              1. 12.4.4.4.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.4.4.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.4.4.7.3 Dedicated Rx Buffers
              1. 12.4.4.4.7.3.1 Rx Buffer Handling
            4. 12.4.4.4.7.4 Debug on CAN Support
          8. 12.4.4.4.8  Tx Handling
            1. 12.4.4.4.8.1 Transmit Pause
            2. 12.4.4.4.8.2 Dedicated Tx Buffers
            3. 12.4.4.4.8.3 Tx FIFO
            4. 12.4.4.4.8.4 Tx Queue
            5. 12.4.4.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.4.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.4.4.8.7 Transmit Cancellation
            8. 12.4.4.4.8.8 Tx Event Handling
          9. 12.4.4.4.9  FIFO Acknowledge Handling
          10. 12.4.4.4.10 Message RAM
            1. 12.4.4.4.10.1 Message RAM Configuration
            2. 12.4.4.4.10.2 Rx Buffer and FIFO Element
            3. 12.4.4.4.10.3 Tx Buffer Element
            4. 12.4.4.4.10.4 Tx Event FIFO Element
            5. 12.4.4.4.10.5 Standard Message ID Filter Element
            6. 12.4.4.4.10.6 Extended Message ID Filter Element
        5. 12.4.4.5 MCAN Registers
          1. 12.4.4.5.1 MCAN Subsystem Registers
          2. 12.4.4.5.2 MCAN Core Registers
          3. 12.4.4.5.3 MCAN ECC Aggregator Registers
    5. 12.5 Audio Interfaces
      1. 12.5.1 Audio Tracking Logic (ATL)
        1. 12.5.1.1 ATL Overview
          1. 12.5.1.1.1 ATL Features Overview
          2. 12.5.1.1.2 ATL Not Supported Features
    6. 12.6 Timer Modules
      1. 12.6.1 Global Timebase Counter (GTC)
        1. 12.6.1.1 GTC Overview
          1. 12.6.1.1.1 GTC Features
          2. 12.6.1.1.2 GTC Not Supported Features
        2. 12.6.1.2 GTC Integration
        3. 12.6.1.3 GTC Functional Description
          1. 12.6.1.3.1 GTC Block Diagram
          2. 12.6.1.3.2 GTC Counter
          3. 12.6.1.3.3 GTC Gray Encoder
          4. 12.6.1.3.4 GTC Push Event Generation
          5. 12.6.1.3.5 GTC Register Partitioning
        4. 12.6.1.4 GTC Registers
          1. 12.6.1.4.1 GTC0_GTC_CFG0 Registers
          2. 12.6.1.4.2 GTC0_GTC_CFG1 Registers
          3. 12.6.1.4.3 GTC0_GTC_CFG2 Registers
          4. 12.6.1.4.4 GTC0_GTC_CFG3 Registers
      2. 12.6.2 Windowed Watchdog Timer (WWDT)
        1. 12.6.2.1 RTI Overview
          1. 12.6.2.1.1 RTI Features
          2. 12.6.2.1.2 RTI Not Supported Features
        2. 12.6.2.2 RTI Integration
          1. 12.6.2.2.1 RTI Integration in MCU Domain
          2. 12.6.2.2.2 RTI Integration in MAIN Domain
        3. 12.6.2.3 RTI Functional Description
          1. 12.6.2.3.1 RTI Counter Operation
          2. 12.6.2.3.2 RTI Digital Watchdog
          3. 12.6.2.3.3 RTI Digital Windowed Watchdog
          4. 12.6.2.3.4 RTI Low Power Mode Operation
          5. 12.6.2.3.5 RTI Debug Mode Behavior
        4. 12.6.2.4 RTI Registers
      3. 12.6.3 Timers
        1. 12.6.3.1 Timers Overview
          1. 12.6.3.1.1 Timers Features
          2. 12.6.3.1.2 Timers Not Supported Features
        2. 12.6.3.2 Timers Environment
          1. 12.6.3.2.1 Timer External System Interface
        3. 12.6.3.3 Timers Integration
          1. 12.6.3.3.1 Timers Integration in MCU Domain
          2. 12.6.3.3.2 Timers Integration in MAIN Domain
        4. 12.6.3.4 Timers Functional Description
          1. 12.6.3.4.1  Timer Block Diagram
          2. 12.6.3.4.2  Timer Power Management
            1. 12.6.3.4.2.1 Wake-Up Capability
          3. 12.6.3.4.3  Timer Software Reset
          4. 12.6.3.4.4  Timer Interrupts
          5. 12.6.3.4.5  Timer Mode Functionality
            1. 12.6.3.4.5.1 1-ms Tick Generation
          6. 12.6.3.4.6  Timer Capture Mode Functionality
          7. 12.6.3.4.7  Timer Compare Mode Functionality
          8. 12.6.3.4.8  Timer Prescaler Functionality
          9. 12.6.3.4.9  Timer Pulse-Width Modulation
          10. 12.6.3.4.10 Timer Counting Rate
          11. 12.6.3.4.11 Timer Under Emulation
          12. 12.6.3.4.12 Accessing Timer Registers
            1. 12.6.3.4.12.1 Writing to Timer Registers
              1. 12.6.3.4.12.1.1 Write Posting Synchronization Mode
              2. 12.6.3.4.12.1.2 Write Nonposting Synchronization Mode
            2. 12.6.3.4.12.2 Reading From Timer Counter Registers
              1. 12.6.3.4.12.2.1 Read Posted
              2. 12.6.3.4.12.2.2 Read Non-Posted
          13. 12.6.3.4.13 Timer Posted Mode Selection
        5. 12.6.3.5 Timers Low-Level Programming Models
          1. 12.6.3.5.1 Timer Global Initialization
            1. 12.6.3.5.1.1 Global Initialization of Surrounding Modules
            2. 12.6.3.5.1.2 Timer Module Global Initialization
              1. 12.6.3.5.1.2.1 Main Sequence – Timer Module Global Initialization
          2. 12.6.3.5.2 Timer Operational Mode Configuration
            1. 12.6.3.5.2.1 Timer Mode
              1. 12.6.3.5.2.1.1 Main Sequence – Timer Mode Configuration
            2. 12.6.3.5.2.2 Timer Compare Mode
              1. 12.6.3.5.2.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.6.3.5.2.3 Timer Capture Mode
              1. 12.6.3.5.2.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.6.3.5.2.3.2 Subsequence – Initialize Capture Mode
              3. 12.6.3.5.2.3.3 Subsequence – Detect Event
            4. 12.6.3.5.2.4 Timer PWM Mode
              1. 12.6.3.5.2.4.1 Main Sequence – Timer PWM Mode Configuration
        6. 12.6.3.6 Timers Registers
    7. 12.7 Internal Diagnostics Modules
      1. 12.7.1 Dual Clock Comparator (DCC)
        1. 12.7.1.1 DCC Overview
          1. 12.7.1.1.1 DCC Features
          2. 12.7.1.1.2 DCC Not Supported Features
        2. 12.7.1.2 DCC Integration
          1. 12.7.1.2.1 DCC Integration in MCU Domain
          2. 12.7.1.2.2 DCC Integration in MAIN Domain
        3. 12.7.1.3 DCC Functional Description
          1. 12.7.1.3.1 DCC Counter Operation
          2. 12.7.1.3.2 DCC Low Power Mode Operation
          3. 12.7.1.3.3 DCC Suspend Mode Behavior
          4. 12.7.1.3.4 DCC Single-Shot Mode
          5. 12.7.1.3.5 DCC Continuous mode
            1. 12.7.1.3.5.1 DCC Continue on Error
            2. 12.7.1.3.5.2 DCC Error Count
          6. 12.7.1.3.6 DCC Control and count hand-off across clock domains
          7. 12.7.1.3.7 DCC Error Trajectory record
            1. 12.7.1.3.7.1 DCC FIFO capturing for Errors
            2. 12.7.1.3.7.2 DCC FIFO in continuous capture mode
            3. 12.7.1.3.7.3 DCC FIFO Details
            4. 12.7.1.3.7.4 DCC FIFO Debug mode behavior
          8. 12.7.1.3.8 DCC Count read registers
        4. 12.7.1.4 DCC Registers
      2. 12.7.2 Error Signaling Module (ESM)
        1. 12.7.2.1 ESM Overview
          1. 12.7.2.1.1 ESM Features
        2. 12.7.2.2 ESM Environment
        3. 12.7.2.3 ESM Integration
          1. 12.7.2.3.1 ESM Integration in WKUP Domain
          2. 12.7.2.3.2 ESM Integration in MCU Domain
          3. 12.7.2.3.3 ESM Integration in MAIN Domain
        4. 12.7.2.4 ESM Functional Description
          1. 12.7.2.4.1 ESM Interrupt Requests
            1. 12.7.2.4.1.1 ESM Configuration Error Interrupt
            2. 12.7.2.4.1.2 ESM Low Priority Error Interrupt
              1. 12.7.2.4.1.2.1 ESM Low Priority Error Level Event
              2. 12.7.2.4.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.7.2.4.1.3 ESM High Priority Error Interrupt
              1. 12.7.2.4.1.3.1 ESM High Priority Error Level Event
              2. 12.7.2.4.1.3.2 ESM High Priority Error Pulse Event
          2. 12.7.2.4.2 ESM Error Event Inputs
          3. 12.7.2.4.3 ESM Error Pin Output
          4. 12.7.2.4.4 ESM Minimum Time Interval
          5. 12.7.2.4.5 ESM Protection for Registers
          6. 12.7.2.4.6 ESM Clock Stop
        5. 12.7.2.5 ESM Registers
      3. 12.7.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.7.3.1 MCRC Overview
          1. 12.7.3.1.1 MCRC Features
          2. 12.7.3.1.2 MCRC Not Supported Features
        2. 12.7.3.2 MCRC Integration
        3. 12.7.3.3 MCRC Functional Description
          1. 12.7.3.3.1  MCRC Block Diagram
          2. 12.7.3.3.2  MCRC General Operation
          3. 12.7.3.3.3  MCRC Modes of Operation
            1. 12.7.3.3.3.1 AUTO Mode
            2. 12.7.3.3.3.2 Semi-CPU Mode
            3. 12.7.3.3.3.3 Full-CPU Mode
          4. 12.7.3.3.4  PSA Signature Register
          5. 12.7.3.3.5  PSA Sector Signature Register
          6. 12.7.3.3.6  CRC Value Register
          7. 12.7.3.3.7  Raw Data Register
          8. 12.7.3.3.8  Example DMA Controller Setup
            1. 12.7.3.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.7.3.3.8.2 AUTO Mode Using Software Trigger
            3. 12.7.3.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.7.3.3.9  Pattern Count Register
          10. 12.7.3.3.10 Sector Count Register/Current Sector Register
          11. 12.7.3.3.11 Interrupts
            1. 12.7.3.3.11.1 Compression Complete Interrupt
            2. 12.7.3.3.11.2 CRC Fail Interrupt
            3. 12.7.3.3.11.3 Overrun Interrupt
            4. 12.7.3.3.11.4 Underrun Interrupt
            5. 12.7.3.3.11.5 Timeout Interrupt
            6. 12.7.3.3.11.6 Interrupt Offset Register
            7. 12.7.3.3.11.7 Error Handling
          12. 12.7.3.3.12 Power Down Mode
          13. 12.7.3.3.13 Emulation
        4. 12.7.3.4 MCRC Programming Examples
          1. 12.7.3.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.7.3.4.1.1 DMA Setup
            2. 12.7.3.4.1.2 Timer Setup
            3. 12.7.3.4.1.3 CRC Setup
          2. 12.7.3.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.7.3.4.2.1 DMA Setup
            2. 12.7.3.4.2.2 CRC Setup
          3. 12.7.3.4.3 Example: Semi-CPU Mode
            1. 12.7.3.4.3.1 DMA Setup
            2. 12.7.3.4.3.2 Timer Setup
            3. 12.7.3.4.3.3 CRC Setup
          4. 12.7.3.4.4 Example: Full-CPU Mode
            1. 12.7.3.4.4.1 CRC Setup
        5. 12.7.3.5 MCRC Registers
      4. 12.7.4 ECC Aggregator
        1. 12.7.4.1 ECC Aggregator Overview
          1. 12.7.4.1.1 ECC Aggregator Features
        2. 12.7.4.2 ECC Aggregator Integration
        3. 12.7.4.3 ECC Aggregator Functional Description
          1. 12.7.4.3.1 ECC Aggregator Block Diagram
          2. 12.7.4.3.2 ECC Aggregator Register Groups
          3. 12.7.4.3.3 Read Access to the ECC Control and Status Registers
          4. 12.7.4.3.4 Serial Write Operation
          5. 12.7.4.3.5 Interrupts
          6. 12.7.4.3.6 Inject Only Mode
        4. 12.7.4.4 ECC Aggregator Registers
  15. 13On-Chip Debug
  16. 14Revision History

12.1.6.6 UART Registers

Table 12-786 lists the memory-mapped registers for the UART. All register offset addresses not listed in Table 12-786 should be considered as reserved locations and the register contents should not be modified.

Table 12-785 UART Instances
Instance Base Address
UART0 0280 0000h
UART1 0281 0000h
UART2 0282 0000h
UART3 0283 0000h
UART4 0284 0000h
UART5 0285 0000h
UART6 0286 0000h
UART7 0287 0000h
UART8 0288 0000h
UART9 0289 0000h
UART0 04A0 0000h
WKUP_UART0 4230 0000h
Table 12-786 UART Registers
Offset Acronym Register Name UART0 Physical Address UART1 Physical Address UART2 Physical Address
0h UART_THR Transmit holding register 0280 0000h 0281 0000h 0282 0000h
0h UART_RHR Receiver holding register 0280 0000h 0281 0000h 0282 0000h
0h UART_DLL Baud clock divisor LSB value register 0280 0000h 0281 0000h 0282 0000h
4h UART_IER_UART UART mode interrupt enable register 0280 0004h 0281 0004h 0282 0004h
4h UART_IER_IRDA IrDA mode interrupt enable register 0280 0004h 0281 0004h 0282 0004h
4h UART_IER_CIR CIR mode interrupt enable register 0280 0004h 0281 0004h 0282 0004h
4h UART_DLH Baud clock divisor MSB value register 0280 0004h 0281 0004h 0282 0004h
8h UART_IIR_UART UART mode interrupt identification register 0280 0008h 0281 0008h 0282 0008h
8h UART_IIR_IRDA IrDA mode interrupt identification register 0280 0008h 0281 0008h 0282 0008h
8h UART_IIR_CIR CIR mode interrupt identification register 0280 0008h 0281 0008h 0282 0008h
8h UART_FCR FIFO control register 0280 0008h 0281 0008h 0282 0008h
8h UART_EFR Enhanced feature register 0280 0008h 0281 0008h 0282 0008h
Ch UART_LCR Line control register 0280 000Ch 0281 000Ch 0282 000Ch
10h UART_MCR Modem control register 0280 0010h 0281 0010h 0282 0010h
10h UART_XON1_ADDR1 UART mode XON1 character, IrDA mode ADDR1 address register 0280 0010h 0281 0010h 0282 0010h
14h UART_LSR_UART UART mode line status register 0280 0014h 0281 0014h 0282 0014h
14h UART_LSR_IRDA IrDA mode line status register 0280 0014h 0281 0014h 0282 0014h
14h UART_LSR_CIR CIR mode line status register 0280 0014h 0281 0014h 0282 0014h
14h UART_XON2_ADDR2 UART mode XON2 character, IrDA mode ADDR2 address register 0280 0014h 0281 0014h 0282 0014h
18h UART_MSR Modem status register 0280 0018h 0281 0018h 0282 0018h
18h UART_XOFF1 UART mode XOFF1 character 0280 0018h 0281 0018h 0282 0018h
18h UART_TCR Transmission control register 0280 0018h 0281 0018h 0282 0018h
1Ch UART_SPR Scratchpad register 0280 001Ch 0281 001Ch 0282 001Ch
1Ch UART_XOFF2 UART mode XOFF2 character 0280 001Ch 0281 001Ch 0282 001Ch
1Ch UART_TLR Trigger level register 0280 001Ch 0281 001Ch 0282 001Ch
20h UART_MDR1 Mode definition register 1 0280 0020h 0281 0020h 0282 0020h
24h UART_MDR2 Mode definition register 2 0280 0024h 0281 0024h 0282 0024h
28h UART_SFLSR Status FIFO line status register 0280 0028h 0281 0028h 0282 0028h
28h UART_TXFLL Transmit frame length register low 0280 0028h 0281 0028h 0282 0028h
2Ch UART_RESUME Resume halted operation register 0280 002Ch 0281 002Ch 0282 002Ch
2Ch UART_TXFLH Transmit frame length register high 0280 002Ch 0281 002Ch 0282 002Ch
30h UART_SFREGL Status FIFO register low 0280 0030h 0281 0030h 0282 0030h
30h UART_RXFLL Received frame length register low 0280 0030h 0281 0030h 0282 0030h
34h UART_SFREGH Status FIFO register high 0280 0034h 0281 0034h 0282 0034h
34h UART_RXFLH Received frame length register high 0280 0034h 0281 0034h 0282 0034h
38h UART_BLR BOF control register 0280 0038h 0281 0038h 0282 0038h
38h UART_UASR UART autobauding status register 0280 0038h 0281 0038h 0282 0038h
3Ch UART_ACREG Auxiliary control register 0280 003Ch 0281 003Ch 0282 003Ch
40h UART_SCR Supplementary control register 0280 0040h 0281 0040h 0282 0040h
44h UART_SSR Supplementary status register 0280 0044h 0281 0044h 0282 0044h
48h UART_EBLR BOF length register 0280 0048h 0281 0048h 0282 0048h
50h UART_MVR Module version register 0280 0050h 0281 0050h 0282 0050h
54h UART_SYSC System configuration register 0280 0054h 0281 0054h 0282 0054h
58h UART_SYSS System status register 0280 0058h 0281 0058h 0282 0058h
5Ch UART_WER Wake-up enable register 0280 005Ch 0281 005Ch 0282 005Ch
60h UART_CFPS Carrier frequency prescaler register 0280 0060h 0281 0060h 0282 0060h
64h UART_RXFIFO_LVL RX FIFO level register 0280 0064h 0281 0064h 0282 0064h
68h UART_TXFIFO_LVL TX FIFO level register 0280 0068h 0281 0068h 0282 0068h
6Ch UART_IER2 Interrupt enable register 2 0280 006Ch 0281 006Ch 0282 006Ch
70h UART_ISR2 Interrupt status register 2 0280 0070h 0281 0070h 0282 0070h
74h UART_FREQ_SEL Sample per bit selector register 0280 0074h 0281 0074h 0282 0074h
78h UART_ABAUD_1ST_CHAR 0280 0078h 0281 0078h 0282 0078h
7Ch UART_BAUD_2ND_CHAR 0280 007Ch 0281 007Ch 0282 007Ch
80h UART_MDR3 Mode definition register 3 0280 0080h 0281 0080h 0282 0080h
84h UART_TX_DMA_THRESHOLD TX DMA threshold level register 0280 0084h 0281 0084h 0282 0084h
88h UART_MDR4 Mode definition register 4 0280 0088h 0281 0088h 0282 0088h
8Ch UART_EFR2 Enhanced features register 2 0280 008Ch 0281 008Ch 0282 008Ch
90h UART_ECR Enhanced control register 0280 0090h 0281 0090h 0282 0090h
94h UART_TIMEGUARD Timeguard register 0280 0094h 0281 0094h 0282 0094h
98h UART_TIMEOUTL Timeout lower byte register 0280 0098h 0281 0098h 0282 0098h
9Ch UART_TIMEOUTH Timeout higher byte register 0280 009Ch 0281 009Ch 0282 009Ch
A0h UART_SCCR Smartcard mode control register 0280 00A0h 0281 00A0h 0282 00A0h
A4h UART_ERHR Extended receive holding register 0280 00A4h 0281 00A4h 0282 00A4h
A4h UART_ETHR Extended transmit holding register 0280 00A4h 0281 00A4h 0282 00A4h
A8h UART_MAR Multidrop address register 0280 00A8h 0281 00A8h 0282 00A8h
ACh UART_MMR Multidrop mask register 0280 00ACh 0281 00ACh 0282 00ACh
B0h UART_MBR Multidrop broadcast address register 0280 00B0h 0281 00B0h 0282 00B0h
Table 12-787 UART Registers
Offset Acronym Register Name UART3 Physical Address UART4 Physical Address UART5 Physical Address
0h UART_THR Transmit holding register 0283 0000h 0284 0000h 0285 0000h
0h UART_RHR Receiver holding register 0283 0000h 0284 0000h 0285 0000h
0h UART_DLL Baud clock divisor LSB value register 0283 0000h 0284 0000h 0285 0000h
4h UART_IER_UART UART mode interrupt enable register 0283 0004h 0284 0004h 0285 0004h
4h UART_IER_IRDA IrDA mode interrupt enable register 0283 0004h 0284 0004h 0285 0004h
4h UART_IER_CIR CIR mode interrupt enable register 0283 0004h 0284 0004h 0285 0004h
4h UART_DLH Baud clock divisor MSB value register 0283 0004h 0284 0004h 0285 0004h
8h UART_IIR_UART UART mode interrupt identification register 0283 0008h 0284 0008h 0285 0008h
8h UART_IIR_IRDA IrDA mode interrupt identification register 0283 0008h 0284 0008h 0285 0008h
8h UART_IIR_CIR CIR mode interrupt identification register 0283 0008h 0284 0008h 0285 0008h
8h UART_FCR FIFO control register 0283 0008h 0284 0008h 0285 0008h
8h UART_EFR Enhanced feature register 0283 0008h 0284 0008h 0285 0008h
Ch UART_LCR Line control register 0283 000Ch 0284 000Ch 0285 000Ch
10h UART_MCR Modem control register 0283 0010h 0284 0010h 0285 0010h
10h UART_XON1_ADDR1 UART mode XON1 character, IrDA mode ADDR1 address register 0283 0010h 0284 0010h 0285 0010h
14h UART_LSR_UART UART mode line status register 0283 0014h 0284 0014h 0285 0014h
14h UART_LSR_IRDA IrDA mode line status register 0283 0014h 0284 0014h 0285 0014h
14h UART_LSR_CIR CIR mode line status register 0283 0014h 0284 0014h 0285 0014h
14h UART_XON2_ADDR2 UART mode XON2 character, IrDA mode ADDR2 address register 0283 0014h 0284 0014h 0285 0014h
18h UART_MSR Modem status register 0283 0018h 0284 0018h 0285 0018h
18h UART_XOFF1 UART mode XOFF1 character 0283 0018h 0284 0018h 0285 0018h
18h UART_TCR Transmission control register 0283 0018h 0284 0018h 0285 0018h
1Ch UART_SPR Scratchpad register 0283 001Ch 0284 001Ch 0285 001Ch
1Ch UART_XOFF2 UART mode XOFF2 character 0283 001Ch 0284 001Ch 0285 001Ch
1Ch UART_TLR Trigger level register 0283 001Ch 0284 001Ch 0285 001Ch
20h UART_MDR1 Mode definition register 1 0283 0020h 0284 0020h 0285 0020h
24h UART_MDR2 Mode definition register 2 0283 0024h 0284 0024h 0285 0024h
28h UART_SFLSR Status FIFO line status register 0283 0028h 0284 0028h 0285 0028h
28h UART_TXFLL Transmit frame length register low 0283 0028h 0284 0028h 0285 0028h
2Ch UART_RESUME Resume halted operation register 0283 002Ch 0284 002Ch 0285 002Ch
2Ch UART_TXFLH Transmit frame length register high 0283 002Ch 0284 002Ch 0285 002Ch
30h UART_SFREGL Status FIFO register low 0283 0030h 0284 0030h 0285 0030h
30h UART_RXFLL Received frame length register low 0283 0030h 0284 0030h 0285 0030h
34h UART_SFREGH Status FIFO register high 0283 0034h 0284 0034h 0285 0034h
34h UART_RXFLH Received frame length register high 0283 0034h 0284 0034h 0285 0034h
38h UART_BLR BOF control register 0283 0038h 0284 0038h 0285 0038h
38h UART_UASR UART autobauding status register 0283 0038h 0284 0038h 0285 0038h
3Ch UART_ACREG Auxiliary control register 0283 003Ch 0284 003Ch 0285 003Ch
40h UART_SCR Supplementary control register 0283 0040h 0284 0040h 0285 0040h
44h UART_SSR Supplementary status register 0283 0044h 0284 0044h 0285 0044h
48h UART_EBLR BOF length register 0283 0048h 0284 0048h 0285 0048h
50h UART_MVR Module version register 0283 0050h 0284 0050h 0285 0050h
54h UART_SYSC System configuration register 0283 0054h 0284 0054h 0285 0054h
58h UART_SYSS System status register 0283 0058h 0284 0058h 0285 0058h
5Ch UART_WER Wake-up enable register 0283 005Ch 0284 005Ch 0285 005Ch
60h UART_CFPS Carrier frequency prescaler register 0283 0060h 0284 0060h 0285 0060h
64h UART_RXFIFO_LVL RX FIFO level register 0283 0064h 0284 0064h 0285 0064h
68h UART_TXFIFO_LVL TX FIFO level register 0283 0068h 0284 0068h 0285 0068h
6Ch UART_IER2 Interrupt enable register 2 0283 006Ch 0284 006Ch 0285 006Ch
70h UART_ISR2 Interrupt status register 2 0283 0070h 0284 0070h 0285 0070h
74h UART_FREQ_SEL Sample per bit selector register 0283 0074h 0284 0074h 0285 0074h
78h UART_ABAUD_1ST_CHAR 0283 0078h 0284 0078h 0285 0078h
7Ch UART_BAUD_2ND_CHAR 0283 007Ch 0284 007Ch 0285 007Ch
80h UART_MDR3 Mode definition register 3 0283 0080h 0284 0080h 0285 0080h
84h UART_TX_DMA_THRESHOLD TX DMA threshold level register 0283 0084h 0284 0084h 0285 0084h
88h UART_MDR4 Mode definition register 4 0283 0088h 0284 0088h 0285 0088h
8Ch UART_EFR2 Enhanced features register 2 0283 008Ch 0284 008Ch 0285 008Ch
90h UART_ECR Enhanced control register 0283 0090h 0284 0090h 0285 0090h
94h UART_TIMEGUARD Timeguard register 0283 0094h 0284 0094h 0285 0094h
98h UART_TIMEOUTL Timeout lower byte register 0283 0098h 0284 0098h 0285 0098h
9Ch UART_TIMEOUTH Timeout higher byte register 0283 009Ch 0284 009Ch 0285 009Ch
A0h UART_SCCR Smartcard mode control register 0283 00A0h 0284 00A0h 0285 00A0h
A4h UART_ERHR Extended receive holding register 0283 00A4h 0284 00A4h 0285 00A4h
A4h UART_ETHR Extended transmit holding register 0283 00A4h 0284 00A4h 0285 00A4h
A8h UART_MAR Multidrop address register 0283 00A8h 0284 00A8h 0285 00A8h
ACh UART_MMR Multidrop mask register 0283 00ACh 0284 00ACh 0285 00ACh
B0h UART_MBR Multidrop broadcast address register 0283 00B0h 0284 00B0h 0285 00B0h
Table 12-788 UART Registers
Offset Acronym Register Name UART6 Physical Address UART7 Physical Address
0h UART_THR Transmit holding register 0286 0000h 0287 0000h
0h UART_RHR Receiver holding register 0286 0000h 0287 0000h
0h UART_DLL Baud clock divisor LSB value register 0286 0000h 0287 0000h
4h UART_IER_UART UART mode interrupt enable register 0286 0004h 0287 0004h
4h UART_IER_IRDA IrDA mode interrupt enable register 0286 0004h 0287 0004h
4h UART_IER_CIR CIR mode interrupt enable register 0286 0004h 0287 0004h
4h UART_DLH Baud clock divisor MSB value register 0286 0004h 0287 0004h
8h UART_IIR_UART UART mode interrupt identification register 0286 0008h 0287 0008h
8h UART_IIR_IRDA IrDA mode interrupt identification register 0286 0008h 0287 0008h
8h UART_IIR_CIR CIR mode interrupt identification register 0286 0008h 0287 0008h
8h UART_FCR FIFO control register 0286 0008h 0287 0008h
8h UART_EFR Enhanced feature register 0286 0008h 0287 0008h
Ch UART_LCR Line control register 0286 000Ch 0287 000Ch
10h UART_MCR Modem control register 0286 0010h 0287 0010h
10h UART_XON1_ADDR1 UART mode XON1 character, IrDA mode ADDR1 address register 0286 0010h 0287 0010h
14h UART_LSR_UART UART mode line status register 0286 0014h 0287 0014h
14h UART_LSR_IRDA IrDA mode line status register 0286 0014h 0287 0014h
14h UART_LSR_CIR CIR mode line status register 0286 0014h 0287 0014h
14h UART_XON2_ADDR2 UART mode XON2 character, IrDA mode ADDR2 address register 0286 0014h 0287 0014h
18h UART_MSR Modem status register 0286 0018h 0287 0018h
18h UART_XOFF1 UART mode XOFF1 character 0286 0018h 0287 0018h
18h UART_TCR Transmission control register 0286 0018h 0287 0018h
1Ch UART_SPR Scratchpad register 0286 001Ch 0287 001Ch
1Ch UART_XOFF2 UART mode XOFF2 character 0286 001Ch 0287 001Ch
1Ch UART_TLR Trigger level register 0286 001Ch 0287 001Ch
20h UART_MDR1 Mode definition register 1 0286 0020h 0287 0020h
24h UART_MDR2 Mode definition register 2 0286 0024h 0287 0024h
28h UART_SFLSR Status FIFO line status register 0286 0028h 0287 0028h
28h UART_TXFLL Transmit frame length register low 0286 0028h 0287 0028h
2Ch UART_RESUME Resume halted operation register 0286 002Ch 0287 002Ch
2Ch UART_TXFLH Transmit frame length register high 0286 002Ch 0287 002Ch
30h UART_SFREGL Status FIFO register low 0286 0030h 0287 0030h
30h UART_RXFLL Received frame length register low 0286 0030h 0287 0030h
34h UART_SFREGH Status FIFO register high 0286 0034h 0287 0034h
34h UART_RXFLH Received frame length register high 0286 0034h 0287 0034h
38h UART_BLR BOF control register 0286 0038h 0287 0038h
38h UART_UASR UART autobauding status register 0286 0038h 0287 0038h
3Ch UART_ACREG Auxiliary control register 0286 003Ch 0287 003Ch
40h UART_SCR Supplementary control register 0286 0040h 0287 0040h
44h UART_SSR Supplementary status register 0286 0044h 0287 0044h
48h UART_EBLR BOF length register 0286 0048h 0287 0048h
50h UART_MVR Module version register 0286 0050h 0287 0050h
54h UART_SYSC System configuration register 0286 0054h 0287 0054h
58h UART_SYSS System status register 0286 0058h 0287 0058h
5Ch UART_WER Wake-up enable register 0286 005Ch 0287 005Ch
60h UART_CFPS Carrier frequency prescaler register 0286 0060h 0287 0060h
64h UART_RXFIFO_LVL RX FIFO level register 0286 0064h 0287 0064h
68h UART_TXFIFO_LVL TX FIFO level register 0286 0068h 0287 0068h
6Ch UART_IER2 Interrupt enable register 2 0286 006Ch 0287 006Ch
70h UART_ISR2 Interrupt status register 2 0286 0070h 0287 0070h
74h UART_FREQ_SEL Sample per bit selector register 0286 0074h 0287 0074h
78h UART_ABAUD_1ST_CHAR 0286 0078h 0287 0078h
7Ch UART_BAUD_2ND_CHAR 0286 007Ch 0287 007Ch
80h UART_MDR3 Mode definition register 3 0286 0080h 0287 0080h
84h UART_TX_DMA_THRESHOLD TX DMA threshold level register 0286 0084h 0287 0084h
88h UART_MDR4 Mode definition register 4 0286 0088h 0287 0088h
8Ch UART_EFR2 Enhanced features register 2 0286 008Ch 0287 008Ch
90h UART_ECR Enhanced control register 0286 0090h 0287 0090h
94h UART_TIMEGUARD Timeguard register 0286 0094h 0287 0094h
98h UART_TIMEOUTL Timeout lower byte register 0286 0098h 0287 0098h
9Ch UART_TIMEOUTH Timeout higher byte register 0286 009Ch 0287 009Ch
A0h UART_SCCR Smartcard mode control register 0286 00A0h 0287 00A0h
A4h UART_ERHR Extended receive holding register 0286 00A4h 0287 00A4h
A4h UART_ETHR Extended transmit holding register 0286 00A4h 0287 00A4h
A8h UART_MAR Multidrop address register 0286 00A8h 0287 00A8h
ACh UART_MMR Multidrop mask register 0286 00ACh 0287 00ACh
B0h UART_MBR Multidrop broadcast address register 0286 00B0h 0287 00B0h
Table 12-789 UART Registers
Offset Acronym Register Name UART8 Physical Address UART9 Physical Address
0h UART_THR Transmit holding register 0288 0000h 0289 0000h
0h UART_RHR Receiver holding register 0288 0000h 0289 0000h
0h UART_DLL Baud clock divisor LSB value register 0288 0000h 0289 0000h
4h UART_IER_UART UART mode interrupt enable register 0288 0004h 0289 0004h
4h UART_IER_IRDA IrDA mode interrupt enable register 0288 0004h 0289 0004h
4h UART_IER_CIR CIR mode interrupt enable register 0288 0004h 0289 0004h
4h UART_DLH Baud clock divisor MSB value register 0288 0004h 0289 0004h
8h UART_IIR_UART UART mode interrupt identification register 0288 0008h 0289 0008h
8h UART_IIR_IRDA IrDA mode interrupt identification register 0288 0008h 0289 0008h
8h UART_IIR_CIR CIR mode interrupt identification register 0288 0008h 0289 0008h
8h UART_FCR FIFO control register 0288 0008h 0289 0008h
8h UART_EFR Enhanced feature register 0288 0008h 0289 0008h
Ch UART_LCR Line control register 0288 000Ch 0289 000Ch
10h UART_MCR Modem control register 0288 0010h 0289 0010h
10h UART_XON1_ADDR1 UART mode XON1 character, IrDA mode ADDR1 address register 0288 0010h 0289 0010h
14h UART_LSR_UART UART mode line status register 0288 0014h 0289 0014h
14h UART_LSR_IRDA IrDA mode line status register 0288 0014h 0289 0014h
14h UART_LSR_CIR CIR mode line status register 0288 0014h 0289 0014h
14h UART_XON2_ADDR2 UART mode XON2 character, IrDA mode ADDR2 address register 0288 0014h 0289 0014h
18h UART_MSR Modem status register 0288 0018h 0289 0018h
18h UART_XOFF1 UART mode XOFF1 character 0288 0018h 0289 0018h
18h UART_TCR Transmission control register 0288 0018h 0289 0018h
1Ch UART_SPR Scratchpad register 0288 001Ch 0289 001Ch
1Ch UART_XOFF2 UART mode XOFF2 character 0288 001Ch 0289 001Ch
1Ch UART_TLR Trigger level register 0288 001Ch 0289 001Ch
20h UART_MDR1 Mode definition register 1 0288 0020h 0289 0020h
24h UART_MDR2 Mode definition register 2 0288 0024h 0289 0024h
28h UART_SFLSR Status FIFO line status register 0288 0028h 0289 0028h
28h UART_TXFLL Transmit frame length register low 0288 0028h 0289 0028h
2Ch UART_RESUME Resume halted operation register 0288 002Ch 0289 002Ch
2Ch UART_TXFLH Transmit frame length register high 0288 002Ch 0289 002Ch
30h UART_SFREGL Status FIFO register low 0288 0030h 0289 0030h
30h UART_RXFLL Received frame length register low 0288 0030h 0289 0030h
34h UART_SFREGH Status FIFO register high 0288 0034h 0289 0034h
34h UART_RXFLH Received frame length register high 0288 0034h 0289 0034h
38h UART_BLR BOF control register 0288 0038h 0289 0038h
38h UART_UASR UART autobauding status register 0288 0038h 0289 0038h
3Ch UART_ACREG Auxiliary control register 0288 003Ch 0289 003Ch
40h UART_SCR Supplementary control register 0288 0040h 0289 0040h
44h UART_SSR Supplementary status register 0288 0044h 0289 0044h
48h UART_EBLR BOF length register 0288 0048h 0289 0048h
50h UART_MVR Module version register 0288 0050h 0289 0050h
54h UART_SYSC System configuration register 0288 0054h 0289 0054h
58h UART_SYSS System status register 0288 0058h 0289 0058h
5Ch UART_WER Wake-up enable register 0288 005Ch 0289 005Ch
60h UART_CFPS Carrier frequency prescaler register 0288 0060h 0289 0060h
64h UART_RXFIFO_LVL RX FIFO level register 0288 0064h 0289 0064h
68h UART_TXFIFO_LVL TX FIFO level register 0288 0068h 0289 0068h
6Ch UART_IER2 Interrupt enable register 2 0288 006Ch 0289 006Ch
70h UART_ISR2 Interrupt status register 2 0288 0070h 0289 0070h
74h UART_FREQ_SEL Sample per bit selector register 0288 0074h 0289 0074h
78h UART_ABAUD_1ST_CHAR 0288 0078h 0289 0078h
7Ch UART_BAUD_2ND_CHAR 0288 007Ch 0289 007Ch
80h UART_MDR3 Mode definition register 3 0288 0080h 0289 0080h
84h UART_TX_DMA_THRESHOLD TX DMA threshold level register 0288 0084h 0289 0084h
88h UART_MDR4 Mode definition register 4 0288 0088h 0289 0088h
8Ch UART_EFR2 Enhanced features register 2 0288 008Ch 0289 008Ch
90h UART_ECR Enhanced control register 0288 0090h 0289 0090h
94h UART_TIMEGUARD Timeguard register 0288 0094h 0289 0094h
98h UART_TIMEOUTL Timeout lower byte register 0288 0098h 0289 0098h
9Ch UART_TIMEOUTH Timeout higher byte register 0288 009Ch 0289 009Ch
A0h UART_SCCR Smartcard mode control register 0288 00A0h 0289 00A0h
A4h UART_ERHR Extended receive holding register 0288 00A4h 0289 00A4h
A4h UART_ETHR Extended transmit holding register 0288 00A4h 0289 00A4h
A8h UART_MAR Multidrop address register 0288 00A8h 0289 00A8h
ACh UART_MMR Multidrop mask register 0288 00ACh 0289 00ACh
B0h UART_MBR Multidrop broadcast address register 0288 00B0h 0289 00B0h
Table 12-790 UART Registers
Offset Acronym Register Name MCU_UART0 Physical Address WKUP_UART0 Physical Address
0h UART_THR Transmit holding register 40A0 0000h 4230 0000h
0h UART_RHR Receiver holding register 40A0 0000h 4230 0000h
0h UART_DLL Baud clock divisor LSB value register 40A0 0000h 4230 0000h
4h UART_IER_UART UART mode interrupt enable register 40A0 0004h 4230 0004h
4h UART_IER_IRDA IrDA mode interrupt enable register 40A0 0004h 4230 0004h
4h UART_IER_CIR CIR mode interrupt enable register 40A0 0004h 4230 0004h
4h UART_DLH Baud clock divisor MSB value register 40A0 0004h 4230 0004h
8h UART_IIR_UART UART mode interrupt identification register 40A0 0008h 4230 0008h
8h UART_IIR_IRDA IrDA mode interrupt identification register 40A0 0008h 4230 0008h
8h UART_IIR_CIR CIR mode interrupt identification register 40A0 0008h 4230 0008h
8h UART_FCR FIFO control register 40A0 0008h 4230 0008h
8h UART_EFR Enhanced feature register 40A0 0008h 4230 0008h
Ch UART_LCR Line control register 40A0 000Ch 4230 000Ch
10h UART_MCR Modem control register 40A0 0010h 4230 0010h
10h UART_XON1_ADDR1 UART mode XON1 character, IrDA mode ADDR1 address register 40A0 0010h 4230 0010h
14h UART_LSR_UART UART mode line status register 40A0 0014h 4230 0014h
14h UART_LSR_IRDA IrDA mode line status register 40A0 0014h 4230 0014h
14h UART_LSR_CIR CIR mode line status register 40A0 0014h 4230 0014h
14h UART_XON2_ADDR2 UART mode XON2 character, IrDA mode ADDR2 address register 40A0 0014h 4230 0014h
18h UART_MSR Modem status register 40A0 0018h 4230 0018h
18h UART_XOFF1 UART mode XOFF1 character 40A0 0018h 4230 0018h
18h UART_TCR Transmission control register 40A0 0018h 4230 0018h
1Ch UART_SPR Scratchpad register 40A0 001Ch 4230 001Ch
1Ch UART_XOFF2 UART mode XOFF2 character 40A0 001Ch 4230 001Ch
1Ch UART_TLR Trigger level register 40A0 001Ch 4230 001Ch
20h UART_MDR1 Mode definition register 1 40A0 0020h 4230 0020h
24h UART_MDR2 Mode definition register 2 40A0 0024h 4230 0024h
28h UART_SFLSR Status FIFO line status register 40A0 0028h 4230 0028h
28h UART_TXFLL Transmit frame length register low 40A0 0028h 4230 0028h
2Ch UART_RESUME Resume halted operation register 40A0 002Ch 4230 002Ch
2Ch UART_TXFLH Transmit frame length register high 40A0 002Ch 4230 002Ch
30h UART_SFREGL Status FIFO register low 40A0 0030h 4230 0030h
30h UART_RXFLL Received frame length register low 40A0 0030h 4230 0030h
34h UART_SFREGH Status FIFO register high 40A0 0034h 4230 0034h
34h UART_RXFLH Received frame length register high 40A0 0034h 4230 0034h
38h UART_BLR BOF control register 40A0 0038h 4230 0038h
38h UART_UASR UART autobauding status register 40A0 0038h 4230 0038h
3Ch UART_ACREG Auxiliary control register 40A0 003Ch 4230 003Ch
40h UART_SCR Supplementary control register 40A0 0040h 4230 0040h
44h UART_SSR Supplementary status register 40A0 0044h 4230 0044h
48h UART_EBLR BOF length register 40A0 0048h 4230 0048h
50h UART_MVR Module version register 40A0 0050h 4230 0050h
54h UART_SYSC System configuration register 40A0 0054h 4230 0054h
58h UART_SYSS System status register 40A0 0058h 4230 0058h
5Ch UART_WER Wake-up enable register 40A0 005Ch 4230 005Ch
60h UART_CFPS Carrier frequency prescaler register 40A0 0060h 4230 0060h
64h UART_RXFIFO_LVL RX FIFO level register 40A0 0064h 4230 0064h
68h UART_TXFIFO_LVL TX FIFO level register 40A0 0068h 4230 0068h
6Ch UART_IER2 Interrupt enable register 2 40A0 006Ch 4230 006Ch
70h UART_ISR2 Interrupt status register 2 40A0 0070h 4230 0070h
74h UART_FREQ_SEL Sample per bit selector register 40A0 0074h 4230 0074h
78h UART_ABAUD_1ST_CHAR 40A0 0078h 4230 0078h
7Ch UART_BAUD_2ND_CHAR 40A0 007Ch 4230 007Ch
80h UART_MDR3 Mode definition register 3 40A0 0080h 4230 0080h
84h UART_TX_DMA_THRESHOLD TX DMA threshold level register 40A0 0084h 4230 0084h
88h UART_MDR4 Mode definition register 4 40A0 0088h 4230 0088h
8Ch UART_EFR2 Enhanced features register 2 40A0 008Ch 4230 008Ch
90h UART_ECR Enhanced control register 40A0 0090h 4230 0090h
94h UART_TIMEGUARD Timeguard register 40A0 0094h 4230 0094h
98h UART_TIMEOUTL Timeout lower byte register 40A0 0098h 4230 0098h
9Ch UART_TIMEOUTH Timeout higher byte register 40A0 009Ch 4230 009Ch
A0h UART_SCCR Smartcard mode control register 40A0 00A0h 4230 00A0h
A4h UART_ERHR Extended receive holding register 40A0 00A4h 4230 00A4h
A4h UART_ETHR Extended transmit holding register 40A0 00A4h 4230 00A4h
A8h UART_MAR Multidrop address register 40A0 00A8h 4230 00A8h
ACh UART_MMR Multidrop mask register 40A0 00ACh 4230 00ACh
B0h UART_MBR Multidrop broadcast address register 40A0 00B0h 4230 00B0h

1.6.6.1 UART_THR Register (Offset = 0h) [reset = 0h]

UART_THR is shown in Figure 12-422 and described in Table 12-792.

Return to Summary Table.

The transmitter section consists of the transmit holding register (UART_THR) and the transmit shift register. The UART_THR is a 64-byte FIFO. The local host (LH) writes data to the UART_THR. The data is placed in the transmit shift register where it is shifted out serially on the TX output. If the FIFO is disabled, location 0 of the FIFO stores the data.

Table 12-791 UART_THR Instances
Instance Physical Address
UART0 0280 0000h
UART1 0281 0000h
UART2 0282 0000h
UART3 0283 0000h
UART4 0284 0000h
UART5 0285 0000h
UART6 0286 0000h
UART7 0287 0000h
UART8 0288 0000h
UART9 0289 0000h
MCU_UART0 40A0 0000h
WKUP_UART0 4230 0000h
Figure 12-422 UART_THR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED THR
R-0h W-0h
LEGEND: R = Read Only; W = Write Only; -n = value after reset
Table 12-792 UART_THR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 THR W 0h

Transmit holding register

1.6.6.2 UART_RHR Register (Offset = 0h) [reset = 0h]

UART_RHR is shown in Figure 12-423 and described in Table 12-794.

Return to Summary Table.

The receiver section consists of the receiver holding register (UART_RHR) and the receiver shift register. The UART_RHR is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the UART_RHR. If the FIFO is disabled, location 0 of the FIFO stores the single data character. Note: If an overflow occurs, the data in the UART_RHR is not overwritten.

Table 12-793 UART_RHR Instances
Instance Physical Address
UART0 0280 0000h
UART1 0281 0000h
UART2 0282 0000h
UART3 0283 0000h
UART4 0284 0000h
UART5 0285 0000h
UART6 0286 0000h
UART7 0287 0000h
UART8 0288 0000h
UART9 0289 0000h
MCU_UART0 40A0 0000h
WKUP_UART0 4230 0000h
Figure 12-423 UART_RHR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RHR
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-794 UART_RHR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 RHR R 0h

Receive holding register

1.6.6.3 UART_DLL Register (Offset = 0h) [reset = 0h]

UART_DLL is shown in Figure 12-424 and described in Table 12-796.

Return to Summary Table.

This register, with UART_DLH, stores the 14-bit divisor for generation of the baud clock in the baud rate generator. UART_DLH stores the most-significant part of the divisor. UART_DLL stores the least-significant part of the divisor.

Table 12-795 UART_DLL Instances
Instance Physical Address
UART0 0280 0000h
UART1 0281 0000h
UART2 0282 0000h
UART3 0283 0000h
UART4 0284 0000h
UART5 0285 0000h
UART6 0286 0000h
UART7 0287 0000h
UART8 0288 0000h
UART9 0289 0000h
MCU_UART0 40A0 0000h
WKUP_UART0 4230 0000h
Figure 12-424 UART_DLL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CLOCK_LSB
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-796 UART_DLL Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 CLOCK_LSB R/W 0h

Stores the 8-bit LSB divisor value

1.6.6.4 UART_IER_UART Register (Offset = 4h) [reset = 0h]

UART_IER_UART is shown in Figure 12-425 and described in Table 12-798.

Return to Summary Table.

Interrupt enable register

The interrupt enable register (UART_IER_UART) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error, UART_RHR interrupt, UART_THR interrupt, XOFF received and CTS*/RTS* change of state from low to high. Each interrupt can be enabled/disabled individually. There is also a sleep mode enable bit.

Table 12-797 UART_IER_UART Instances
Instance Physical Address
UART0 0280 0004h
UART1 0281 0004h
UART2 0282 0004h
UART3 0283 0004h
UART4 0284 0004h
UART5 0285 0004h
UART6 0286 0004h
UART7 0287 0004h
UART8 0288 0004h
UART9 0289 0004h
MCU_UART0 40A0 0004h
WKUP_UART0 4230 0004h
Figure 12-425 UART_IER_UART Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
CTS_IT RTS_IT XOFF_IT SLEEP_MODE MODEM_STS_IT LINE_STS_IT THR_IT RHR_IT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-798 UART_IER_UART Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 CTS_IT R/W 0h


0h = Disables the CTS* interrupt
1h = Enables the CTS* interrupt
6 RTS_IT R/W 0h


0h = Disables the RTS* interrupt
1h = Enables the RTS* interrupt
5 XOFF_IT R/W 0h


0h = Disables the XOFF interrupt
1h = Enables the XOFF interrupt
4 SLEEP_MODE R/W 0h


0h = Disables sleep mode
1h = Enables sleep mode (stop baud rate clock when the module is inactive)
3 MODEM_STS_IT R/W 0h


0h = Disables the modem status register interrupt
1h = Enables the modem status register interrupt
2 LINE_STS_IT R/W 0h


0h = Disables the receiver line status interrupt
1h = Enables the receiver line status interrupt
1 THR_IT R/W 0h


0h = Disables the THR interrupt
1h = Enables the THR interrupt
0 RHR_IT R/W 0h


0h = Disables the RHR interrupt and time-out interrupt
1h = Enables the RHR interrupt and time-out interrupt

1.6.6.5 UART_IER_IRDA Register (Offset = 4h) [reset = 0h]

UART_IER_IRDA is shown in Figure 12-426 and described in Table 12-800.

Return to Summary Table.

There are 8 types of interrupt in these modes, received EOF, LSR interrupt, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The TX_STATUS_IT interrupt reflects two possible conditions. The UART_MDR2[0] should be read to determine the status in the event of this interrupt.

Table 12-799 UART_IER_IRDA Instances
Instance Physical Address
UART0 0280 0004h
UART1 0281 0004h
UART2 0282 0004h
UART3 0283 0004h
UART4 0284 0004h
UART5 0285 0004h
UART6 0286 0004h
UART7 0287 0004h
UART8 0288 0004h
UART9 0289 0004h
MCU_UART0 40A0 0004h
WKUP_UART0 4230 0004h
Figure 12-426 UART_IER_IRDA Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
EOF_IT LINE_STS_IT TX_STATUS_IT STS_FIFO_TRIG_IT RX_OVERRUN_IT LAST_RX_BYTE_IT THR_IT RHR_IT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-800 UART_IER_IRDA Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 EOF_IT R/W 0h


0h = Disables the received EOF interrupt
1h = Enables the received EOF interrupt
6 LINE_STS_IT R/W 0h


0h = Disables the receiver line status interrupt
1h = Enables the receiver line status interrupt
5 TX_STATUS_IT R/W 0h


0h = Disables the TX status interrupt
1h = Enables the TX status interrupt
4 STS_FIFO_TRIG_IT R/W 0h


0h = Disables status FIFO trigger level interrupt
1h = Enables status FIFO trigger level interrupt
3 RX_OVERRUN_IT R/W 0h


0h = Disables the RX overrun interrupt
1h = Enables the RX overrun interrupt
2 LAST_RX_BYTE_IT R/W 0h


0h = Disables the last byte of frame in RX FIFO interrupt
1h = Enables the last byte of frame in RX FIFO interrupt
1 THR_IT R/W 0h


0h = Disables the THR interrupt
1h = Enables the THR interrupt
0 RHR_IT R/W 0h


0h = Disables the RHR interrupt and time-out interrupt
1h = Enables the RHR interrupt and time-out interrupt

1.6.6.6 UART_IER_CIR Register (Offset = 4h) [reset = X]

UART_IER_CIR is shown in Figure 12-427 and described in Table 12-802.

Return to Summary Table.

There are 6 types of interrupt in these modes, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated based on the value set in the BOF Length register (UART_EBLR). In IR-CIR mode, contrary to the IR-IRDA mode, the TX_STATUS_IT has only one meaning corresponding to the case UART_MDR2[0] = 0.

Table 12-801 UART_IER_CIR Instances
Instance Physical Address
UART0 0280 0004h
UART1 0281 0004h
UART2 0282 0004h
UART3 0283 0004h
UART4 0284 0004h
UART5 0285 0004h
UART6 0286 0004h
UART7 0287 0004h
UART8 0288 0004h
UART9 0289 0004h
MCU_UART0 40A0 0004h
WKUP_UART0 4230 0004h
Figure 12-427 UART_IER_CIR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
NOT_USED TX_STATUS_IT RESERVED RX_OVERRUN_IT RX_STOP_IT THR_IT RHR_IT
R/W-0h R/W-0h R/W-X R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-802 UART_IER_CIR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-6 NOT_USED R/W 0h
5 TX_STATUS_IT R/W 0h


0h = Disables the TX status interrupt
1h = Enables the TX status interrupt
4 RESERVED R/W X
3 RX_OVERRUN_IT R/W 0h


0h = Disables the RX overrun interrupt
1h = Enables the RX overrun interrupt
2 RX_STOP_IT R/W 0h


0h = Disables the receive stop interrupt
1h = Enables the receive stop interrupt
1 THR_IT R/W 0h


0h = Disables the THR interrupt
1h = Enables the THR interrupt
0 RHR_IT R/W 0h


0h = Disables the RHR interrupt
1h = Enables the RHR interrupt

1.6.6.7 UART_DLH Register (Offset = 4h) [reset = 0h]

UART_DLH is shown in Figure 12-428 and described in Table 12-804.

Return to Summary Table.

This register, with UART_DLL, stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor.

Table 12-803 UART_DLH Instances
Instance Physical Address
UART0 0280 0004h
UART1 0281 0004h
UART2 0282 0004h
UART3 0283 0004h
UART4 0284 0004h
UART5 0285 0004h
UART6 0286 0004h
UART7 0287 0004h
UART8 0288 0004h
UART9 0289 0004h
MCU_UART0 40A0 0004h
WKUP_UART0 4230 0004h
Figure 12-428 UART_DLH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CLOCK_MSB
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-804 UART_DLH Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h

Reserved
5-0 CLOCK_MSB R/W 0h

Stores the 6-bit MSB divisor value

1.6.6.8 UART_IIR_UART Register (Offset = 8h) [reset = 1h]

UART_IIR_UART is shown in Figure 12-429 and described in Table 12-806.

Return to Summary Table.

Interrupt identification register.
The UART_IIR_UART is a read-only register that provides the source of the interrupt in a prioritized manner.

Table 12-805 UART_IIR_UART Instances
Instance Physical Address
UART0 0280 0008h
UART1 0281 0008h
UART2 0282 0008h
UART3 0283 0008h
UART4 0284 0008h
UART5 0285 0008h
UART6 0286 0008h
UART7 0287 0008h
UART8 0288 0008h
UART9 0289 0008h
MCU_UART0 40A0 0008h
WKUP_UART0 4230 0008h
Figure 12-429 UART_IIR_UART Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
FCR_MIRROR IT_TYPE IT_PENDING
R-0h R-0h R-1h
LEGEND: R = Read Only; -n = value after reset
Table 12-806 UART_IIR_UART Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-6 FCR_MIRROR R 0h

Mirror the contents of UART_FCR[0] on both bits.
5-1 IT_TYPE R 0h

Read 0h = Modem interrupt. Priority = 4
Read 1h = THR interrupt. Priority = 3
Read 2h = RHR interrupt. Priority = 2
Read 3h = Receiver line status error. Priority = 3
Read 6h = Rx time-out. Priority = 2
Read 8h = XOFF/special character. Priority = 5
Read 10h = CTS, RTS, DSR change state from active (low) to inactive (high) Priority = 6
0 IT_PENDING R 1h

Read 0h = An interrupt is pending.
Read 1h = No interrupt is pending.

1.6.6.9 UART_IIR_IRDA Register (Offset = 8h) [reset = 0h]

UART_IIR_IRDA is shown in Figure 12-430 and described in Table 12-808.

Return to Summary Table.

The interrupt line is activated whenever one of the 8 interrupts is active.

Table 12-807 UART_IIR_IRDA Instances
Instance Physical Address
UART0 0280 0008h
UART1 0281 0008h
UART2 0282 0008h
UART3 0283 0008h
UART4 0284 0008h
UART5 0285 0008h
UART6 0286 0008h
UART7 0287 0008h
UART8 0288 0008h
UART9 0289 0008h
MCU_UART0 40A0 0008h
WKUP_UART0 4230 0008h
Figure 12-430 UART_IIR_IRDA Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
EOF_IT LINE_STS_IT TX_STATUS_IT STS_FIFO_IT RX_OE_IT RX_FIFO_LAST_BYTE_IT THR_IT RHR_IT
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-808 UART_IIR_IRDA Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 EOF_IT R 0h


Read 0h = Receive EOF interrupt inactive
Read 1h = Received EOF interrupt active
6 LINE_STS_IT R 0h


Read 0h = Receiver line status interrupt inactive
Read 1h = Receiver line status interrupt active
5 TX_STATUS_IT R 0h


Read 0h = TX status interrupt inactive
Read 1h = TX status interrupt active
4 STS_FIFO_IT R 0h


Read 0h = Status FIFO trigger level interrupt inactive
Read 1h = Status FIFO trigger level interrupt active
3 RX_OE_IT R 0h


Read 0h = RX overrun interrupt inactive
Read 1h = RX overrun interrupt active
2 RX_FIFO_LAST_BYTE_IT R 0h


Read 0h = Last byte of frame in RX FIFO interrupt inactive
Read 1h = Last byte of frame in RX FIFO interrupt active
1 THR_IT R 0h


Read 0h = THR interrupt inactive
Read 1h = THR interrupt active
0 RHR_IT R 0h


Read 0h = RHR interrupt inactive
Read 1h = RHR interrupt active

1.6.6.10 UART_IIR_CIR Register (Offset = 8h) [reset = X]

UART_IIR_CIR is shown in Figure 12-431 and described in Table 12-810.

Return to Summary Table.

The interrupt line is activated whenever one of the 6 interrupts is active.

Table 12-809 UART_IIR_CIR Instances
Instance Physical Address
UART0 0280 0008h
UART1 0281 0008h
UART2 0282 0008h
UART3 0283 0008h
UART4 0284 0008h
UART5 0285 0008h
UART6 0286 0008h
UART7 0287 0008h
UART8 0288 0008h
UART9 0289 0008h
MCU_UART0 40A0 0008h
WKUP_UART0 4230 0008h
Figure 12-431 UART_IIR_CIR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED TX_STATUS_IT RESERVED RX_OE_IT RX_STOP_IT THR_IT RHR_IT
R-X R-0h R-X R-0h R-0h R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-810 UART_IIR_CIR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-6 RESERVED R X
5 TX_STATUS_IT R 0h

Read 0h = TX status interrupt inactive
Read 1h = TX status interrupt active
4 RESERVED R X
3 RX_OE_IT R 0h

Read 0h = RX overrun interrupt inactive
Read 1h = RX overrun interrupt active
2 RX_STOP_IT R 0h

Read 0h = Receive stop interrupt inactive
Read 1h = Receive stop interrupt active
1 THR_IT R 0h

Read 0h = THR interrupt inactive
Read 1h = THR interrupt active
0 RHR_IT R 0h

Read 0h = RHR interrupt inactive
Read 1h = RHR interrupt active

1.6.6.11 UART_FCR Register (Offset = 8h) [reset = 0h]

UART_FCR is shown in Figure 12-432 and described in Table 12-812.

Return to Summary Table.

FIFO control register
Notes: Bits 4 and 5 can only be written to when UART_EFR[4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See Table 12-745 for UART_FCR[5:4] setting restriction when UART_SCR[6] = 1. See Table 12-746 for UART_FCR[7:6] setting restriction when UART_SCR[7] = 1.

Table 12-811 UART_FCR Instances
Instance Physical Address
UART0 0280 0008h
UART1 0281 0008h
UART2 0282 0008h
UART3 0283 0008h
UART4 0284 0008h
UART5 0285 0008h
UART6 0286 0008h
UART7 0287 0008h
UART8 0288 0008h
UART9 0289 0008h
MCU_UART0 40A0 0008h
WKUP_UART0 4230 0008h
Figure 12-432 UART_FCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RX_FIFO_TRIG TX_FIFO_TRIG DMA_MODE TX_FIFO_CLEAR RX_FIFO_CLEAR FIFO_EN
W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R = Read Only; W = Write Only; -n = value after reset
Table 12-812 UART_FCR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-6 RX_FIFO_TRIG W 0h

Sets the trigger level for the RX FIFO: If UART_SCR[7] = 0 and UART_TLR[7:4] = 0000:
0h = 8 characters
1h = 16 characters
2h = 56 characters
3h = 60 characters
If UART_SCR[7] = 0 and UART_TLR[7:4] != 0000, RX_FIFO_TRIG is not considered. If UART_SCR[7] = 1, RX_FIFO_TRIG is 2 LSBs of the trigger level (1-63 on 6 bits) with the granularity 1.
5-4 TX_FIFO_TRIG W 0h

Sets the trigger level for the TX FIFO: If UART_SCR[6] = 0 and UART_TLR[3:0] = 0000:
0h = 8 spaces
1h = 16 spaces
2h = 32 spaces
3h = 56 spaces
If UART_SCR[6] = 0 and UART_TLR[3:0] != 0000, TX_FIFO_TRIG is not considered. If UART_SCR[6] = 1, TX_FIFO_TRIG is 2 LSBs of the trigger level (1-63 on 6 bits) with the granularity 1
3 DMA_MODE W 0h

This register is considered if UART_SCR[0] = 0.
Write 0h = DMA_MODE 0 (No DMA)
Write 1h = DMA_MODE 1 (UART_nDMA_REQ[0] in TX (UARTi_DREQ_TX), UART_nDMA_REQ[1] in RX (UARTi_DREQ_RX))
2 TX_FIFO_CLEAR W 0h


Write 0h = No change
Write 1h = Clears the TX FIFO and resets its counter logic to 0. Returns to 0 after clearing FIFO.
1 RX_FIFO_CLEAR W 0h


Write 0h = No change
Write 1h = Clears the RX FIFO and resets its counter logic to 0. Returns to 0 after clearing FIFO.
0 FIFO_EN W 0h


Write 0h = Disables the transmit and RX FIFOs. The transmit and receive holding registers are 1-byte FIFOs.
Write 1h = Enables the transmit and RX FIFOs. The transmit and receive holding registers are 64-byte FIFOs.

1.6.6.12 UART_EFR Register (Offset = 8h) [reset = 0h]

UART_EFR is shown in Figure 12-433 and described in Table 12-814.

Return to Summary Table.

Enhanced feature register
This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes, but UART_EFR[4] enables write accesses to UART_FCR[5:4], the TX trigger level, which is also used in IrDA modes.

Table 12-813 UART_EFR Instances
Instance Physical Address
UART0 0280 0008h
UART1 0281 0008h
UART2 0282 0008h
UART3 0283 0008h
UART4 0284 0008h
UART5 0285 0008h
UART6 0286 0008h
UART7 0287 0008h
UART8 0288 0008h
UART9 0289 0008h
MCU_UART0 40A0 0008h
WKUP_UART0 4230 0008h
Figure 12-433 UART_EFR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
AUTO_CTS_EN AUTO_RTS_EN SPECIAL_CHAR_DETECT ENHANCED_EN SW_FLOW_CONTROL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-814 UART_EFR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 AUTO_CTS_EN R/W 0h

Auto-CTS enable bit
0h = Normal operation
1h = Auto-CTS flow control is enabled. Transmission is halted when the CTS* pin is high (inactive).
6 AUTO_RTS_EN R/W 0h

Auto-RTS enable bit
0h = Normal operation
1h = Auto-RTS flow control is enabled. RTS* pin goes high (inactive) when the RX FIFO HALT trigger level, UART_TCR[3:0], is reached, and goes low (active) when the RX FIFO RESTORE transmission trigger level is reached.
5 SPECIAL_CHAR_DETECT R/W 0h


0h = Normal operation
1h = Special character detect enable. Received data is compared with XOFF2 data. If a match occurs, the received data is transferred to the RX FIFO and the UART_IIR[4] bit is set to 1 to indicate that a special character was detected.
4 ENHANCED_EN R/W 0h

Enhanced functions write enable bit
0h = Disables writing to IER bits 4-7, UART_FCR bits 4-5, and UART_MCR bits 5-7.
1h = Enables writing to IER bits 4-7, UART_FCR bits 4-5, and UART_MCR bits 5-7.
3-0 SW_FLOW_CONTROL R/W 0h

Combinations of software flow control can be selected by programming bit 3 - bit 0. See UART_EFR[3:0] Software Flow Control Options.

1.6.6.13 UART_LCR Register (Offset = Ch) [reset = 0h]

UART_LCR is shown in Figure 12-434 and described in Table 12-816.

Return to Summary Table.

Line control register UART_LCR[6:0] define transmission and reception parameters. Note: When UART_LCR[6] is set to 1, the TX line is forced to 0 and remains in this state as long as UART_LCR[6] = 1.

Table 12-815 UART_LCR Instances
Instance Physical Address
UART0 0280 000Ch
UART1 0281 000Ch
UART2 0282 000Ch
UART3 0283 000Ch
UART4 0284 000Ch
UART5 0285 000Ch
UART6 0286 000Ch
UART7 0287 000Ch
UART8 0288 000Ch
UART9 0289 000Ch
MCU_UART0 40A0 000Ch
WKUP_UART0 4230 000Ch
Figure 12-434 UART_LCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
DIV_EN BREAK_EN PARITY_TYPE2 PARITY_TYPE1 PARITY_EN NB_STOP CHAR_LENGTH
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-816 UART_LCR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 DIV_EN R/W 0h


0h = Normal operating condition
1h = Divisor latch enable. Allows access to UART_DLL, UART_DLH, and other registers (see UART Register Access Mode Programming (Using UART_LCR).
6 BREAK_EN R/W 0h

Break control bit
0h = Normal operating condition
1h = Forces the transmitter output to go low to alert the communication terminal
5 PARITY_TYPE2 R/W 0h

Selects the forced parity format (if UART_LCR[3] = 1). If UART_LCR[5] = 1 and UART_LCR[4] = 0, the parity bit is forced to 1 in the transmitted and received data. If UART_LCR[5] = 1 and UART_LCR[4] = 1, the parity bit is forced to 0 in the transmitted and received data.
4 PARITY_TYPE1 R/W 0h


0h = Odd parity is generated (if UART_LCR[3] = 1).
1h = Even parity is generated (if UART_LCR[3] = 1).
3 PARITY_EN R/W 0h

0h = No parity
1h = A parity bit is generated during transmission and the receiver checks for received parity.
2 NB_STOP R/W 0h

Specifies the number of stop-bits
0h = 1 stop-bit (word length = 5, 6, 7, 8)
1h = 1.5 stop-bits (word length = 5) 2 stop-bits (word length = 6, 7, 8)
1-0 CHAR_LENGTH R/W 0h

Specifies the word length to be transmitted or received
0h = 5 bits
1h = 6 bits
2h = 7 bits
3h = 8 bits

1.6.6.14 UART_MCR Register (Offset = 10h) [reset = 0h]

UART_MCR is shown in Figure 12-435 and described in Table 12-818.

Return to Summary Table.

Modem control register UART_MCR[3:0] controls the interface with the modem, data set, or peripheral device that emulates the modem.

Table 12-817 UART_MCR Instances
Instance Physical Address
UART0 0280 0010h
UART1 0281 0010h
UART2 0282 0010h
UART3 0283 0010h
UART4 0284 0010h
UART5 0285 0010h
UART6 0286 0010h
UART7 0287 0010h
UART8 0288 0010h
UART9 0289 0010h
MCU_UART0 40A0 0010h
WKUP_UART0 4230 0010h
Figure 12-435 UART_MCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED TCR_TLR XON_EN LOOPBACK_EN CD_STS_CH RI_STS_CH RTS DTR
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-818 UART_MCR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 RESERVED R 0h
6 TCR_TLR R/W 0h

0h = No action
1h = Enables access to the UART_TCR and UART_TLR registers
5 XON_EN R/W 0h

0h = Disable XON any function.
1h = Enable XON any function.
4 LOOPBACK_EN R/W 0h

0h = Normal operating mode
1h = Enable local loopback mode (internal). In this mode, the MCR[3:0] signals are looped back into the UART_MSR[7:4] bit field. The transmit output is looped back to the receive input internally.
3 CD_STS_CH R/W 0h

0h = In loopback, forces DCD* input high and IRQ outputs to inactive state
1h = In loopback, forces DCD* input low and IRQ outputs to inactive state
2 RI_STS_CH R/W 0h

0h = In loopback, forces RI* input high
1h = In loopback, forces RI* input low
1 RTS R/W 0h

In loopback, controls the UART_MSR[4] bit. If auto-RTS is enabled, the RTS* output is controlled by hardware flow control.
0h = Force RTS* output to inactive (high).
1h = Force RTS* output to active (low).
0 DTR R/W 0h

0h = Force DTR* output to inactive (high).
1h = Force DTR* output to active (low).

1.6.6.15 UART_XON1_ADDR1 Register (Offset = 10h) [reset = 0h]

UART_XON1_ADDR1 is shown in Figure 12-436 and described in Table 12-820.

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UART mode: XON1 character, IrDA mode: ADDR1 address

Table 12-819 UART_XON1_ADDR1 Instances
Instance Physical Address
UART0 0280 0010h
UART1 0281 0010h
UART2 0282 0010h
UART3 0283 0010h
UART4 0284 0010h
UART5 0285 0010h
UART6 0286 0010h
UART7 0287 0010h
UART8 0288 0010h
UART9 0289 0010h
MCU_UART0 40A0 0010h
WKUP_UART0 4230 0010h
Figure 12-436 UART_XON1_ADDR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED XON_WORD1
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-820 UART_XON1_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 XON_WORD1 R/W 0h

Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes

1.6.6.16 UART_LSR_UART Register (Offset = 14h) [reset = 60h]

UART_LSR_UART is shown in Figure 12-437 and described in Table 12-822.

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Line status register

Table 12-821 UART_LSR_UART Instances
Instance Physical Address
UART0 0280 0014h
UART1 0281 0014h
UART2 0282 0014h
UART3 0283 0014h
UART4 0284 0014h
UART5 0285 0014h
UART6 0286 0014h
UART7 0287 0014h
UART8 0288 0014h
UART9 0289 0014h
MCU_UART0 40A0 0014h
WKUP_UART0 4230 0014h
Figure 12-437 UART_LSR_UART Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RX_FIFO_STS TX_SR_E TX_FIFO_E RX_BI RX_FE RX_PE RX_OE RX_FIFO_E
R-0h R-1h R-1h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-822 UART_LSR_UART Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 RX_FIFO_STS R 0h

Read 0h = Normal operation
Read 1h = At least one parity error, framing error, or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO.
6 TX_SR_E R 1h

Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty.
Read 1h = Transmitter hold (TX FIFO) and shift registers are empty.
5 TX_FIFO_E R 1h

Read 0h = Transmit hold register (TX FIFO) is not empty.
Read 1h = Transmit hold register (TX FIFO) is empty. The transmission is not necessarily complete.
4 RX_BI R 0h

Read 0h = No break condition
Read 1h = A break was detected while the data from the RX FIFO was received (for example, RX input was low for one character + 1 bit time frame).
3 RX_FE R 0h

Read 0h = No framing error in data RX FIFO
Read 1h = Framing error occurred in data from RX FIFO (received data did not have a valid stop-bit).
2 RX_PE R 0h

Read 0h = No parity error in data from RX FIFO
Read 1h = Parity error in data from RX FIFO
1 RX_OE R 0h

Read 0h = No overrun error
Read 1h = Overrun error occurred. Set when the character in the receive shift register is not transferred to the RX FIFO. This occurs only when the RX FIFO is full.
0 RX_FIFO_E R 0h

Read 0h = No data in the RX FIFO
Read 1h = At least one data character in the RX FIFO

1.6.6.17 UART_LSR_IRDA Register (Offset = 14h) [reset = 83h]

UART_LSR_IRDA is shown in Figure 12-438 and described in Table 12-824.

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When the LSR is read, LSR[4:2] reflect the error bits [FL, CRC, ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read).

Table 12-823 UART_LSR_IRDA Instances
Instance Physical Address
UART0 0280 0014h
UART1 0281 0014h
UART2 0282 0014h
UART3 0283 0014h
UART4 0284 0014h
UART5 0285 0014h
UART6 0286 0014h
UART7 0287 0014h
UART8 0288 0014h
UART9 0289 0014h
MCU_UART0 40A0 0014h
WKUP_UART0 4230 0014h
Figure 12-438 UART_LSR_IRDA Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
THR_EMPTY STS_FIFO_FULL RX_LAST_BYTE FRAME_TOO_LONG ABORT CRC STS_FIFO_E RX_FIFO_E
R-1h R-0h R-0h R-0h R-0h R-0h R-1h R-1h
LEGEND: R = Read Only; -n = value after reset
Table 12-824 UART_LSR_IRDA Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 THR_EMPTY R 1h

Read 0h = Transmit holding register (TX FIFO) is not empty.
Read 1h = Transmit hold register (TX FIFO) is empty. The transmission is not necessarily complete.
6 STS_FIFO_FULL R 0h

Read 0h = Status FIFO not full
Read 1h = Status FIFO full
5 RX_LAST_BYTE R 0h

Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read.
Read 1h = The RX FIFO (RHR) contains the last byte of the frame to be read. This bit is set only when the last byte of a frame is available to be read. It determines the frame boundary. It is cleared on a single read of the LSR register.
4 FRAME_TOO_LONG R 0h

Read 0h = No frame-too-long error in frame
Read 1h = Frame-too-long error in the frame at the top of the STATUS FIFO, (next character to be read). This bit is set to 1 when a frame exceeding the maximum length (set by RXFLH and RXFLL registers) is received. When this error is detected, current frame reception is terminated. Reception is stopped until the next START flag is detected.
3 ABORT R 0h

Read 0h = No abort pattern error in frame
Read 1h = Abort pattern is received. SIR and MIR: Abort pattern FIR: Illegal symbol
2 CRC R 0h

Read 0h = No CRC error in frame
Read 1h = CRC error in the frame at the top of the STATUS FIFO (next character to be read)
1 STS_FIFO_E R 1h

Read 0h = Status FIFO not empty
Read 1h = Status FIFO empty
0 RX_FIFO_E R 1h

Read 0h = No data in the RX FIFO
Read 1h = At least one data character in the RX FIFO

1.6.6.18 UART_LSR_CIR Register (Offset = 14h) [reset = X]

UART_LSR_CIR is shown in Figure 12-439 and described in Table 12-826.

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Line status register in CIR mode

Table 12-825 UART_LSR_CIR Instances
Instance Physical Address
UART0 0280 0014h
UART1 0281 0014h
UART2 0282 0014h
UART3 0283 0014h
UART4 0284 0014h
UART5 0285 0014h
UART6 0286 0014h
UART7 0287 0014h
UART8 0288 0014h
UART9 0289 0014h
MCU_UART0 40A0 0014h
WKUP_UART0 4230 0014h
Figure 12-439 UART_LSR_CIR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
THR_EMPTY RESERVED RX_STOP RESERVED RX_FIFO_E
R-1h R-0h R-0h R-X R-1h
LEGEND: R = Read Only; -n = value after reset
Table 12-826 UART_LSR_CIR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 THR_EMPTY R 1h

Read 0h = Transmit holding register (TX FIFO) is not empty.
Read 1h = Transmit hold register (TX FIFO) is empty. The transmission is not necessarily complete.
6 RESERVED R 0h
5 RX_STOP R 0h

The RX_STOP is generated based on the value set in the BOF Length register (UART_EBLR). It is cleared on a single read of the UART_LSR register.
Read 0h = Reception is ongoing or waiting for a new frame.
Read 1h = Reception is complete.
4-1 RESERVED R X
0 RX_FIFO_E R 1h

Read 0h = At least one data character in the RX FIFO
Read 1h = No data in the RX FIFO

1.6.6.19 UART_XON2_ADDR2 Register (Offset = 14h) [reset = 0h]

UART_XON2_ADDR2 is shown in Figure 12-440 and described in Table 12-828.

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Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes

Table 12-827 UART_XON2_ADDR2 Instances
Instance Physical Address
UART0 0280 0014h
UART1 0281 0014h
UART2 0282 0014h
UART3 0283 0014h
UART4 0284 0014h
UART5 0285 0014h
UART6 0286 0014h
UART7 0287 0014h
UART8 0288 0014h
UART9 0289 0014h
MCU_UART0 40A0 0014h
WKUP_UART0 4230 0014h
Figure 12-440 UART_XON2_ADDR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED XON_WORD2
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-828 UART_XON2_ADDR2 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 XON_WORD2 R/W 0h

Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes

1.6.6.20 UART_MSR Register (Offset = 18h) [reset = 0h]

UART_MSR is shown in Figure 12-441 and described in Table 12-830.

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Modem status register. UART mode only.
This register provides information about the current state of the control lines from the modem, data set, or peripheral device to the LH. It also indicates when a control input from the modem changes state.

Table 12-829 UART_MSR Instances
Instance Physical Address
UART0 0280 0018h
UART1 0281 0018h
UART2 0282 0018h
UART3 0283 0018h
UART4 0284 0018h
UART5 0285 0018h
UART6 0286 0018h
UART7 0287 0018h
UART8 0288 0018h
UART9 0289 0018h
MCU_UART0 40A0 0018h
WKUP_UART0 4230 0018h
Figure 12-441 UART_MSR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
NCD_STS NRI_STS NDSR_STS NCTS_STS DCD_STS RI_STS DSR_STS CTS_STS
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-830 UART_MSR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 NCD_STS R 0h

This bit is the complement of the DCD* input. In loopback mode, it is equivalent to UART_MCR[3].
6 NRI_STS R 0h

This bit is the complement of the RI* input. In loopback mode, it is equivalent to UART_MCR[2].
5 NDSR_STS R 0h

This bit is the complement of the DSR* input. In loopback mode, it is equivalent to UART_MCR[0].
4 NCTS_STS R 0h

This bit is the complement of the CTS* input. In loopback mode, it is equivalent to UART_MCR[1].
3 DCD_STS R 0h

Indicates that DCD* input (or UART_MCR[3] in loopback) changed. Cleared on a read.
2 RI_STS R 0h

Indicates that RI* input (or UART_MCR[2] in loopback) changed state from low to high. Cleared on a read.
1 DSR_STS R 0h


Read 1h = Indicates that DSR* input (or UART_MCR[0] in loopback) changed state. Cleared on a read.
0 CTS_STS R 0h


Read 1h = Indicates that CTS* input (or UART_MCR[1] in loopback) changed state. Cleared on a read.

1.6.6.21 UART_XOFF1 Register (Offset = 18h) [reset = 0h]

UART_XOFF1 is shown in Figure 12-442 and described in Table 12-832.

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UART mode XOFF1 character

Table 12-831 UART_XOFF1 Instances
Instance Physical Address
UART0 0280 0018h
UART1 0281 0018h
UART2 0282 0018h
UART3 0283 0018h
UART4 0284 0018h
UART5 0285 0018h
UART6 0286 0018h
UART7 0287 0018h
UART8 0288 0018h
UART9 0289 0018h
MCU_UART0 40A0 0018h
WKUP_UART0 4230 0018h
Figure 12-442 UART_XOFF1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED XOFF_WORD1
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-832 UART_XOFF1 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 XOFF_WORD1 R/W 0h

Stores the 8-bit XOFF1 character used in UART modes

1.6.6.22 UART_TCR Register (Offset = 18h) [reset = Fh]

UART_TCR is shown in Figure 12-443 and described in Table 12-834.

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Transmission control register
This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4 x [4-bit register value]) The programmer must ensure that UART_TCR[3:0] > UART_TCR[7:4] when auto-RTS or software flow control is enabled to avoid a mis-operation of the device. In FIFO interrupt mode with flow control, the programmer must ensure that the trigger level to halt transmission is greater than or equal to the RX FIFO trigger level (UART_TLR[7:4] or UART_FCR[7:6]); otherwise, FIFO operation stalls. In FIFO DMA mode with flow control, this concept does not exist because a DMA request is sent each time a byte is received.

Table 12-833 UART_TCR Instances
Instance Physical Address
UART0 0280 0018h
UART1 0281 0018h
UART2 0282 0018h
UART3 0283 0018h
UART4 0284 0018h
UART5 0285 0018h
UART6 0286 0018h
UART7 0287 0018h
UART8 0288 0018h
UART9 0289 0018h
MCU_UART0 40A0 0018h
WKUP_UART0 4230 0018h
Figure 12-443 UART_TCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RX_FIFO_TRIG_START RX_FIFO_TRIG_HALT
R/W-0h R/W-Fh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-834 UART_TCR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-4 RX_FIFO_TRIG_START R/W 0h

RX FIFO trigger level to RESTORE transmission (0 - 60)
3-0 RX_FIFO_TRIG_HALT R/W Fh

RX FIFO trigger level to HALT transmission (0 - 60)

1.6.6.23 UART_SPR Register (Offset = 1Ch) [reset = 0h]

UART_SPR is shown in Figure 12-444 and described in Table 12-836.

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Scratchpad register
This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data.

Table 12-835 UART_SPR Instances
Instance Physical Address
UART0 0280 001Ch
UART1 0281 001Ch
UART2 0282 001Ch
UART3 0283 001Ch
UART4 0284 001Ch
UART5 0285 001Ch
UART6 0286 001Ch
UART7 0287 001Ch
UART8 0288 001Ch
UART9 0289 001Ch
MCU_UART0 40A0 001Ch
WKUP_UART0 4230 001Ch
Figure 12-444 UART_SPR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SPR_WORD
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-836 UART_SPR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 SPR_WORD R/W 0h

Scratchpad register

1.6.6.24 UART_XOFF2 Register (Offset = 1Ch) [reset = 0h]

UART_XOFF2 is shown in Figure 12-445 and described in Table 12-838.

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UART mode XOFF2 character

Table 12-837 UART_XOFF2 Instances
Instance Physical Address
UART0 0280 001Ch
UART1 0281 001Ch
UART2 0282 001Ch
UART3 0283 001Ch
UART4 0284 001Ch
UART5 0285 001Ch
UART6 0286 001Ch
UART7 0287 001Ch
UART8 0288 001Ch
UART9 0289 001Ch
MCU_UART0 40A0 001Ch
WKUP_UART0 4230 001Ch
Figure 12-445 UART_XOFF2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED XOFF_WORD2
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-838 UART_XOFF2 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 XOFF_WORD2 R/W 0h

Stores the 8-bit XOFF2 character used in UART modes.

1.6.6.25 UART_TLR Register (Offset = 1Ch) [reset = 0h]

UART_TLR is shown in Figure 12-446 and described in Table 12-840.

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Trigger level register
This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation.

Table 12-839 UART_TLR Instances
Instance Physical Address
UART0 0280 001Ch
UART1 0281 001Ch
UART2 0282 001Ch
UART3 0283 001Ch
UART4 0284 001Ch
UART5 0285 001Ch
UART6 0286 001Ch
UART7 0287 001Ch
UART8 0288 001Ch
UART9 0289 001Ch
MCU_UART0 40A0 001Ch
WKUP_UART0 4230 001Ch
Figure 12-446 UART_TLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RX_FIFO_TRIG_DMA TX_FIFO_TRIG_DMA
R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-840 UART_TLR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-4 RX_FIFO_TRIG_DMA R/W 0h

Receive FIFO trigger level
3-0 TX_FIFO_TRIG_DMA R/W 0h

Transmit FIFO trigger level

1.6.6.26 UART_MDR1 Register (Offset = 20h) [reset = 7h]

UART_MDR1 is shown in Figure 12-447 and described in Table 12-842.

Return to Summary Table.

Mode definition register 1
The mode of operation can be programmed by writing to MDR1[2:0] and therefore the UART_MDR1 must be programmed on startup after configuration of the configuration registers (UART_DLL, UART_DLH, and UART_LCR). The value of MDR1[2:0] must not be changed again during normal operation. Note: If the module is disabled by setting the MODE_SELECT field to 111, interrupt requests can still be generated unless disabled through the interrupt enable register (UART_IER). In this case, UART mode interrupts are visible. Reading the interrupt identification register (UART_IIR) shows UART mode interrupt flags.

Table 12-841 UART_MDR1 Instances
Instance Physical Address
UART0 0280 0020h
UART1 0281 0020h
UART2 0282 0020h
UART3 0283 0020h
UART4 0284 0020h
UART5 0285 0020h
UART6 0286 0020h
UART7 0287 0020h
UART8 0288 0020h
UART9 0289 0020h
MCU_UART0 40A0 0020h
WKUP_UART0 4230 0020h
Figure 12-447 UART_MDR1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
FRAME_END_MODE SIP_MODE SCT SET_TXIR IR_SLEEP MODE_SELECT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-842 UART_MDR1 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 FRAME_END_MODE R/W 0h

IrDA mode only
0h = Frame-length method
1h = Set EOT bit method
6 SIP_MODE R/W 0h

MIR/FIR modes only
0h = Manual SIP mode: SIP is generated with the control of UART_ACREG[3].
1h = Automatic SIP mode: SIP is generated after each transmission.
5 SCT R/W 0h

Store and control the transmission.
0h = Starts the infrared transmission when a value is written to UART_THR
1h = Starts the infrared transmission with the control of UART_ACREG[2].
Note: Before starting any transmission, there must be no reception ongoing.
4 SET_TXIR R/W 0h

Used to configure the infrared transceiver
0h = a) No action if UART_MDR2[7] = 0
b) TXIR pin output is forced low if UART_MDR2[7] = 1.
1h = IRTX pin output is forced high (not dependent on UART_MDR2[7] value).
3 IR_SLEEP R/W 0h

0h = IrDA/CIR sleep mode disabled
1h = IrDA/CIR sleep mode enabled
2-0 MODE_SELECT R/W 7h

0h = UART 16x mode
1h = SIR mode
2h = UART 16x auto-baud
3h = UART 13x mode
4h = MIR mode
5h = FIR mode
6h = CIR mode
7h = Disable (default state)

1.6.6.27 UART_MDR2 Register (Offset = 24h) [reset = 0h]

UART_MDR2 is shown in Figure 12-448 and described in Table 12-844.

Return to Summary Table.

Mode definition register 2
IR-IrDA and IR-CIR modes only. UART_MDR2[0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the trigger level for the frame status FIFO (8 entries) and must be programmed before the mode is programmed in UART_MDR1[2:0].
Note: The UART_MDR2[6] gives the flexibility to invert the RX pin in the UART to ensure that the protocol at the input of the transceiver module has the same polarity at module level. By default, the RX pin is inverted because most transceivers invert the IR receive pin.

Table 12-843 UART_MDR2 Instances
Instance Physical Address
UART0 0280 0024h
UART1 0281 0024h
UART2 0282 0024h
UART3 0283 0024h
UART4 0284 0024h
UART5 0285 0024h
UART6 0286 0024h
UART7 0287 0024h
UART8 0288 0024h
UART9 0289 0024h
MCU_UART0 40A0 0024h
WKUP_UART0 4230 0024h
Figure 12-448 UART_MDR2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
SET_TXIR_ALT IRRXINVERT CIR_PULSE_MODE UART_PULSE STS_FIFO_TRIG IRTX_UNDERRUN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-844 UART_MDR2 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 SET_TXIR_ALT R/W 0h

Provide alternate function for UART_MDR1[4] (SET_TXIR).
0h = Normal mode
1h = Alternate mode for SET_TXIR
6 IRRXINVERT R/W 0h

IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes.
0h = Inversion is performed.
1h = No inversion is performed.
5-4 CIR_PULSE_MODE R/W 0h

CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:
0h = Pulse width of 3 from 12 cycles
1h = Pulse width of 4 from 12 cycles
2h = Pulse width of 5 from 12 cycles
3h = Pulse width of 6 from 12 cycles
3 UART_PULSE R/W 0h

UART mode only. Allows pulse shaping in UART mode.
0h = Normal UART mode
1h = UART mode with a pulse shaping
2-1 STS_FIFO_TRIG R/W 0h

IR-IrDA mode only. Frame status FIFO threshold select:
0h = 1 entry
1h = 4 entries
2h = 7 entries
3h = 8 entries
0 IRTX_UNDERRUN R 0h

IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs, the meaning of the interrupt is:
Read 0h = The last bit of the frame transmitted successfully without error.
Read 1h = An underrun occurred. The last bit of the frame was transmitted but with an underrun error. The bit is reset to 0 when the UART_RESUME register is read.

1.6.6.28 UART_SFLSR Register (Offset = 28h) [reset = 0h]

UART_SFLSR is shown in Figure 12-449 and described in Table 12-846.

Return to Summary Table.

Status FIFO line status register
IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (UART_SFREGL and UART_SFREGH must be read first).

Table 12-845 UART_SFLSR Instances
Instance Physical Address
UART0 0280 0028h
UART1 0281 0028h
UART2 0282 0028h
UART3 0283 0028h
UART4 0284 0028h
UART5 0285 0028h
UART6 0286 0028h
UART7 0287 0028h
UART8 0288 0028h
UART9 0289 0028h
MCU_UART0 40A0 0028h
WKUP_UART0 4230 0028h
Figure 12-449 UART_SFLSR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED OE_ERROR FRAME_TOO_LONG_ERROR ABORT_DETECT CRC_ERROR RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-846 UART_SFLSR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-5 RESERVED R 0h
4 OE_ERROR R 0h

Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received
Note: Top of RX FIFO = Next frame to be read from RX FIFO
3 FRAME_TOO_LONG_ERROR R 0h

Read 1h = Frame-length too long error in frame at top of RX FIFO
2 ABORT_DETECT R 0h

Read 1h = Abort pattern detected in frame at top of RX FIFO
1 CRC_ERROR R 0h

Read 1h = CRC error in frame at top of RX FIFO
0 RESERVED R 0h

1.6.6.29 UART_TXFLL Register (Offset = 28h) [reset = 0h]

UART_TXFLL is shown in Figure 12-450 and described in Table 12-848.

Return to Summary Table.

Transmit frame length register low
IrDA modes only. The UART_TXFLL and UART_TXFLH registers hold the 13-bit transmit frame length (expressed in bytes). UART_TXFLL holds the LSBs and UART_TXFLH holds the MSBs. The frame length value is used if the frame length method of frame closing is used.

Table 12-847 UART_TXFLL Instances
Instance Physical Address
UART0 0280 0028h
UART1 0281 0028h
UART2 0282 0028h
UART3 0283 0028h
UART4 0284 0028h
UART5 0285 0028h
UART6 0286 0028h
UART7 0287 0028h
UART8 0288 0028h
UART9 0289 0028h
MCU_UART0 40A0 0028h
WKUP_UART0 4230 0028h
Figure 12-450 UART_TXFLL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TXFLL
R-0h W-0h
LEGEND: R = Read Only; W = Write Only; -n = value after reset
Table 12-848 UART_TXFLL Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 TXFLL W 0h

LSB register used to specify the frame length

1.6.6.30 UART_RESUME Register (Offset = 2Ch) [reset = 0h]

UART_RESUME is shown in Figure 12-451 and described in Table 12-850.

Return to Summary Table.

IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist and reads always as 0x00.

Table 12-849 UART_RESUME Instances
Instance Physical Address
UART0 0280 002Ch
UART1 0281 002Ch
UART2 0282 002Ch
UART3 0283 002Ch
UART4 0284 002Ch
UART5 0285 002Ch
UART6 0286 002Ch
UART7 0287 002Ch
UART8 0288 002Ch
UART9 0289 002Ch
MCU_UART0 40A0 002Ch
WKUP_UART0 4230 002Ch
Figure 12-451 UART_RESUME Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESUME
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-850 UART_RESUME Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 RESUME R 0h

Dummy read to restart the TX or RX

1.6.6.31 UART_TXFLH Register (Offset = 2Ch) [reset = 0h]

UART_TXFLH is shown in Figure 12-452 and described in Table 12-852.

Return to Summary Table.

Transmit frame length register high
IrDA modes only. The UART_TXFLL and UART_TXFLH registers hold the 13-bit transmit frame length (expressed in bytes). UART_TXFLL holds the LSBs and UART_TXFLH holds the MSBs. The frame length value is used if the frame length method of frame closing is used.

Table 12-851 UART_TXFLH Instances
Instance Physical Address
UART0 0280 002Ch
UART1 0281 002Ch
UART2 0282 002Ch
UART3 0283 002Ch
UART4 0284 002Ch
UART5 0285 002Ch
UART6 0286 002Ch
UART7 0287 002Ch
UART8 0288 002Ch
UART9 0289 002Ch
MCU_UART0 40A0 002Ch
WKUP_UART0 4230 002Ch
Figure 12-452 UART_TXFLH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED TXFLH
R-0h R-0h W-0h
LEGEND: R = Read Only; W = Write Only; -n = value after reset
Table 12-852 UART_TXFLH Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-5 RESERVED R 0h
4-0 TXFLH W 0h

MSB register used to specify the frame length

1.6.6.32 UART_SFREGL Register (Offset = 30h) [reset = 0h]

UART_SFREGL is shown in Figure 12-453 and described in Table 12-854.

Return to Summary Table.

Status FIFO register low
IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the UART_SFREGL and UART_SFREGH registers (these registers do not physically exist). The LSBs are read from UART_SFREGL and the MSBs are read from UART_SFREGH. Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the UART_SFLSR register.

Table 12-853 UART_SFREGL Instances
Instance Physical Address
UART0 0280 0030h
UART1 0281 0030h
UART2 0282 0030h
UART3 0283 0030h
UART4 0284 0030h
UART5 0285 0030h
UART6 0286 0030h
UART7 0287 0030h
UART8 0288 0030h
UART9 0289 0030h
MCU_UART0 40A0 0030h
WKUP_UART0 4230 0030h
Figure 12-453 UART_SFREGL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SFREGL
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-854 UART_SFREGL Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 SFREGL R 0h

LSB part of the frame length

1.6.6.33 UART_RXFLL Register (Offset = 30h) [reset = 0h]

UART_RXFLL is shown in Figure 12-454 and described in Table 12-856.

Return to Summary Table.

Received frame length register low
IrDA modes only. The UART_RXFLL and UART_RXFLH registers hold the 12-bit receive maximum frame length. UART_RXFLL holds the LSBs and UART_RXFLH holds the MSBs. If the intended maximum receive frame length is n bytes, program the UART_RXFLL and UART_RXFLH registers to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the result of frame format with CRC and stop flag; 2 bytes are associated with the FIR stop flag).

Table 12-855 UART_RXFLL Instances
Instance Physical Address
UART0 0280 0030h
UART1 0281 0030h
UART2 0282 0030h
UART3 0283 0030h
UART4 0284 0030h
UART5 0285 0030h
UART6 0286 0030h
UART7 0287 0030h
UART8 0288 0030h
UART9 0289 0030h
MCU_UART0 40A0 0030h
WKUP_UART0 4230 0030h
Figure 12-454 UART_RXFLL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RXFLL
R-0h W-0h
LEGEND: R = Read Only; W = Write Only; -n = value after reset
Table 12-856 UART_RXFLL Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 RXFLL W 0h

LSB register used to specify the frame length in reception

1.6.6.34 UART_SFREGH Register (Offset = 34h) [reset = 0h]

UART_SFREGH is shown in Figure 12-455 and described in Table 12-858.

Return to Summary Table.

Status FIFO register high
IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the UART_SFREGL and UART_SFREGH registers (these registers do not physically exist). The LSBs are read from UART_SFREGL and the MSBs are read from UART_SFREGH. Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the UART_SFLSR register.

Table 12-857 UART_SFREGH Instances
Instance Physical Address
UART0 0280 0034h
UART1 0281 0034h
UART2 0282 0034h
UART3 0283 0034h
UART4 0284 0034h
UART5 0285 0034h
UART6 0286 0034h
UART7 0287 0034h
UART8 0288 0034h
UART9 0289 0034h
MCU_UART0 40A0 0034h
WKUP_UART0 4230 0034h
Figure 12-455 UART_SFREGH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED SFREGH
R-0h R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-858 UART_SFREGH Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-4 RESERVED R 0h
3-0 SFREGH R 0h

MSB part of the frame length

1.6.6.35 UART_RXFLH Register (Offset = 34h) [reset = 0h]

UART_RXFLH is shown in Figure 12-456 and described in Table 12-860.

Return to Summary Table.

Received frame length register high
IrDA modes only. The UART_RXFLL and UART_RXFLH registers hold the 12-bit receive maximum frame length. UART_RXFLL holds the LSBs and UART_RXFLH holds the MSBs. If the intended maximum receive frame length is n bytes, program the UART_RXFLL and UART_RXFLH to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the result of frame format with CRC and stop flag; 2 bytes are associated with the FIR stop flag).

Table 12-859 UART_RXFLH Instances
Instance Physical Address
UART0 0280 0034h
UART1 0281 0034h
UART2 0282 0034h
UART3 0283 0034h
UART4 0284 0034h
UART5 0285 0034h
UART6 0286 0034h
UART7 0287 0034h
UART8 0288 0034h
UART9 0289 0034h
MCU_UART0 40A0 0034h
WKUP_UART0 4230 0034h
Figure 12-456 UART_RXFLH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED RXFLH
R-0h R-0h W-0h
LEGEND: R = Read Only; W = Write Only; -n = value after reset
Table 12-860 UART_RXFLH Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-4 RESERVED R 0h
3-0 RXFLH W 0h

MSB register used to specify the frame length in reception

1.6.6.36 UART_BLR Register (Offset = 38h) [reset = 40h]

UART_BLR is shown in Figure 12-457 and described in Table 12-862.

Return to Summary Table.

BOF control register
IrDA modes only. The UART_BLR[6] bit selects whether 0xC0 or 0xFF start patterns are to be used, when multiple start flags are required in SIR mode. If only one start flag is required, this is always 0xC0. If n start flags are required, (-1) 0xC0 or (-1) 0xFF flags are sent, followed by a single 0xC0 flag (immediately preceding the first data byte).

Table 12-861 UART_BLR Instances
Instance Physical Address
UART0 0280 0038h
UART1 0281 0038h
UART2 0282 0038h
UART3 0283 0038h
UART4 0284 0038h
UART5 0285 0038h
UART6 0286 0038h
UART7 0287 0038h
UART8 0288 0038h
UART9 0289 0038h
MCU_UART0 40A0 0038h
WKUP_UART0 4230 0038h
Figure 12-457 UART_BLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
STS_FIFO_RESET XBOF_TYPE RESERVED
R/W1S-0h R/W-1h R-0h
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset
Table 12-862 UART_BLR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 STS_FIFO_RESET R/W1S 0h

Status FIFO reset. This bit is self-clearing.
6 XBOF_TYPE R/W 1h

SIR xBOF select
0h = 0xFF
1h = 0xC0
5-0 RESERVED R 0h

1.6.6.37 UART_UASR Register (Offset = 38h) [reset = 0h]

UART_UASR is shown in Figure 12-458 and described in Table 12-864.

Return to Summary Table.

UART autobauding status register
UART autobauding mode only. This status register returns the speed, the number of bits by characters, and the type of the parity in UART autobauding mode. In autobauding mode, the input frequency of the UART modem must be fixed to 48 MHz. Any other module clock frequency results in incorrect baud rate recognition.
Note: When the UART is in autobauding mode, this register, instead of the UART_LCR, UART_DLL, and UART_DLH registers, is used to set up transmission according to the characteristics of the previous reception.
To reset the autobauding hardware (to start a new AT detection), set UART_MDR1[2:0] to 111 (reset value), then set UART_MDR1[2:1] to 010 (UART in autobaud mode).
To set the UART to standard mode (no autobaud), set UART_MDR1[2:1] to 000.

Table 12-863 UART_UASR Instances
Instance Physical Address
UART0 0280 0038h
UART1 0281 0038h
UART2 0282 0038h
UART3 0283 0038h
UART4 0284 0038h
UART5 0285 0038h
UART6 0286 0038h
UART7 0287 0038h
UART8 0288 0038h
UART9 0289 0038h
MCU_UART0 40A0 0038h
WKUP_UART0 4230 0038h
Figure 12-458 UART_UASR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
PARITY_TYPE BIT_BY_CHAR SPEED
R-0h R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-864 UART_UASR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-6 PARITY_TYPE R 0h

Read 0h = No parity identified
Read 1h = Parity space
Read 2h = Even parity
Read 3h = Odd parity
5 BIT_BY_CHAR R 0h

Read 0h = 7-bit character identified
Read 1h = 8-bit character identified
4-0 SPEED R 0h

Used to report the speed identified
Read 0h = No speed identified
Read 1h = 115,200 baud
Read 2h = 57,600 baud
Read 3h = 38,400 baud
Read 4h = 28,800 baud
Read 5h = 19,200 baud
Read 6h = 14,400 baud
Read 7h = 9,600 baud
Read 8h = 4,800 baud
Read 9h = 2,400 baud
Read Ah = 1,200 baud

1.6.6.38 UART_ACREG Register (Offset = 3Ch) [reset = 0h]

UART_ACREG is shown in Figure 12-459 and described in Table 12-866.

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Auxiliary control register. IR-IrDA and IR-CIR modes only.

Table 12-865 UART_ACREG Instances
Instance Physical Address
UART0 0280 003Ch
UART1 0281 003Ch
UART2 0282 003Ch
UART3 0283 003Ch
UART4 0284 003Ch
UART5 0285 003Ch
UART6 0286 003Ch
UART7 0287 003Ch
UART8 0288 003Ch
UART9 0289 003Ch
MCU_UART0 40A0 003Ch
WKUP_UART0 4230 003Ch
Figure 12-459 UART_ACREG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
PULSE_TYPE SD_MOD DIS_IR_RX DIS_TX_UNDERRUN SEND_SIP SCTX_EN ABORT_EN EOT_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W1S-0h R/W1S-0h R/W-0h R/W1S-0h
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset
Table 12-866 UART_ACREG Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 PULSE_TYPE R/W 0h

SIR pulse width select
0h = 3/16 of baud-rate pulse width
1h = 1.6 µs
6 SD_MOD R/W 0h

Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers.
0h = SD pin is set to high.
1h = SD pin is set to low.
5 DIS_IR_RX R/W 0h

0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)
1h = Disables RX input (permanent state - independent of transmit)
4 DIS_TX_UNDERRUN R/W 0h

It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting UART_ACREG[4] = 1, garbage data is sent over TX line.
0h = Long stop-bits cannot be transmitted; TX underrun is enabled.
1h = Long stop-bits can be transmitted; TX underrun is disabled.
3 SEND_SIP R/W1S 0h

MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission, the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission.
0h = No action
1h = Send SIP pulse.
2 SCTX_EN R/W1S 0h

Store and controlled TX start. When UART_MDR1[5] = 1 and the LH writes 1 to this bit, the TX state-machine starts frame transmission. This bit is self-clearing.
1 ABORT_EN R/W 0h

Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and UART_MDR1[5] = 1, UART IrDA starts a new transfer with data of the previous frame when the abort frame is sent. Therefore, TX FIFO must be reset before sending an abort frame.
0 EOT_EN R/W1S 0h

EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO).

1.6.6.39 UART_SCR Register (Offset = 40h) [reset = 0h]

UART_SCR is shown in Figure 12-460 and described in Table 12-868.

Return to Summary Table.

Supplementary control register
Note: Bit 4 enables the wake-up interrupt, but this interrupt is not mapped into the UART_IIR register. Therefore, when an interrupt occurs and there is no interrupt pending in the UART_IIR register, the UART_SSR[1] bit must be checked. To clear the wake-up interrupt, bit UART_SCR[4] must be reset to 0.

Table 12-867 UART_SCR Instances
Instance Physical Address
UART0 0280 0040h
UART1 0281 0040h
UART2 0282 0040h
UART3 0283 0040h
UART4 0284 0040h
UART5 0285 0040h
UART6 0286 0040h
UART7 0287 0040h
UART8 0288 0040h
UART9 0289 0040h
MCU_UART0 40A0 0040h
WKUP_UART0 4230 0040h
Figure 12-460 UART_SCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RX_TRIG_GRANU1 TX_TRIG_GRANU1 DSR_IT RX_CTS_DSR_WAKE_UP_ENABLE TX_EMPTY_CTL_IT DMA_MODE_2 DMA_MODE_CTL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-868 UART_SCR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 RX_TRIG_GRANU1 R/W 0h

0h = Disables the granularity of 1 for trigger RX level
1h = Enables the granularity of 1 for trigger RX level
6 TX_TRIG_GRANU1 R/W 0h

0h = Disables the granularity of 1 for trigger TX level
1h = Enables the granularity of 1 for trigger TX level
5 DSR_IT R/W 0h

0h = Disables DSR* interrupt
1h = Enables DSR* interrupt
4 RX_CTS_DSR_WAKE_UP_ENABLE R/W 0h

0h = Disables the wake-up interrupt and clears SSR[1]
1h = Waits for a falling edge of pins RX, CTS*, or DSR* to generate an interrupt
3 TX_EMPTY_CTL_IT R/W 0h

0h = Normal mode for THR interrupt
1h = The THR interrupt is generated when TX FIFO and TX shift register are empty.
2-1 DMA_MODE_2 R/W 0h

Used to specify the DMA mode valid if the UART_SCR[0] bit = 1
0h = DMA mode 0 (no DMA)
1h = DMA mode 1 (UART_nDMA_REQ[0] in TX, UART_nDMA_REQ[1] in RX)
2h = DMA mode 2 (UART_nDMA_REQ[0] in RX)
3h = DMA mode 3 (UART_nDMA_REQ[0] in TX)
0 DMA_MODE_CTL R/W 0h

0h = The DMA_MODE is set with UART_FCR[3].
1h = The DMA_MODE is set with UART_SCR[2:1].

1.6.6.40 UART_SSR Register (Offset = 44h) [reset = 4h]

UART_SSR is shown in Figure 12-461 and described in Table 12-870.

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Supplementary status register
Note: Bit 1 is reset only when UART_SCR[4] is reset to 0.

Table 12-869 UART_SSR Instances
Instance Physical Address
UART0 0280 0044h
UART1 0281 0044h
UART2 0282 0044h
UART3 0283 0044h
UART4 0284 0044h
UART5 0285 0044h
UART6 0286 0044h
UART7 0287 0044h
UART8 0288 0044h
UART9 0289 0044h
MCU_UART0 40A0 0044h
WKUP_UART0 4230 0044h
Figure 12-461 UART_SSR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED DMA_COUNTER_RST RX_CTS_DSR_WAKE_UP_STS TX_FIFO_FULL
R-0h R/W-1h R-0h R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-870 UART_SSR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-3 RESERVED R 0h
2 DMA_COUNTER_RST R/W 1h

0h = The DMA counter will not be reset if the corresponding FIFO is reset (through UART_FCR[1] or UART_FCR[2]).
1h = The DMA counter will be reset if corresponding FIFO is reset (through UART_FCR[1] or UART_FCR[2]).
1 RX_CTS_DSR_WAKE_UP_STS R 0h

Read 0h = No falling edge event on RX, CTS*, and DSR*
Read 1h = A falling edge occurred on RX, CTS*, or DSR*.
0 TX_FIFO_FULL R 0h

Read 0h = TX FIFO is not full.
Read 1h = TX FIFO is full.

1.6.6.41 UART_EBLR Register (Offset = 48h) [reset = 0h]

UART_EBLR is shown in Figure 12-462 and described in Table 12-872.

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BOF length register
IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation, this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore, to send only one BOF with no XBOF, this register must be set to 1. To send one BOF with N XBOF, this register must be set to N + 1. The value 0 sends 1 BOF plus 255 XBOF. In IR-IrDA MIR mode, this register specifies the number of additional start flags (MIR protocol mandates a minimum of 2 start flags). In IR-CIR mode, this register specifies the number of consecutive 0s to be received before generating the RX_STOP interrupt (UART_IIR[2]). All received 0s are stored in the RX FIFO. When the register is set to 0, this feature is deactivated and always in reception state, which can be disabled by setting the UART_ACREG[5] to 1.
Note: If the RX_STOP interrupt occurs before a byte boundary, the remaining bits of the last byte are filled with 0s and passed into the RX FIFO.

Table 12-871 UART_EBLR Instances
Instance Physical Address
UART0 0280 0048h
UART1 0281 0048h
UART2 0282 0048h
UART3 0283 0048h
UART4 0284 0048h
UART5 0285 0048h
UART6 0286 0048h
UART7 0287 0048h
UART8 0288 0048h
UART9 0289 0048h
MCU_UART0 40A0 0048h
WKUP_UART0 4230 0048h
Figure 12-462 UART_EBLR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EBLR
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-872 UART_EBLR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 EBLR R/W 0h

IR-IrDA mode: This register allows definition of up to 176 xBOFs, the maximum required by IrDA specification.
IR-CIR mode: This register specifies the number of consecutive 0s to be received before generating the RX_STOP interrupt (UART_IIR[2]).
00h = Feature disabled
01h = Generate RX_STOP interrupt after receiving one zero bit.
...
FFh = Generate RX_STOP interrupt after receiving 255 zero bits.

1.6.6.42 UART_MVR Register (Offset = 50h) [reset = 47424603h]

UART_MVR is shown in Figure 12-463 and described in Table 12-874.

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Module version register
The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned.

Table 12-873 UART_MVR Instances
Instance Physical Address
UART0 0280 0050h
UART1 0281 0050h
UART2 0282 0050h
UART3 0283 0050h
UART4 0284 0050h
UART5 0285 0050h
UART6 0286 0050h
UART7 0287 0050h
UART8 0288 0050h
UART9 0289 0050h
MCU_UART0 40A0 0050h
WKUP_UART0 4230 0050h
Figure 12-463 UART_MVR Register
31 30 29 28 27 26 25 24
SCHEME RESERVED FUNC
R-1h R-0h R-742h
23 22 21 20 19 18 17 16
FUNC
R-742h
15 14 13 12 11 10 9 8
RTL MAJOR
8h R-6h
7 6 5 4 3 2 1 0
CUSTOM MINOR
R-0h R-3h
LEGEND: R = Read Only; -n = value after reset
Table 12-874 UART_MVR Register Field Descriptions
Bit Field Type Reset Description
31-30 SCHEME R 1h

Scheme revision number of module
29-28 RESERVED R 0h
27-16 FUNC R 742h

Function revision number of module
15-11 RTL R 8h

Rtl revision number of module
10-8 MAJOR R 6h

Major revision number of the module
7-6 CUSTOM R 0h

Custom revision number of the module
5-0 MINOR R 3h

Minor revision number of the module

1.6.6.43 UART_SYSC Register (Offset = 54h) [reset = 0h]

UART_SYSC is shown in Figure 12-464 and described in Table 12-876.

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System configuration register
The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled, the clock is gated off until an OCP command for this device is detected. When the software reset bit is set high, it causes a full device reset.

Table 12-875 UART_SYSC Instances
Instance Physical Address
UART0 0280 0054h
UART1 0281 0054h
UART2 0282 0054h
UART3 0283 0054h
UART4 0284 0054h
UART5 0285 0054h
UART6 0286 0054h
UART7 0287 0054h
UART8 0288 0054h
UART9 0289 0054h
MCU_UART0 40A0 0054h
WKUP_UART0 4230 0054h
Figure 12-464 UART_SYSC Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED IDLEMODE ENAWAKEUP SOFTRESET AUTOIDLE
R-0h R/W-0h R/W-0h W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset
Table 12-876 UART_SYSC Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-5 RESERVED R 0h
4-3 IDLEMODE R/W 0h

Power management req/ack control ref: OCP Design Guidelines Version 1.1
0h = Force-idle: Idle request is acknowledged unconditionally.
1h = No-idle: Idle request is never acknowledged.
2h = Smart-idle: Idle request is acknowledged based in module internal activity.
3h = Smart-idle Wake-up: Acknowledgement to an idle request is given based in the internal activity of the module. The module is allowed to generate wake-up request.
2 ENAWAKEUP R/W 0h

Wake-up feature control
0h = Wakeup is disabled.
1h = Wake-up capability is enabled.
1 SOFTRESET W 0h

Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0.
0h = Normal mode
1h = The module is reset.
0 AUTOIDLE R/W 0h

Internal OCP clock gating strategy
0h = Clock is running.
1h = Automatic OCP clock gating strategy is applied, based on OCP interface activity

1.6.6.44 UART_SYSS Register (Offset = 58h) [reset = 0h]

UART_SYSS is shown in Figure 12-465 and described in Table 12-878.

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System status register

Table 12-877 UART_SYSS Instances
Instance Physical Address
UART0 0280 0058h
UART1 0281 0058h
UART2 0282 0058h
UART3 0283 0058h
UART4 0284 0058h
UART5 0285 0058h
UART6 0286 0058h
UART7 0287 0058h
UART8 0288 0058h
UART9 0289 0058h
MCU_UART0 40A0 0058h
WKUP_UART0 4230 0058h
Figure 12-465 UART_SYSS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESETDONE
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-878 UART_SYSS Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-1 RESERVED R 0h
0 RESETDONE R 0h

Internal reset monitoring
Read 0h = Internal module reset is ongoing.
Read 1h = Reset complete

1.6.6.45 UART_WER Register (Offset = 5Ch) [reset = FFh]

UART_WER is shown in Figure 12-466 and described in Table 12-880.

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Wake-up enable register
The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require the system to wake up. Even if the wakeup is disabled for certain events, if these events are also an interrupt to the UART, the UART registers the interrupt.

Table 12-879 UART_WER Instances
Instance Physical Address
UART0 0280 005Ch
UART1 0281 005Ch
UART2 0282 005Ch
UART3 0283 005Ch
UART4 0284 005Ch
UART5 0285 005Ch
UART6 0286 005Ch
UART7 0287 005Ch
UART8 0288 005Ch
UART9 0289 005Ch
MCU_UART0 40A0 005Ch
WKUP_UART0 4230 005Ch
Figure 12-466 UART_WER Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
EVENT_7_TX_WAKEUP_EN EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT EVENT_5_RHR_INTERRUPT EVENT_4_RX_ACTIVITY EVENT_3_DCD_CD_ACTIVITY EVENT_2_RI_ACTIVITY EVENT_1_DSR_ACTIVITY EVENT_0_CTS_ACTIVITY
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-880 UART_WER Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 EVENT_7_TX_WAKEUP_EN R/W 1h

0h = Event is not allowed to wake up the system.
1h = Event can wake up the system: it can be THR_IT or TX_DMA request and/or TX_STATUS_IT.
6 EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT R/W 1h

0h = Event is not allowed to wake up the system.
1h = Event can wake up the system.
5 EVENT_5_RHR_INTERRUPT R/W 1h

0h = Event is not allowed to wake up the system.
1h = Event can wake up the system.
4 EVENT_4_RX_ACTIVITY R/W 1h

0h = Event is not allowed to wake up the system.
1h = Event can wake up the system.
3 EVENT_3_DCD_CD_ACTIVITY R/W 1h

0h = Event is not allowed to wake up the system
1h = Event can wake up the system
2 EVENT_2_RI_ACTIVITY R/W 1h

0h = Event is not allowed to wake up the system.
1h = Event can wake up the system.
1 EVENT_1_DSR_ACTIVITY R/W 1h

0h = Event is not allowed to wake up the system.
1h = Event can wake up the system.
0 EVENT_0_CTS_ACTIVITY R/W 1h

0h = Event is not allowed to wake up the system.
1h = Event can wake up the system.

1.6.6.46 UART_CFPS Register (Offset = 60h) [reset = 69h]

UART_CFPS is shown in Figure 12-467 and described in Table 12-882.

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Carrier frequency prescaler
Because the consumer IR works at modulation rates of 30 to 56.8 kHz, the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote-control requirements in baud multiples of 12x. The value of the CFPS at reset is 0105 decimal, which equals 38.1 kHz output from starting conditions. The 48-MHz carrier is prescaled by the CFPS, which is then divided by the 12x baud multiple.

Table 12-881 UART_CFPS Instances
Instance Physical Address
UART0 0280 0060h
UART1 0281 0060h
UART2 0282 0060h
UART3 0283 0060h
UART4 0284 0060h
UART5 0285 0060h
UART6 0286 0060h
UART7 0287 0060h
UART8 0288 0060h
UART9 0289 0060h
MCU_UART0 40A0 0060h
WKUP_UART0 4230 0060h
Figure 12-467 UART_CFPS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CFPS
R-0h R/W-69h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-882 UART_CFPS Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 CFPS R/W 69h

System clock frequency prescaler at (12x multiple). Examples for CFPS values:
85h = 30 kHz Target Freq; 30.08 kHz Actual Freq
7Ah = 32.75 kHz Target Freq; 32.79 kHz Actual Freq
6Fh = 36 kHz Target Freq; 36.04 kHz Actual Freq
6Dh = 36.7 kHz Target Freq; 36.69 kHz Actual Freq
69h = 38 kHz Target Freq; 38.1 kHz Actual Freq
64h = 40 kHz Target Freq; 40 kHz Actual Freq
46h = 56.8 kHz Target Freq; 57.14 kHz Actual Freq
Note: CFPS = 0 is not supported.

1.6.6.47 UART_RXFIFO_LVL Register (Offset = 64h) [reset = 0h]

UART_RXFIFO_LVL is shown in Figure 12-468 and described in Table 12-884.

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Level of the RX FIFO

Table 12-883 UART_RXFIFO_LVL Instances
Instance Physical Address
UART0 0280 0064h
UART1 0281 0064h
UART2 0282 0064h
UART3 0283 0064h
UART4 0284 0064h
UART5 0285 0064h
UART6 0286 0064h
UART7 0287 0064h
UART8 0288 0064h
UART9 0289 0064h
MCU_UART0 40A0 0064h
WKUP_UART0 4230 0064h
Figure 12-468 UART_RXFIFO_LVL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RXFIFO_LVL
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-884 UART_RXFIFO_LVL Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 RXFIFO_LVL R 0h

Shows the number of received bytes in the RX FIFO

1.6.6.48 UART_TXFIFO_LVL Register (Offset = 68h) [reset = 0h]

UART_TXFIFO_LVL is shown in Figure 12-469 and described in Table 12-886.

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Level of the TX FIFO

Table 12-885 UART_TXFIFO_LVL Instances
Instance Physical Address
UART0 0280 0068h
UART1 0281 0068h
UART2 0282 0068h
UART3 0283 0068h
UART4 0284 0068h
UART5 0285 0068h
UART6 0286 0068h
UART7 0287 0068h
UART8 0288 0068h
UART9 0289 0068h
MCU_UART0 40A0 0068h
WKUP_UART0 4230 0068h
Figure 12-469 UART_TXFIFO_LVL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TXFIFO_LVL
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-886 UART_TXFIFO_LVL Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 TXFIFO_LVL R 0h

Shows the number of written bytes in the TX FIFO

1.6.6.49 UART_IER2 Register (Offset = 6Ch) [reset = 0h]

UART_IER2 is shown in Figure 12-470 and described in Table 12-888.

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Enables RX/TX FIFOs empty corresponding interrupts

Table 12-887 UART_IER2 Instances
Instance Physical Address
UART0 0280 006Ch
UART1 0281 006Ch
UART2 0282 006Ch
UART3 0283 006Ch
UART4 0284 006Ch
UART5 0285 006Ch
UART6 0286 006Ch
UART7 0287 006Ch
UART8 0288 006Ch
UART9 0289 006Ch
MCU_UART0 40A0 006Ch
WKUP_UART0 4230 006Ch
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Figure 12-470 UART_IER2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RHR_IT_DIS EN_TXFIFO_EMPTY EN_RXFIFO_EMPTY
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-888 UART_IER2 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-3 RESERVED R 0h
1 EN_TXFIFO_EMPTY R/W 0h

Enables TX FIFO empty corresponding interrupt
0h = Disables EN_TXFIFO_EMPTY interrupt
1h = Enables EN_TXFIFO_EMPTY interrupt
0 EN_RXFIFO_EMPTY R/W 0h

Enables RX FIFO empty corresponding interrupt
0h = Disables EN_RXFIFO_EMPTY interrupt
1h = Enables EN_RXFIFO_EMPTY interrupt

1.6.6.50 UART_ISR2 Register (Offset = 70h) [reset = 3h]

UART_ISR2 is shown in Figure 12-471 and described in Table 12-890.

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Status of RX/TX FIFOs empty corresponding interrupts

Table 12-889 UART_ISR2 Instances
Instance Physical Address
UART0 0280 0070h
UART1 0281 0070h
UART2 0282 0070h
UART3 0283 0070h
UART4 0284 0070h
UART5 0285 0070h
UART6 0286 0070h
UART7 0287 0070h
UART8 0288 0070h
UART9 0289 0070h
MCU_UART0 40A0 0070h
WKUP_UART0 4230 0070h
Figure 12-471 UART_ISR2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED TXFIFO_EMPTY_STS RXFIFO_EMPTY_STS
R-0h R/W1C-1h R/W1C-1h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-890 UART_ISR2 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-2 RESERVED R 0h
1 TXFIFO_EMPTY_STS R/W1C 1h

Used to generate interrupt if the TX_FIFO is empty (software flow control)
0h = TXFIFO_EMPTY interrupt not pending.
1h = TXFIFO_EMPTY interrupt pending.
0 RXFIFO_EMPTY_STS R/W1C 1h

Used to generate interrupt if the RX_FIFO is empty (software flow control)
0h = RXFIFO_EMPTY interrupt not pending.
1h = RXFIFO_EMPTY interrupt pending.

1.6.6.51 UART_FREQ_SEL Register (Offset = 74h) [reset = 1Ah]

UART_FREQ_SEL is shown in Figure 12-472 and described in Table 12-892.

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Sample per bit selector

Table 12-891 UART_FREQ_SEL Instances
Instance Physical Address
UART0 0280 0074h
UART1 0281 0074h
UART2 0282 0074h
UART3 0283 0074h
UART4 0284 0074h
UART5 0285 0074h
UART6 0286 0074h
UART7 0287 0074h
UART8 0288 0074h
UART9 0289 0074h
MCU_UART0 40A0 0074h
WKUP_UART0 4230 0074h
Figure 12-472 UART_FREQ_SEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FREQ_SEL
R-0h R/W-1Ah
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-892 UART_FREQ_SEL Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h

RESERVED
7-0 FREQ_SEL R/W 1Ah

Sets the sample per bit if nondefault frequency is used. UART_MDR3[1] must be set to 1 after this value is set. Must be equal to or higher than 6.

1.6.6.52 UART_ABAUD_1ST_CHAR Register (Offset = 78h) [reset = 0h]

UART_ABAUD_1ST_CHAR is shown in Figure 12-473 and described in Table 12-894.

Return to Summary Table.

Unused

Table 12-893 UART_ABAUD_1ST_CHAR Instances
Instance Physical Address
UART0 0280 0078h
UART1 0281 0078h
UART2 0282 0078h
UART3 0283 0078h
UART4 0284 0078h
UART5 0285 0078h
UART6 0286 0078h
UART7 0287 0078h
UART8 0288 0078h
UART9 0289 0078h
MCU_UART0 40A0 0078h
WKUP_UART0 4230 0078h
Figure 12-473 UART_ABAUD_1ST_CHAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-894 UART_ABAUD_1ST_CHAR Register Field Descriptions
Bit Field Type Reset Description
31-0 RESERVED R 0h

1.6.6.53 UART_BAUD_2ND_CHAR Register (Offset = 7Ch) [reset = 0h]

UART_BAUD_2ND_CHAR is shown in Figure 12-474 and described in Table 12-896.

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Unused

Table 12-895 UART_BAUD_2ND_CHAR Instances
Instance Physical Address
UART0 0280 007Ch
UART1 0281 007Ch
UART2 0282 007Ch
UART3 0283 007Ch
UART4 0284 007Ch
UART5 0285 007Ch
UART6 0286 007Ch
UART7 0287 007Ch
UART8 0288 007Ch
UART9 0289 007Ch
MCU_UART0 40A0 007Ch
WKUP_UART0 4230 007Ch
Figure 12-474 UART_BAUD_2ND_CHAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-896 UART_BAUD_2ND_CHAR Register Field Descriptions
Bit Field Type Reset Description
31-0 RESERVED R 0h

1.6.6.54 UART_MDR3 Register (Offset = 80h) [reset = 0h]

UART_MDR3 is shown in Figure 12-475 and described in Table 12-898.

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Mode definition register 3

Table 12-897 UART_MDR3 Instances
Instance Physical Address
UART0 0280 0080h
UART1 0281 0080h
UART2 0282 0080h
UART3 0283 0080h
UART4 0284 0080h
UART5 0285 0080h
UART6 0286 0080h
UART7 0287 0080h
UART8 0288 0080h
UART9 0289 0080h
MCU_UART0 40A0 0080h
WKUP_UART0 4230 0080h
Figure 12-475 UART_MDR3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED DIR_EN DIR_POL SET_DMA_TX_THRESHOLD NONDEFAULT_FREQ DISABLE_CIR_RX_DEMOD
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-898 UART_MDR3 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-5 RESERVED R 0h

Reserved
4 DIR_EN R/W 0h

RS-485 External Transceiver Direction Enable
3 DIR_POL R/W 0h RS-485 External Transceiver Direction Polarity.
0h = TX: RTS=0, RX: RTS=1.
1h = TX: RTS=1, RX: RTS=0
2 SET_DMA_TX_THRESHOLD R/W 0h

Enable to set different TXDMA threshold in UART_TX_DMA_THRESHOLD register.
1 NONDEFAULT_FREQ R/W 0h

Used to enable the NONDEFAULT fclk frequencies.
0h = Disables using NONDEFAULT fclk frequencies.
1h = Enables using NONDEFAULT fclk frequencies (set UART_FREQ_SEL and UART_DLH/UART_DLL).
0 DISABLE_CIR_RX_DEMOD R/W 0h

Used to enable CIR RX demodulation.
0h = Enables CIR RX demodulation.
1h = Disables CIR RX demodulation.

1.6.6.55 UART_TX_DMA_THRESHOLD Register (Offset = 84h) [reset = 0h]

UART_TX_DMA_THRESHOLD is shown in Figure 12-476 and described in Table 12-900.

Return to Summary Table.

Use to manually set the TX DMA threshold level. UART_MDR3[2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register.

Table 12-899 UART_TX_DMA_THRESHOLD Instances
Instance Physical Address
UART0 0280 0084h
UART1 0281 0084h
UART2 0282 0084h
UART3 0283 0084h
UART4 0284 0084h
UART5 0285 0084h
UART6 0286 0084h
UART7 0287 0084h
UART8 0288 0084h
UART9 0289 0084h
MCU_UART0 40A0 0084h
WKUP_UART0 4230 0084h
Figure 12-476 UART_TX_DMA_THRESHOLD Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED TX_DMA_THRESHOLD
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-900 UART_TX_DMA_THRESHOLD Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-6 RESERVED R 0h
5-0 TX_DMA_THRESHOLD R/W 0h

Used to manually set the TX DMA threshold level

1.6.6.56 UART_MDR4 Register (Offset = 88h) [reset = 0h]

UART_MDR4 is shown in Figure 12-477 and described in Table 12-902.

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Mode definition register 4

Table 12-901 UART_MDR4 Instances
Instance Physical Address
UART0 0280 0088h
UART1 0281 0088h
UART2 0282 0088h
UART3 0283 0088h
UART4 0284 0088h
UART5 0285 0088h
UART6 0286 0088h
UART7 0287 0088h
UART8 0288 0088h
UART9 0289 0088h
MCU_UART0 40A0 0088h
WKUP_UART0 4230 0088h
Figure 12-477 UART_MDR4 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED MODE9 FREQ_SEL_H MODE
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-902 UART_MDR4 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 RESERVED R 0h
6 MODE9 R/W 0h
9-bit character length When '1', overrides character length setting in UART_LCR
5-3 FREQ_SEL_H R/W 0h

Upper 3 bits of UART_FREQ_SEL register for higher division values, as required for example for FI/Di in ISO7816 mode
2-0 MODE R/W 0h

New modes [when set, overrides UART_MDR1 modes]

0h = Disabled (no override)

1h = Reserved

2h = Synchronous mode with external clock

3h = Synchronous mode with generated clock

4h = ISO 7816 mode T=0

5h = ISO 7816 mode T=1

6h = Reserved

7h = Reserved

1.6.6.57 UART_EFR2 Register (Offset = 8Ch) [reset = 0h]

UART_EFR2 is shown in Figure 12-478 and described in Table 12-904.

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Enhanced Features Register 2

Table 12-903 UART_EFR2 Instances
Instance Physical Address
UART0 0280 008Ch
UART1 0281 008Ch
UART2 0282 008Ch
UART3 0283 008Ch
UART4 0284 008Ch
UART5 0285 008Ch
UART6 0286 008Ch
UART7 0287 008Ch
UART8 0288 008Ch
UART9 0289 008Ch
MCU_UART0 40A0 008Ch
WKUP_UART0 4230 008Ch
Figure 12-478 UART_EFR2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
BROADCAST TIMEOUT_BEHAVE C8 C4 C2 MULTIDROP RHR_OVERRUN ENDIAN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-904 UART_EFR2 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 BROADCAST R/W 0h

Enables broadcast address matching in multi-drop address match mode
6 TIMEOUT_BEHAVE R/W 0h

Specifies how timeout is measured

0h = Timeout after at least one character has been received

1h = Periodic timeout even when no character has been received
5 C8 R/W 0h

Value for ISO 7816 C8 pin for software control
4 C4 R/W 0h

Value for ISO 7816 C4 pin for software control
3 C2 R/W 0h

Value for ISO 7816 reset pin [software controllable]
2 MULTIDROP R/W 0h

Enables parity Multi-drop mode [overrides UART_LCR[5..3]] when '1'
1 RHR_OVERRUN R/W 0h

UART_RHR Overrun behavior when buffer full

0h = Data in RHR is not overwritten (standard)

1h = Data in RHR is overwritten when buffer full (and FIFO disabled)
0 ENDIAN R/W 0h

Endianness

0h = Little Endian (LSB First)

1h = Big Endian (MSB First)

1.6.6.58 UART_ECR Register (Offset = 90h) [reset = 18h]

UART_ECR is shown in Figure 12-479 and described in Table 12-906.

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Enhanced Control register

Table 12-905 UART_ECR Instances
Instance Physical Address
UART0 0280 0090h
UART1 0281 0090h
UART2 0282 0090h
UART3 0283 0090h
UART4 0284 0090h
UART5 0285 0090h
UART6 0286 0090h
UART7 0287 0090h
UART8 0288 0090h
UART9 0289 0090h
MCU_UART0 40A0 0090h
WKUP_UART0 4230 0090h
Figure 12-479 UART_ECR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CLEAR_TX_PE TX_EN RX_EN TX_RST RX_RST A_MULTIDROP
R-0h W-0h R/W-1h R/W-1h W-0h W-0h W-0h
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset
Table 12-906 UART_ECR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-6 RESERVED R 0h
5 CLEAR_TX_PE W 0h

Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]
4 TX_EN R/W 1h

Enables/Disables the transmitter

0h = DISABLED (Transmitter is shut down)

1h = ENABLED (Transmitter is working)
3 RX_EN R/W 1h

Enables/Disables the receiver

0h = DISABLED (Receiver is shut down)

1h = ENABLED (Receiver is operating)
2 TX_RST W 0h

Writing 1h = resets the transmitter
1 RX_RST W 0h

Writing 1h = resets the receiver
0 A_MULTIDROP W 0h

In multi-drop mode, when written with the value '1' causes the next byte written into UART_THR to be transmitted with the parity bit set, signaling an address

1.6.6.59 UART_TIMEGUARD Register (Offset = 94h) [reset = 0h]

UART_TIMEGUARD is shown in Figure 12-480 and described in Table 12-908.

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Timeguard

Table 12-907 UART_TIMEGUARD Instances
Instance Physical Address
UART0 0280 0094h
UART1 0281 0094h
UART2 0282 0094h
UART3 0283 0094h
UART4 0284 0094h
UART5 0285 0094h
UART6 0286 0094h
UART7 0287 0094h
UART8 0288 0094h
UART9 0289 0094h
MCU_UART0 40A0 0094h
WKUP_UART0 4230 0094h
Figure 12-480 UART_TIMEGUARD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TIMEGUARD
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-908 UART_TIMEGUARD Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 TIMEGUARD R/W 0h

Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes, useful when comunicating with slower devices

1.6.6.60 UART_TIMEOUTL Register (Offset = 98h) [reset = 0h]

UART_TIMEOUTL is shown in Figure 12-481 and described in Table 12-910.

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Timeout lower byte

Table 12-909 UART_TIMEOUTL Instances
Instance Physical Address
UART0 0280 0098h
UART1 0281 0098h
UART2 0282 0098h
UART3 0283 0098h
UART4 0284 0098h
UART5 0285 0098h
UART6 0286 0098h
UART7 0287 0098h
UART8 0288 0098h
UART9 0289 0098h
MCU_UART0 40A0 0098h
WKUP_UART0 4230 0098h
Figure 12-481 UART_TIMEOUTL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TIMEOUT_L
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-910 UART_TIMEOUTL Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 TIMEOUT_L R/W 0h

Custom timeout period in baud clocks, to override the internal value, when different from 0 [Lower byte of the 16 bit value]

1.6.6.61 UART_TIMEOUTH Register (Offset = 9Ch) [reset = 0h]

UART_TIMEOUTH is shown in Figure 12-482 and described in Table 12-912.

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Timeout higher byte

Table 12-911 UART_TIMEOUTH Instances
Instance Physical Address
UART0 0280 009Ch
UART1 0281 009Ch
UART2 0282 009Ch
UART3 0283 009Ch
UART4 0284 009Ch
UART5 0285 009Ch
UART6 0286 009Ch
UART7 0287 009Ch
UART8 0288 009Ch
UART9 0289 009Ch
MCU_UART0 40A0 009Ch
WKUP_UART0 4230 009Ch
Figure 12-482 UART_TIMEOUTH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TIMEOUT_H
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-912 UART_TIMEOUTH Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 TIMEOUT_H R/W 0h

Custom timeout period in baud clocks, to override the internal value, when different from 0 [Higher byte of the 16 bit value]

1.6.6.62 UART_SCCR Register (Offset = A0h) [reset = 7h]

UART_SCCR is shown in Figure 12-483 and described in Table 12-914.

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Smartcard (ISO7816) mode Control Register

Table 12-913 UART_SCCR Instances
Instance Physical Address
UART0 0280 00A0h
UART1 0281 00A0h
UART2 0282 00A0h
UART3 0283 00A0h
UART4 0284 00A0h
UART5 0285 00A0h
UART6 0286 00A0h
UART7 0287 00A0h
UART8 0288 00A0h
UART9 0289 00A0h
MCU_UART0 40A0 00A0h
WKUP_UART0 4230 00A0h
Figure 12-483 UART_SCCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
DSNACK INACK RESERVED MAX_ITERATION
R/W-0h R/W-0h R-0h R/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-914 UART_SCCR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 DSNACK R/W 0h

Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned, the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it
6 INACK R/W 0h

Inhibit NACK when receiving, even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it
5-3 RESERVED R 0h
2-0 MAX_ITERATION R/W 7h

Number of times to repeat transmitted character, if the receiver did not acknowledge If not acknowledged after the max value is reached, the UART transmitter will set parity error, stop and not continue until it is cleared

1.6.6.63 UART_ERHR Register (Offset = A4h) [reset = 0h]

UART_ERHR is shown in Figure 12-484 and described in Table 12-916.

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Extended Receive Holding Register

Table 12-915 UART_ERHR Instances
Instance Physical Address
UART0 0280 00A4h
UART1 0281 00A4h
UART2 0282 00A4h
UART3 0283 00A4h
UART4 0284 00A4h
UART5 0285 00A4h
UART6 0286 00A4h
UART7 0287 00A4h
UART8 0288 00A4h
UART9 0289 00A4h
MCU_UART0 40A0 00A4h
WKUP_UART0 4230 00A4h
Figure 12-484 UART_ERHR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERHR
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-916 UART_ERHR Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R 0h
8-0 ERHR R 0h

Extended Receive Holding Register - allows accessing the full 9bit UART_RHR

1.6.6.64 UART_ETHR Register (Offset = A4h) [reset = 0h]

UART_ETHR is shown in Figure 12-485 and described in Table 12-918.

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Extended Transmit Holding Register

Table 12-917 UART_ETHR Instances
Instance Physical Address
UART0 0280 00A4h
UART1 0281 00A4h
UART2 0282 00A4h
UART3 0283 00A4h
UART4 0284 00A4h
UART5 0285 00A4h
UART6 0286 00A4h
UART7 0287 00A4h
UART8 0288 00A4h
UART9 0289 00A4h
MCU_UART0 40A0 00A4h
WKUP_UART0 4230 00A4h
Figure 12-485 UART_ETHR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ETHR
R-0h W-0h
LEGEND: R = Read Only; W = Write Only; -n = value after reset
Table 12-918 UART_ETHR Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R 0h
8-0 ETHR W 0h

Extended Transmit Holding Register - allows writing the full 9bit UART_RHR

1.6.6.65 UART_MAR Register (Offset = A8h) [reset = 0h]

UART_MAR is shown in Figure 12-486 and described in Table 12-920.

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Multidrop Address Register

Table 12-919 UART_MAR Instances
Instance Physical Address
UART0 0280 00A8h
UART1 0281 00A8h
UART2 0282 00A8h
UART3 0283 00A8h
UART4 0284 00A8h
UART5 0285 00A8h
UART6 0286 00A8h
UART7 0287 00A8h
UART8 0288 00A8h
UART9 0289 00A8h
MCU_UART0 40A0 00A8h
WKUP_UART0 4230 00A8h
Figure 12-486 UART_MAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADDRESS
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-920 UART_MAR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 ADDRESS R/W 0h

Multidrop match address value

1.6.6.66 UART_MMR Register (Offset = ACh) [reset = 0h]

UART_MMR is shown in Figure 12-487 and described in Table 12-922.

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Multidrop Mask Register

Table 12-921 UART_MMR Instances
Instance Physical Address
UART0 0280 00ACh
UART1 0281 00ACh
UART2 0282 00ACh
UART3 0283 00ACh
UART4 0284 00ACh
UART5 0285 00ACh
UART6 0286 00ACh
UART7 0287 00ACh
UART8 0288 00ACh
UART9 0289 00ACh
MCU_UART0 40A0 00ACh
WKUP_UART0 4230 00ACh
Figure 12-487 UART_MMR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MASK
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-922 UART_MMR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 MASK R/W 0h

Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching

1.6.6.67 UART_MBR Register (Offset = B0h) [reset = 0h]

UART_MBR is shown in Figure 12-488 and described in Table 12-924.

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Multidrop Broadcast Address Register

Table 12-923 UART_MBR Instances
Instance Physical Address
UART0 0280 00B0h
UART1 0281 00B0h
UART2 0282 00B0h
UART3 0283 00B0h
UART4 0284 00B0h
UART5 0285 00B0h
UART6 0286 00B0h
UART7 0287 00B0h
UART8 0288 00B0h
UART9 0289 00B0h
MCU_UART0 40A0 00B0h
WKUP_UART0 4230 00B0h
Figure 12-488 UART_MBR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED BROADCAST_ADDRESS
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-924 UART_MBR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 BROADCAST_ADDRESS R/W 0h

Broadcast address for address matching