SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Each A72SS has its own power domain, see Table 5-1345. Each (PD_A72_Cluster_i) of these power domains can be transitioned independently. See Figure 5-659 for the power states of the A72SS.
If at least one ARMi_COREn is ON, the respective CC_ARMSS power domain has to be ON. The sequencing shall ensure that all cores except Core 0 are powered down (in ARMi_COREn_ISO or ARMi_COREn_OFF state) and CORE 0 is in ARMi_CORE0_RESET state before respective CC_ARMSS domain can be powered down.
For more information about the Arm A72 cluster transitions among the power states, see Power Management Section in Arm® Cortex®-A72 MPCore Processor Technical Reference Manual, available at http://infocenter.arm.com/help/index.jsp.