SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This register contains the type, direction, and transaction ID of the transaction error that was captured.
Bits | Field | Type | Reset | Description |
---|---|---|---|---|
31:28 | Reserved | r | 0x0 | Reserved. Read as 0. |
27:16 | rid | r | 0x0 |
Route ID – This indicates the Route ID of the captured transaction |
15:12 | Reserved | r | 0x0 | Reserved. Read as 0. |
11:8 | oid | r | 0x0 | Order ID – This indicates the Order ID of the capture transaction |
7:4 | Reserved | r | 0x0 | Reserved. Read as 0. |
2 | dir | r | 0x0 |
Direction – This indicates whether the captured transaction was a read or a write 0 – Write 1 – Read |
1 | type | r | 0x0 |
Type – This indicates what type of error these registers contain information about 0 – Transaction Timeout 1 – Unexpected Response |
0 | valid | r | 0x0 |
If this field is a 1, then the contents of this and the below registers is considered valid. I.e. it contains the information about the transaction that was captured. If this field is 0 then this and the other listed registers are not valid. This is because there is either no error pending, or the error pending did not have any captured information because there was an error pending in front of it that had already captured information.
|