SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The SPI boot mode supports the 1S-1S-1S mode only (Bit-width =1, Single Data Rate). The Command and Address issued are 8 bits and 24 bits, respectively. The Read Command issued for SPI is 0x03, followed by zero for address and 0 dummy cycles.The frequency of operation supported is 4.156 MHz.
The following boot mode pin configuration and corresponding pin usage and mux configuration are shown below. This is the SPI Port 0 boot mode.
9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Rsvd (not for boot use) | Rsvd | MCU Only | Primary Boot Mode A | PLL Config | |||||
X | X | X | X | 0 | 1 | 1 | X | X | X |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Backup Boot Mode Config | Primary Boot Mode Config | Backup Boot Mode | Primary Boot B | ||||
X | X/0* | X | X | X | X | X | X/0* |
Primary boot mode B and Primary Boot Mode Config 6 must be set to 0 if MCU only is set to 0.
Table 4-21 shows configuration pins assignment to functions when boot mode is the SPI on OSPI port mode.
The SPI bus will be run at 4.156 MHz.
BOOTMODE Pins | Field | Value | Description | MCU Only=1 Value |
---|---|---|---|---|
6 (7)(1) | Port | 0 | Port 0 | 0 |
1 | Reserved | |||
5 | Mode | 0 | SPI Mode 0 | 0 |
1 | SPI Mode 3 | |||
4 | Csel | 0 | Boot Flash is on CS 0 | 0 |
1 | Boot Flash is on CS 1 |
Table 4-22 summarizes the OSPI pin configuration done by ROM code for SPI boot device on port 0.
Device Pin | Module Signal | Pull Enable | Pull Direction | Driver Index | Rx En/Dis | Tx En/Dis | Pinmux Sel |
---|---|---|---|---|---|---|---|
MCU_OSPI0_CLK0 | MCU_OSPI0_CLK | Disable | Up | 0 | Disable | Enable | 0 |
MCU_OSPI0_LBCLKO | MCU_OSPI0_LBCLKO | Disable | Up | 0 | Enable | Enable | 0 |
MCU_OSPI0_DQS | MCU_OSPI0_DQS | Disable | Up | 0 | Enable | Disable | 0 |
MCU_OSPI0_D0 | MCU_OSPI0_D0 | Enable | Up | 0 | Enable | Enable | 0 |
MCU_OSPI0_D1 | MCU_OSPI0_D1 | Enable | Up | 0 | Enable | Enable | 0 |
MCU_OSPI0_CSn0 | MCU_OSPI0_CSn0 | Enable | Up | 0 | Disable | Enable | 0 |
MCU_OSPI0_CSn1 | MCU_OSPI0_CSn1 | Enable | Up | 0 | Disable | Enable | 0 |